Abstract: A method and system for providing simulation of an integrated circuit during development of the integrated circuit is disclosed. The integrated circuit has an island that includes an interface. The method and system include a snooper, a checker and a generator. The snooper is coupled with an interface and is for obtaining an output provided by the island during simulation. The checker is coupled with an interface and is for checking the output to determine whether the output is a desired output. The generator is coupled with an interface and is for providing an input to the interface during simulation. The generator is coupled with a test case that directs the generator.

Abstract: Techniques and systems for debugging an electronic system having instrumentation circuitry included therein are disclosed. The techniques and systems facilitate analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the invention enables the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.

Abstract: This debugging method exhaustively analyzes the impact of any set of given interrelated signal values in a digital circuit on the circuit's ability to satisfy a set of functional expectations. It accomplishes this automatically by inspecting paths in a binary decision diagram representation of the logical relationship between the signal values in the circuit. As the result, it is able to list all combinations of desirable values on these given signals, and therefore it can conclusively identify which signals are irrelevant and which signals are always involved while other signals are involved under certain known conditions.

Abstract: A method and system for evaluating performance level models of electronic systems having both hardware and software components is provided. The system and method allow for the simplified implementation and testing of several different architectural designs for compliance with the desired operational requirement of a designed electronic system.

Abstract: A method to convert a wire layout geometry to a filament topology for determination of chip resistance is provided. The method includes resolving overlap of layout segments of the wire layout geometry and inserting a vertical filament into each of the layout segments. The method further includes connecting vertical filaments using lateral connections and merging connected parallel filaments. The method also includes removing open filaments and modifying the filament structure in a bend region based on relative dimensions of the vertical filaments within the bend region.

Abstract: A noise countermeasure determination method includes the steps of calculating recommended circuit information considered to minimize a noise by use of at least one formula, based on input circuit information amounting to at least one net of a target circuit which is to be subjected to a noise analysis, and comparing the input circuit information and the recommended circuit information, and determining a differing portion of the recommended circuit information differing from the input circuit information, as noise countermeasures.

Abstract: Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.

Abstract: A modeling method and a simulation method enable a circuit board to undergo modeling without deterioration of simulation precision while describing with no matrix shape. A circuit simulator analyzes power/ground noise of a circuit board with single current change source. A process regards the circuit board as an aggregate of thin doughnut boards of concentric circle shape with the current change source as the center, subsequently, approximating the aggregate of the doughnut boards to be an aggregate of rectangular boards with respective circumferences of the doughnut boards as widths and respective cut-lengths of the same as lengths, then forming respective transmission line models taking respective rectangular boards of the aggregate of the rectangular boards as the transmission line, thus connecting respective transmission line models in series to make it a simulation model of the circuit board.

Abstract: Equivalent circuits and a simulation method for simulating an RF switch are disclosed. The equivalent circuits are a first equivalent circuit and a second equivalent circuit, and are formed by resistors, capacitors, and inductors. The method includes using the first equivalent circuit to simulate the switch at a turned-off state and using the second equivalent circuit to simulate the switch at a turned-on state.

Abstract: A system and method are disclosed for editing netlists described in a hardware description language (HDL). In one embodiment, a netlist is provided and a changes module is provided. The changes module contains a set of changes associated with the netlist. A tool, such as a netlist compiler, then edits the netlist using the changes described in the changes module. The changes module may be used on subsequent, or different, versions of the netlist where the netlist element changed by the changes module are the same. In this manner, repeated manual editing of a netlist, may be significantly reduced.

Abstract: A method of automated enumeration of one or more devices comprising the steps of (A) generating an enumeration of a plurality of fuses and (B) compiling data for each one of said plurality of fuses, wherein the data comprises (i) one or more schematic path data, (ii) one or more simulation path data and/or (iii) one or more physical location data.

Abstract: A method for functional verification of hardware design. First, a first memory region storing a test pattern and a second memory region storing interrupt instructions are provided. Then, the test pattern stored in the first memory is hardware-simulated. If an external interrupt is received during the simulation of the test pattern, the second memory region is accessed and the interrupt instructions are hardware-simulated. Thereafter, the simulated result of the interrupt instructions is self-tested to obtain a first verification result, and the hardware design is verified according to the first verification result.

Abstract: A predictor for optimal transducer power gain computes the maximum transducer power gain attainable by a lossless matching network for a given load operating over selected non-overlapping (disjoint) sub-bands within a frequency band of operation.

Abstract: A method for optimizing the segment lengths of a segmented transmission line, comprising the steps of modeling the electrical performance of the segmented transmission line, and evaluating the model for incremental changes in electrical performance, selecting a set of segment lengths which meets a set of predefined optimization criteria. The predefined optimization criteria is, for example, minimum peak VSWR.

Abstract: A system is provided to increase the accessibility of registers and memories in a user's design undergoing functional verification in a hardware-assisted design verification system. A packet-based protocol is used to perform data transfer operations between a host workstation and a hardware accelerator for loading data to and unloading data from the registers and memories in a target design under verification (DUV) during logic simulation. The method and apparatus synthesizes interface logic into the DUV to provide for greater access to the registers and memories in the target DUV which is simulated with the assistance of the hardware accelerator.

Abstract: A method for accelerating hardware simulation is presented wherein cycle based simulations of digital system designs are generated by raising the level of abstraction in a hardware simulation environment. Behavioral models of the digital system components are created in a high level general purpose programming language. Function calls created in a high level general purpose programming language provide a transaction based communication interface. During a simulation of the system design, the behavioral models communicate with each other through the transaction based communication interface. Additionally, the behavioral models employ an execute and update method of instruction processing that generates cycle accurate information for the simulation.

Abstract: According to an electric network simulating method, element cells representing electric functions of a plurality of circuit elements and connection pipes representing wiring lines for connecting the circuit elements are defined. A current is defined as the number of particles moving through the connection pipe per unit time, and a voltage is defined as the number of particles present in the connection pipe. A rule for expressing the electric function of each circuit element in accordance the state of the connection pipe is set beforehand in units of element cells. The particles are transferred between the element cell and the connection pipe in accordance with the rule. The state of the electric network is simulated in accordance with the number of particles passing through the connection pipe per unit time and the number of particles present in the connection pipe.

Abstract: A method for selecting a process for forming a device, includes generating a plurality of equations using a response surface methodology model. Each equation relates a respective device simulator input parameter to a respective combination of processing parameters that can be used to form the device or a respective combination of device characteristics. A model of a figure-of-merit circuit is formed that is representative of an integrated circuit into which the device is to be incorporated. One of the combinations of processing parameters or combinations of device characteristics is identified that results in a device satisfying a set of performance specifications for the figure-of-merit circuit, using the plurality of equations and the device simulator.

Abstract: A method for the simultaneous graphical display of paths of optical wavelength channels in a telecommunications network together with one or more channel attributes is provided. The graphical display of the network also shows the direction of data flow transported by the channels. An audible or visual alarm for an error condition for a channel attribute on a link in the network can be produced if requires. The operator can also obtain detailed information on a channel by positioning the mouse over a channel.

Abstract: A test pattern generation flow has a stimulus and a device under test (DUT) that operate together through a test bench. The test bench monitors and collects all the data necessary to generate a test program. This information is presented as a captured simulation that allows for ease of generating test software, as well as other simulations such as fault simulation and virtual test simulation. The complete and convenient information can be utilized to automate the development and/or easily manually develop and debug the test software.

Abstract: A method, named the product terms method that allows to implement and/or to change dynamically the logical behavior of any combinational or synchronous sequential circuits has been presented. The method uses for every product term of logical equations, expressed as a sum-of-product, three memory words: mask word, product word and function word. The words of all product terms are ranged in a table, which characterize the logical behavior of the circuit. The invention provides the hardware structure of several new types of VSLI circuits, having re-configurable logic behaviors. A first embodiment implements any type of multiple output combinational circuit, a second embodiment implements any synchronous sequential circuit with only clock input and, a third embodiment implements any synchronous sequential circuit s with data inputs and clock input.

Abstract: A method for modeling analog signals that may comprise (A) detecting one or more attributed analog signals and (B) modeling the attributed analog signals by adding a signature to each of the one or more attributed analog signals.

Abstract: A system is provided for determining voltage at the output of a gate in an integrated circuit. The system locates a gate within the integrated circuit and looks up a set of output current waveforms as a function of time for different effective capacitances at the gate's output. The system applies each output current waveform to its corresponding effective capacitance to calculate a first set of output voltages and applies each output current waveform to a model of the net coupled to the output of the gate to calculate a second set of output voltages. For each time step in a series of time steps, the system selects an output current waveform for which a voltage in the first set of output voltage waveforms matches a voltage in the second set of output voltage waveforms. The system uses the selected output current waveform to determine the output voltage.

Abstract: In a gate-level logic simulation, a change in electric current is calculated from event information 5 output from a logic simulator 4 through use of a current waveform calculation section 7. The thus-calculated change in current is subjected to FFT processing through use of an FFT processing section 9, thereby determining a frequency characteristic of EMI and enabling EMI analysis.

Abstract: A hot carrier lifetime of a MOS transistor is estimated, depending on model formulas: 1/?=1/?0+1/?b; ?b?1sub?mb·Idmb?2·exp(a/|Vbs|), where ? denotes a lifetime, Isub denotes a substrate current, Id denotes a drain current, Vbs denotes a substrate voltage, ?0 denotes a lifetime at the time the substrate voltage Vbs=0, ?b denotes a quantity representing deterioration of a lifetime at the time the substrate voltage |Vbs|>0, and mb and ‘a’ are model parameters. Furthermore, a parameter Age representing a cumulative stress quantity is calculated depending on model formulas: Age=Age0+Ageb; Ageb=?1/Hb[Isubmb·Id2?m]·exp(?a/|Vbs|)dt, where t denotes time, Hb is a model parameter, Age0 denotes a parameter representing a cumulative stress quantity at the time the substrate voltage Vbs=0, and Agebs denotes a quantity representing an increase of the cumulative stress quantity at the time the substrate voltage at |Vbs|>0.

Abstract: A method is presented, in which a thin film resistor is modeled to account for self-heating. The method includes fabricating the thin film resistor and characterizing a thermal resistance of the thin film resistor, wherein the thermal resistance accounts for self-heating thereof during operation. The thermal resistance is then used in a model for simulating integrated circuits using the thin film resistor.

Abstract: A system designed, including commercially distributed modules protected as intellectual property (IP), is verified in a manner that the IP provider and the user communicate with each other over a communication line to complete the system design verification. A system verification equipment to be operated by the IP provider receives from the system designer across the communication line an input vector at time n to a module provided to the system designer who designed the system integrated using one or more provided IP modules. After simulating the module operation with the input vector, the verification equipment returns an output vector obtained at time n+1 to the system designer over the communication line. The verification equipment examines the input vectors to the provided IP modules and records statistics information thereof, based on which the provider will quantitatively understand how the provided modules have been used.

Abstract: The invention provides a method of analyzing a source current at a higher speed and an enhanced accuracy in a semiconductor integrated circuit including a digital circuit. The method to analyze a waveform of the source current, with consideration of re-distribution of charges throughout the digital circuit in the semiconductor integrated circuit, expressing the digital circuit with series of parasitic capacitors ?Cch, ? (nT) and ?Cch, ? (nT) to be charged and connected between the source and the ground lines. The capacitor series are calculated in time series based on the distribution of switching operations of the logic gates included in the digital circuit. An analysis model for determining the waveform of the source current in the digital circuit is obtained by connecting the parasitic capacitor series with a couple of respective parasitic impedances Zd and Zg of the source line and the ground line.

Abstract: The total resistance value of a coupling portion between first and second circuits is used as the resistance value of a load model; one-half of the total capacity value of the coupling portion is used as each coupling capacity value of the load model; the sum of one-half of the total earth capacity value of the coupling portion and the total capacity value of a non-coupling portion near a first circuit driver is used as the earth capacity value of the load model at a point near the first circuit driver; and the sum of one-half of the total earth capacity value of the coupling portion and the total capacity value of a non-coupling portion farther from the first circuit driver than the coupling portion is used as the earth capacity value of the load model at a point remote from the first circuit driver.

Abstract: An HDL simulator having an automated interface to compiled or interpreted application code written in a general purpose language. The interface enables the HDL code to have a direct data access to and from the application code. The simulator automatically maps and converts HDL data types to and from programming language data types, such as the arguments of routine calls or direct data accesses. Further, the simulator provides a programming language calling mechanism and automatically does data type mapping of arguments, which enables the HDL to call application code routines compiled with a standard compiler, and enables such routines to call functions in the HDL. The simulator automatically generates wrappers for the interface which automatically map data types for direct data access when the application code is compiled, and can output messages upon the occurrence of calls or returns.

Abstract: A method and apparatus are provided for solving a set of differential-algebraic equation arising in a circuit simulation is provided. A collocation method is applied to each differential-algebraic equation to discretize the set of differential-algebraic equations. A solution to the set of differential-algebraic equations based on the discretized differential-algebraic equation is then formed.

Abstract: In a simulation considering a skin effect, a signal conductor is vertically and horizontally divided by faces parallel to the surface of the signal conductor, which are set so that intervals are smaller as the faces are nearer to the surface, and larger as the faces are farther from the surface. Also a ground conductor is vertically divided with a similar method, and an integration calculation is made, so that the resistance of the signal conductor, which corresponds to a given frequency, is obtained.

Abstract: A method of efficiently simulating logic designs comprising signals that are capable of having more than two unique decimal values and one or more unique drive states, such as designs based upon the new N-nary logic design style, is disclosed. The present invention includes a signal model that models N-nary signal value, drive strength, and signal definition information in a specific format that supports the ability of the simulator to simulate the operation of the N-nary logic gates such as adders, buffers, and multiplexers by arithmetically and logically manipulating the unique decimal values of the N-nary signals. The simulator comprises an input logic signal model reader, an arithmetic/logical operator, an output logic signal model generator, and an output message generator that generates one or more output- or input-signal-specific output messages that pack relevant simulation data into a format optimized to the architecture of the simulation host.

Abstract: A system and method for improving predictive modeling of an information system is disclosed, including generating dynamic representations of the business solution through predictive modeling and providing automated calibration of a predictive model against predefined performance benchmarks.

Abstract: A mechanism is disclosed for recognizing and functionally abstracting a column of memory cells. According to one embodiment, a column of n (where n is an integer greater than 1) memory cells is identified in a description of a circuit. One of the n memory cells is selected as a representative memory cell. Then, the column of n memory cells is represented as a single-memory-cell column comprising the representative memory cell. The column is thereafter functionally abstracted to derive a logic-level representation of the memory cell. After that is done, n?1 additional instances of the logic-level representation are generated. In this manner, the column of n memory cells is functionally abstracted as a column of n logic-level representations of the representative memory cell.

Abstract: A method and system for disabling an instrumentation event in a simulation model within a batch simulation farm in which a simulation client communicates with an instrumentation server to process simulation data with respect to the simulation model. An instrumentation event disable list is assembled within the instrumentation server. The assembly of the event disable list includes identifying an instrumentation event to be disabled during simulation processing of the simulation model, and delivering to the instrumentation server an instrumentation event name corresponding to the instrumentation event to be disabled. Prior to simulating the simulation model within the simulation client, the instrumentation event disable list is retrieved from the instrumentation server, and instrumentation events are disabled as specified within the instrumentation event disable list.

Abstract: A system is provided for automatically generating ATAP test solutions. The system includes ATAP simulation circuitry, a bus, an ATAP test bench file, an output file, and a test program. The ATAP simulation circuitry is switchably coupled to a selected analog cell having an ATAP for applying analog tests. The bus is coupled with the ATAP simulation. The bus is operative to transmit and receive analog test simulation data. The ATAP test bench file is configured to receive the simulation data. The output file is operative to store the simulation data and deliver the simulation data to the ATAP simulation circuitry. The test program is generated by the ATAP simulation circuitry in the output file. The test program is configured to automatically generate ATAP test benches based upon chip-specific information. A method is also provided.

Abstract: A system for adaptive partitioning of circuit components during simulating of a circuit having a hierarchical data structure includes a simulator module having one or more computer programs for 1) selecting a group of leaf circuits from the first branch and the second branch for simulation, where each leaf circuit is represented by a matrix comprising a set of equations, 2) determining a strength of coupling between two or more leaf circuits of the group in accordance with a set of predetermined electrical coupling criteria, 3) if two or more leaf circuits are deemed be strongly coupled, combining the corresponding matrix of each strongly coupled leaf circuit into a combined matrix, and 4) performing computation for the two or more strongly coupled leaf circuits in accordance with the combined matrix. The system adaptively adjusts the group circuit matrix for computing a group of circuits according to the strength of coupling between the circuits.

Abstract: A system and method for testing a parameterizable logic core are provided in various embodiments. A test controller is configured and arranged to generate a set of random parameter values for the logic core. A netlist is created from the parameterized logic core, and circuit behavior is simulated using the netlist. In other embodiments, selected parameter values are optionally weighted to increase the probability of generating those values, and the parameter set is cloned and mutated when simulation fails.

Abstract: Systems and methods provide electrostatic discharge simulation techniques. For example, a method in accordance with an embodiment of the present invention provides a simulation of electrostatic discharge in integrated circuits. The method may allow for the design of protection circuits and simulating electrostatic discharge events concurrently with the design of the associated electrical circuit.

Abstract: A system and method for diagnosing a software system within a remote electronic device using a network is provided. A diagnostic controller controls diagnostics of the software system by instructing the remote electronic device to replace a selected software component of the software system with a diagnostic software component. The diagnostic software component has equivalent operational characteristics as the selected software component and includes trace logic that collects diagnostic data while operating with the software system. An analysis routine analyzes the diagnostic data and recommends a corrective measure for the software system.

Abstract: A method for operating a data processing system to simulate a mixer having an RF port, a LO port, and an IF port. In the present invention, the signal leaving the IF port is approximated by: b2=f(a1,a3)+S22*a2 where S22 is a constant, a2 is a signal input to the IF port, a1 is a signal input to said RF port and a3 is a signal input to said LO port, and f ? ( a1 , a3 ) = ? i = o M ? ? j = o N ? C ij * a1 i * a3 j The coefficients Cij are constants that depend on said mixer design. These coefficients can be determined by measuring the b2 when a1 and a3 are single tone signals. In addition, the coefficients can be determined by simulating said mixer on a non-linear circuit simulator when a1 and a3 are single tone signals.

Abstract: A semiconductor device analyzer has a substrate model reading module, a Y-matrix entry module, a discriminating module, a matrix reduction module, and an output format discriminating module. The substrate model reading module reads a substrate network model of three-dimensional meshes representing the substrate of a semiconductor device. The substrate network model is a network of resistive and capacitive elements and is used for the simulation and analysis of the semiconductor substrate. The Y-matrix entry module prepares a Y-matrix from the substrate network model, each element of the Y-matrix being expressed with a polynomial of differential operator “s”. The discriminating module discriminates internal nodes to be eliminated from external nodes to be left among the nodes of the substrate network model. The matrix reduction module eliminates the internal nodes, thereby reducing the Y-matrix. The output format determining module determines an output format for an operation result.

Abstract: A method and apparatus for identifying potential noise failures in an integrated circuit design is described. In one embodiment, the method comprises locating a victim net and an aggressor within the integrated circuit design, modeling the victim net using two ?-type resistor-capacitor (RC) circuits, including determining a coupling between the victim net and the aggressor, and indicating that the integrated circuit design requires modification if modeling the victim net indicates that a potential noise failure may occur in the integrated circuit design.

Abstract: An initial condition (IC) behavior module is described for use in a hardware definition language simulation system which operates in two phases. In the first phase, the IC module sets an initial logic condition onto a user-selected node which is to be monitored. The IC module will release the initial condition and then test the node value to determine if the simulation system is able to resolve the node. Alternatively, the IC module may release the node if a user-defined IC time period passes. In the second phase, the IC module monitors the node and reports an error message if the simulated node value becomes unacceptable.

Abstract: An integrated circuit development library is provided that characterizes several different logic device cells. The library specifies a number of different timing relationships for each of the logic device cells. These timing relationships are evaluated for each of the logic device cells at a first derating condition with a first simulator to provide a first set of derated condition values. The first set of derated condition values each correspond to one of the timing relationships evaluated. A first derating factor is calculated from the first set of derated condition values for estimating derated performance of an integrated circuit with a second simulator. This integrated circuit is developed from one or more of the logic device cells of the library.

Abstract: A method, apparatus, system, and signal-bearing medium that in an embodiment select a subset of transmission line models based on bounding electrical criteria. The bounding electrical criteria may include combinations of maximum and minimum values and in an embodiment may also include nominal values. Models that meet the bounding electrical criteria may be used in modeling the transmission line while models that do not meet the bounding electrical criteria are not used.

Abstract: A design tool and method characterizes a circuit at a hardware level description. A behavioral level description of the circuit is created. Symbolic equations for components of the behavioral level description are created. The behavioral level description is partitioned by inserting a marker component into the behavioral level description of the circuit to simplify subsequent processing used to prove equivalence between the behavioral and hardware level descriptions. The symbolic equations are back-substituted until output variables are expressed in terms of input variables that determine the output variables. The marker component is defined using a unique symbolic name. Current time counts of each clock cycle are used to compute an index for the marker component. The behavioral level description is transformed to produce symbolic and numeric files for compilation to gates and proof of functionality.

Abstract: A low cost signature test for RF and analog circuits. A model is provided to predict one or more performance parameters characterizing a first electronic circuit produced by a manufacturing process subject to process variation from the output of one or more second electronic circuits produced by the same process in response to a selected test stimulus, and iteratively varying the test stimulus to minimize the error between the predicted performance parameters and corresponding measured values for the performance parameters, for determining an optimized test stimulus. A non-linear model is preferably constructed for relating signature test results employing the optimized test stimulus in manufacturing testing to circuit performance parameters.

Abstract: The present invention describes a method and an apparatus for determining switching power consumption of global devices (e.g., repeaters, flops or the like) in an integrated circuit design during high-level design phase after the global routing for the integrated circuit is available. The clock cycle is divided into various timing intervals and the timing reports are generated for each cycle to determine a time-domain staggered distribution of each device's switching activity within a given timing interval. Each device's switching activity is analyzed within the given timing interval (or segment thereof). The power consumption is determined for each device that switches in the given timing interval.