Circuit Simulation Patents (Class 703/14)
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Patent number: 7181383Abstract: A system for simulating a circuit having hierarchical data structure includes a simulator module having one or more computer programs for 1) creating a static database in accordance with a netlist description of the circuit, where the static database contains topology information of the circuit; 2) selecting a group circuit for simulation, where the group circuit contains one or more leaf circuits selected from the first branch and the second branch; 3) creating a dynamic database for representing the group circuit, where the dynamic database includes references to the static database for fetching topology information dynamically during simulation; and 4) simulating the group circuit in accordance with the dynamic database. Since the system duplicates and reproduces only the relevant dynamic information when necessary, the disclosed circuit simulator uses less memory and produces better performance.Type: GrantFiled: November 26, 2003Date of Patent: February 20, 2007Assignee: Cadence Design Systems, Inc.Inventors: Bruce W. McGaughy, Prashant Karhade, Jaideep Muhkerjee, Jun Kong
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Patent number: 7181706Abstract: An electrical circuit comprising a plurality of cells can be simulated to produce simulation results by sorting cells between active status cells and inactive status cells and reducing the processing of simulation results from inactive cells to thereby save simulation time.Type: GrantFiled: December 16, 2004Date of Patent: February 20, 2007Inventors: Steven S. Greenberg, Du V. Nguyen, Joseph Rodriguez
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Patent number: 7181376Abstract: A Bayesian network correlating coverage data and input data to a test verification system for coverage directed test generation (CDG) of a device under test. In one embodiment, the Bayesian network is part of a CDG engine which also includes a data analyzer which analyzes coverage data from a current test run of a test verification system and from previous test runs to determine which coverage events from a coverage model have occurred therein, at what frequency and which ones have not yet occurred, a coverage model listing coverage events which define the goal of the test verification system and a task manager coupled to the data analyzer and the Bayesian network which refers to the coverage model and queries the Bayesian network to produce input data to achieve desired coverage events.Type: GrantFiled: June 3, 2003Date of Patent: February 20, 2007Assignee: International Business Machines CorporationInventors: Shai Fine, Moshe Levinger, Avi Ziv
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Patent number: 7181384Abstract: A method for performing simulation on a circuit includes simulating registered and concurrent nodes in the circuit. Only concurrent nodes that are associated with a concurrent feedback loop are simulated until outputs of the concurrent nodes that are associated with the concurrent feedback loop reach a steady state.Type: GrantFiled: August 16, 2004Date of Patent: February 20, 2007Assignee: Altera CorporationInventors: Adam Schott Riggs, Philippe Molson
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Patent number: 7181717Abstract: A method for positioning components of a system onto a target device utilizing programmable logic devices (PLDs) is disclosed. A location is determined for a user defined region on the target device that allows the system to satisfy timing constraints.Type: GrantFiled: June 15, 2004Date of Patent: February 20, 2007Assignee: Altera CorporationInventors: Deshanand P. Singh, Stephen D. Brown, Terry P. Borer, Chris Sanford, Gabriel Quan
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Patent number: 7177788Abstract: Input parameters and technically possible parameter values associated therewith are selected, from which are obtained support point values and result values assigned thereto for the geometrical properties. At each support point value, the respective result value is assigned to the parameter value assigned to the respective support point value. A response surface is adapted to the result values in a total range of the assigned parameter values. This results in response values for which a minimum value and a maximum value are determined in subranges. A total interval is formed from the largest response value overall and the smallest response value overall. The total interval is divided into a given number of sub-intervals. For each of the sub-intervals, the individual probabilities are cumulated, which yields a total probability value for a respective sub-interval over all the value intervals.Type: GrantFiled: October 17, 2002Date of Patent: February 13, 2007Assignee: Infineon Technologies AGInventor: Martin Roessiger
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Patent number: 7177789Abstract: A simulator fitted with at least one microprocessor sends input simulation signals to a unit under test, and receives therefrom output signals in reaction thereto. The method consists in processing some of the output signals from the unit as they are issued by means of a programmable logic circuit, in storing parameter values corresponding to said processed signals, and in giving the microprocessor access to the stored parameter values at a frequency which is compatible with its own operating speed. The apparatus enables the method to be implemented. The simulator comprises at least one programmable logic circuit, e.g. of the FPGA type, that is suitable for receiving at least some of the signals output by the electronic unit.Type: GrantFiled: August 30, 2000Date of Patent: February 13, 2007Assignee: AlstomInventor: Denis Miglianico
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Patent number: 7177783Abstract: The invention allows the inclusion of cross-talk coupling and other noise in circuit simulation by considering a resultant glitch in more detail than just its peak value. A set of parameters represents the noise, with an exemplary embodiment using a triangle approximation to a glitch based on a set of three parameters: the peak voltage value, the leading edge slope and the trailing edge slope. These values are then used as the input stimulus to a given cell instance in the network in which the resulting propagated noise values, also in a triangle approximation, are determined by a simulation. The results can be stored as a library so that, given the parameters of the input noise and the particular cell, a simulation can determine the propagated noise through a look-up process. To reduce the space requirements of the library, the dimensionality of the look-up tables can be reduced through the introduction of a set of auxiliary functions to offset error from this reduction.Type: GrantFiled: January 10, 2003Date of Patent: February 13, 2007Assignee: Cadence Design Systems, Inc.Inventors: Lifeng Wu, Jianlin Wei, I-Hsien Chen
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Patent number: 7171346Abstract: A mismatch modeling tool (10) comprises a software implemented mismatch model (32). The software implemented mismatch model (32) accesses: at least one editable mismatch model data library (18) comprising process parameter variables, and circuit simulation library and program (14) data output. An interface screen (100) provides input and output coupling between a user and the software implemented mismatch model (32).Type: GrantFiled: September 1, 2000Date of Patent: January 30, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Cynthia L. Recker, Patrick G. Drennan
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Patent number: 7171347Abstract: A method of preparing a circuit model for simulation comprises decomposing the circuit model having a number of latches into a plurality of extended latch boundary components and partitioning the plurality of extended latch boundary components. Decomposing and partitioning the circuit model may include decomposing hierarchical cells of the circuit model, and using a constructive bin-packing heuristic to partition the plurality of extended latch boundary components. The partitioned circuit model is compiled, and simulated on a uni-processor, a multi-processor, or a distributed processing computer system.Type: GrantFiled: July 2, 1999Date of Patent: January 30, 2007Assignee: Intel CorporationInventors: Manpreet S. Khaira, Steve W. Otto, Honghua H. Yang, Mandar S. Joshi, Jeremy S. Casas, Erik M. Seligman
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Patent number: 7168060Abstract: A system LSI development environment generating method includes a compiler customizing section which generates a compiler from a configuration designation file, an assembler customizing section which generates an assembler, and a simulator generating section which generates a simulator. The configuration designation file contains a designation of hardware which executes instructions.Type: GrantFiled: July 19, 2002Date of Patent: January 23, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Nobu Matsumoto, Ryuichiro Ohyama, Katsuya Uchida
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Patent number: 7168059Abstract: A tool is disclosed that allows a hardware designer using a behavioral synthesis tool to view a calculated execution time for a group of related loops identified in source code describing a hardware design circuit. Further, a designer can then interactively unroll and/or pipeline a selected loop without having to modify the source code description of the circuit. Using a graphical user interface (GUI), the designer can modify the loop design easily and see the results of the new loop configuration without having to generate the RTL code, perform RTL synthesis, etc. For example, the designer can readily view the relative loop execution time of the circuit to better determine whether the design is acceptable. Additionally, the designer can execute an area-versus-latency analysis, and, if the analysis is not satisfactory, the designer can unroll and or pipeline selected loops using the GUI.Type: GrantFiled: April 19, 2002Date of Patent: January 23, 2007Inventors: Bryan Darrell Bowyer, David Gaines Burnette, Ian Andrew Guyler
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Patent number: 7162403Abstract: A system for tracing signals for a cycle-based simulation includes a traced signal and a system resources availability information of the cycle-based simulation, a runtime compiler configured to use the system resources availability information to assign a system resource to trace the traced signal, a logic design used with the system resources availability information to generate a simulation image, a first value of the traced signal generated by execution of a simulation image, and a traced signal buffer configured to store the first value and upload the first value.Type: GrantFiled: February 14, 2003Date of Patent: January 9, 2007Assignee: Sun Microsystems, Inc.Inventors: Nasser Nouri, Ping-Chih Wu, Mohamed Soufi, David S. Allison
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Patent number: 7162400Abstract: An aspect of the present invention provides a method of carrying out a simulation with simulation data, including, determining whether or not the simulation data includes boundary conditions set for a boundary of a calculation area set for the simulation, computing the influence of the boundary conditions on the inside of the calculation area if the simulation data includes the boundary conditions, displaying the influence of the boundary conditions on the inside of the calculation area, prompting to enter an instruction whether or not the boundary conditions are changed, and if an instruction to make no change in the boundary conditions is entered, carrying out the simulation with the simulation data.Type: GrantFiled: December 28, 2001Date of Patent: January 9, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Sanae Ito, Hirotaka Amakawa
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Patent number: 7162401Abstract: Whenever a resource being modeled is accessed, an indication about the access is stored in a number of memory locations of a corresponding number of applications that are interested in monitoring the resource. The memory locations (also called “monitoring memory locations”) are individually identified for each application when allocating a location in main memory. At this time, a pointer to the monitoring memory location is supplied to the application and also added to a group of pointers of locations to be updated when accessing the resource. In addition, in certain embodiments, a bit is allocated within a bitmap for each monitoring memory location for any given application. Such a bit is set at the time of updating the corresponding monitoring memory location and cleared when the application reads the monitoring memory location. Just checking the bitmap as a whole can inform an application if there is any change in any monitoring memory locations of that application.Type: GrantFiled: March 28, 2003Date of Patent: January 9, 2007Assignee: Applied Micro Circuits CorporationInventor: Robert Emil Abeles
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Patent number: 7159196Abstract: A system and method for providing interface compatibility between two hierarchical collections of integrated circuit (IC) design objects. Upon establishing an associative correspondence between a design object from a first hierarchical collection and a design object from a second hierarchical collection, a port compatibility map is generated based on determination that a particular associative correspondence includes a pair of design objects, one from each hierarchical collection, that are port-compatible. Thereafter, the port compatibility map is reduced to determine a set of design object pairs that allow interface-compatible replaceability between the first and second hierarchical collections.Type: GrantFiled: February 4, 2004Date of Patent: January 2, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventor: David Michael Anderson
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Patent number: 7155379Abstract: A component, system and method for simulation of a PCI device's memory-mapped I/O register(s) are provided. The PCI simulation component has an initialization component, a configuration space simulator and a memory-mapped I/O space simulator. The initialization component can claim an amount of memory by modifying the amount of memory that an operating system has available to it. The initialization component further identifies to the operating system that at least some of the claimed memory resides on a PCI bus. The configuration space simulator causes the operating system to accept that the simulated PCI device is present in the system. The memory-mapped I/O space simulator simulates device and can comprise can comprise a thread that monitors the simulated memory-mapped I/O registers for a change in order to simulate behavior of the simulated PCI device.Type: GrantFiled: February 25, 2003Date of Patent: December 26, 2006Assignee: Microsoft CorporationInventors: Jacob Oshins, Brandon Allsop
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Patent number: 7155378Abstract: A method of providing ad hoc verification for a simulation includes generating a cumulative record of a state value for the simulation of a circuit design, comparing the cumulative record of the state value to a golden record of the state value to obtain a comparison result, and performing ad hoc verification of the circuit design using the comparison result.Type: GrantFiled: December 16, 2002Date of Patent: December 26, 2006Assignee: Sun Microsystems, Inc.Inventors: Liang T. Chen, David R. Emberson, Keith H. Bierman
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Patent number: 7155685Abstract: It is an object of the present invention to provide a method, an apparatus and a program having high optimization precision and capable of obtaining an answer required by a designer in a short time by combining optimization between individual transistors and optimization as the entire circuit, or by appropriately combining judgment of an operation region, an analysis of the operation region and a SWEEP sensitivity analysis when the optimization is carried out. An optimizing designing apparatus of an integrated circuit for designing a circuit, comprises operation region judging means for adjusting an operation region (linear region, saturation region) of the circuit, operation region analysis means for displaying liner characteristics (Ids-Vgs characteristics) of the circuit and saturation characteristics (Ids-Vds characteristics) of the circuit, and SWEEP sensitivity analysis means for displaying variation in output characteristics of the circuit.Type: GrantFiled: December 29, 2003Date of Patent: December 26, 2006Assignees: Sipec Corporation, Seiko Instruments Inc.Inventors: Kenji Mori, Takashi Nakajima
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Patent number: 7155374Abstract: A method for checking a model includes specifying a path to be traversed through the states of a system under study, such that a specified sequence of events is to occur on the specified path between an initial state and a target set of states on the path. Beginning from the initial state, successive reachable sets of states along the specified path are computed, such that in the successive reachable sets the events occur in the specified sequence. When an intersection is not found to exist between one of the reachable sets on the specified path and the target set, a partial trace is produced along the specified path between the initial state and a termination state in which at least one of the specified events occurs.Type: GrantFiled: January 11, 2002Date of Patent: December 26, 2006Assignee: International Business Machines CorporationInventor: Shoham Ben-David
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Patent number: 7148702Abstract: In one embodiment, a vector network analyzer (VNA) comprises a plurality of ports for coupling to a device under test (DUT), at least one reference receiver for measuring signals associated with the DUT, and logic for processing measurement data from the at least one reference receiver to compensate for transmission line effects, wherein the logic for processing evaluates a function, of several controllable variables, that is a sum of multiple transmission line models, wherein each of the controllable variables is related to a respective transmission line length associated with a corresponding transmission line model.Type: GrantFiled: March 30, 2005Date of Patent: December 12, 2006Assignee: Agilent Technologies, Inc.Inventors: Kenneth H. Wong, David V. Blackham, Joel P. Dunsmore
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Patent number: 7149675Abstract: A method for automatically mapping state elements between a first circuit and a second circuit is described. The method proceeds by comparing, in a structural phase, structural features of state elements in the first circuit to structural features of state elements in the second circuit for equivalence. Mappings between state elements of the first circuit and the second circuit are determined based on the comparison of structural features. “Don't care” input conditions are then accounted for prior to determination of functional features. During an inversion detection phase, the polarity of the mappings found in the prior structural phase are determined. A functional phase follows in which the functionality of state elements in the first circuit are compared to the functionality of state elements in the second circuit for equivalence using a three-valued random simulation and further mappings are determined based upon the functional comparison.Type: GrantFiled: March 9, 2001Date of Patent: December 12, 2006Assignee: Intel CorporationInventors: Yatin V. Hoskote, Kiran B. Doreswamy
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Patent number: 7149673Abstract: A method provides early estimation of product life using accelerated stress testing data. In an embodiment, data measured from a product operating in first, high-stress environment is used to predict how long the product will operate in a second, normal operating environment before failure. An additional feature of the present invention provides a quantified indication of how much the product has improved from a redesign.Type: GrantFiled: April 25, 2000Date of Patent: December 12, 2006Assignee: Cingular Wireless II, LLCInventors: Michael K. Brand, Harry W. McLean
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Patent number: 7149986Abstract: A method and device for automatically generating load circuits for a netlist. A computer system having a schematic for a circuit is used to create a netlist. While constructing the netlist, instances are checked for directives. The directives indicate that the instance should be tracked as a load circuit. For the instances having such a directive, their nets are flagged and the hierarchal portion of the circuit attached to the flagged nets is flattened. The resulting flat circuit replaces the instance in the netlist as a load circuit.Type: GrantFiled: April 22, 2003Date of Patent: December 12, 2006Assignee: Micron Technology, Inc.Inventor: Larren Gene Weber
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Patent number: 7149666Abstract: Analyzing interactions between vias in multilayered electronic packages that include at least two spaced-apart conducting planes, and multiple vias that connect signal traces on different layers. Voltages at active via ports are represented as magnetic ring current sources, which generate electromagnetic modes inside the plane structure. Substantial electromagnetic coupling between vias occurs. A full-wave solution of multiple scattering among cylindrical vias in planar waveguides is derived using Foldy-Lax equations. By using the equivalence principle, the coupling is decomposed into interior and exterior problems. For the interior problem, the dyadic Green's function is expressed in terms of vector cylindrical waves and waveguide modes. The Foldy-Lax equations for multiple scattering among the cylindrical vias are applied, and waveguide modes are decoupled in the Foldy-Lax equations.Type: GrantFiled: May 30, 2002Date of Patent: December 12, 2006Assignee: University of WashingtonInventors: Leung Tsang, Houfei Chen, Chungchi Huang, Vikram Jandhyala
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Patent number: 7149651Abstract: Embodiments of the present invention reconstruct an underlying phenomenon without the need for predicting a functional form for that signal, by establishing an upper bound and a lower bound for the value of the phenomenon at every point within a measurement space. By acquiring a large enough number of measurements of the phenomenon, a sufficiently high probability that the value of said phenomenon lies between said upper and said lower bound at every point within said measurement space may be established.Type: GrantFiled: May 14, 2004Date of Patent: December 12, 2006Assignee: Agilent Technologies, Inc.Inventors: Valery Kanevsky, John Eidson, Bruce Hamilton
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Patent number: 7149676Abstract: The performance of a system is simulated in a method comprising: performing simulation in a first simulation mode for at least a first portion of code that models at least a portion of the system; and performing simulation in a second simulation mode for at least a second portion of code that models at least a portion of the system.Type: GrantFiled: June 21, 2001Date of Patent: December 12, 2006Assignee: Renesas Technology CorporationInventor: Sivaram Krishnan
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Patent number: 7146302Abstract: A system configuration database is constructed in volatile memory by first determining which types of integrated circuits are present in a hardware system and the number of each type. In response to a determination, a system configuration database is loaded into volatile memory that includes a respective chip hardware database for each type of integrated circuit in the hardware system. Each chip hardware database defines a Dial entity controlling which of a plurality of different possible latch values is placed in a hardware latch of the associated type of integrated circuit. The system configuration database includes at least a first chip hardware database for a first type of integrated circuit that contains per-instance information for each of the multiple instances of the first type of integrated circuit within the hardware system.Type: GrantFiled: April 28, 2003Date of Patent: December 5, 2006Assignee: International Business Machines CorporationInventors: Wolfgang Roesner, Derek Edward Williams
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Patent number: 7146301Abstract: A method for checking a model, which defines states of a system under study and a transition relation among the states. The method includes specifying a property that applies to a target set that comprises at least one target state among the states of the system under study. Beginning from an initial set of at least one initial state among the states of the system, successive reachable sets are computed, including the states of the system that are reachable from the initial set, until an intersection is found between one of the reachable sets and the target set. A plurality of mutually-disjoint traces are then computed from the at least one target state in the intersection through the states in the reachable sets to the at least one initial state.Type: GrantFiled: January 11, 2002Date of Patent: December 5, 2006Assignee: International Business Machines CorporationInventors: Shoham Ben-David, Anna Gringauze
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Patent number: 7146585Abstract: An antifuse latch device and method for performing a redundancy pretest without the use of additional test circuitry is disclosed. Conventional antifuse latch devices are designed such that a redundancy pretest cannot be performed on the antifuse latch device once the antifuses are programmed but rather requires additional circuitry to map the appropriate address bits to test the redundant row or column. The present invention adds a level translating inverter to a conventional antifuse latch device, thus allowing the antifuse latch device to simulate an unblown antifuse by isolating the antifuse from the latch.Type: GrantFiled: February 25, 2003Date of Patent: December 5, 2006Assignee: Micron Technology, Inc.Inventor: Greg A. Blodgett
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Patent number: 7146300Abstract: A method is provided for co-simulating a digital circuit using a simulation engine (45) which communicates with one or more first programming languages by means of a foreign language interface and which communicates directly with one or more second programming language. At least one first model (2, 3) or at least one first part of the digital circuit is provided in at least one high-level hardware description language which supports concurrent processes communicating with each other. The at least one first model is converted (50, 51) to at least one software model in the at least one first language.Type: GrantFiled: December 11, 2001Date of Patent: December 5, 2006Assignee: Sharp Kabushiki KaishaInventors: Vincent Zammit, Andrew Kay
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Patent number: 7143014Abstract: A system and method is described for the simulation of the transfer function of very large RC networks of IC chips, such as VLSI. Both the real and imaginary components of the transfer function of RC networks have a property of changing more rapidly at lower frequencies but changing less rapidly at higher frequencies. Methods are employed which interpolate between transfer functions of the RC network for specific frequencies in order to derive an interpolated transfer function of the RC network.Type: GrantFiled: April 25, 2002Date of Patent: November 28, 2006Assignee: International Business Machines CorporationInventor: Sanjay Upreti
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Patent number: 7143020Abstract: A method for inferring a requested data input function of a sequential cell from a library of candidate cells, wherein the requested cell and the candidate cell are expressed as polynoms and then divided. The method generates polynomial expressions of the inhibition, transformation and inference steps necessary to convert the candidate cell into the requested cell. The use of polynomial expression and division greatly reduces the number of rules necessary to accommodate the varying combinations of requested cell and candidate cell functions.Type: GrantFiled: October 7, 1999Date of Patent: November 28, 2006Assignee: Cadence Design Systems, Inc.Inventor: Arnaud Pedenon
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Patent number: 7143018Abstract: A method and system for minimizing redundancy in collected harvest event testcases from a batch simulation farm which includes a harvest testcase server that collects simulation data for a simulation model from at least one simulation client. In accordance with the method of the present invention, a testcase is executed on the simulation model within a simulation client. Responsive to the testcase triggering a harvest event, the harvest event is compared with a list of harvest events that have previously been triggered within the simulation model. In response to determining that the harvest event has not been previously triggered within the simulation model, the testcase is delivered to the harvest testcase server.Type: GrantFiled: November 30, 2001Date of Patent: November 28, 2006Assignee: International Business Machines CorporationInventors: Carol Ivash Gabele, Wolfgang Roesner, Derek Edward Williams
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Patent number: 7143021Abstract: A machine-implemented, simulations-supporting system creates a hierarchy of data structures for simplifying the task of identifying iso-topological, and iso-geometric, and iso-static instances of subcircuit-definitions. The behaviors of such isomorphic and iso-static instances can be simultaneously predicted by appointing a simulation leader for them and using the simulation leader in combination with a respective simulation model to predict the behavior of the simulation leader. The predicted behavior of the leader is then copied for the followers. In one embodiment, state-describing S-circuit cards each point to a respective, and possibly merged, I-circuit card. The I-circuit cards each point to respective, and possibly merged, element instantiating cards (AG-cards) as well as to respective, and possibly merged, interconnect-topology describing cards (T-circuits).Type: GrantFiled: October 3, 2001Date of Patent: November 28, 2006Assignee: Cadence Design Systems, Inc.Inventors: Bruce W. McGaughy, Prashant Karhade, Peng Wan, Manish Singh
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System and method for integrating subcircuit models in an integrated power grid analysis environment
Patent number: 7143022Abstract: A system and method for integrating a plurality of subcircuit grids in a simulation environment. Upon obtaining a subcircuit layer of a particular granularity for each logical component of an electrical entity (e.g., a semiconductor die in a package and board environment), the nodes of a first subcircuit layer are interconnected to the nodes of a second subcircuit layer using a constraint-based search process.Type: GrantFiled: December 30, 2003Date of Patent: November 28, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Yong Wang, Mark Frank, Jerimy Nelson -
Patent number: 7139936Abstract: An apparatus verifies the correctness of a behavioral model of a microcode machine, where the microcode machine is operable in a native state and an emulated state. The apparatus includes means for producing the native state, means for producing the emulated state, and means for comparing the native state and the emulated state. Corresponding to the apparatus, a method verifies the correctness of a processor behavioral model, where the processor operates in a native mode state and an emulated mode state. The method includes determining if a macroinstruction to be executed is a native instruction, and, if the macroinstruction is a native instruction, executing the native instruction, the execution producing the native mode state of the processor.Type: GrantFiled: August 22, 2003Date of Patent: November 21, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Jeremy Petsinger, Kevin David Safford, Karl P. Brummel, Russell C. Brockmann, Bruce A. Long, Patrick Knebel
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Patent number: 7136799Abstract: A mixed signal delay locked loop characterization technique for automatically characterizing a mixed signal delay locked loop is provided. The technique tests the mixed signal delay locked loop using a top-down approach in order to ensure the robustness of the mixed signal delay locked loop. Top-level testing involves testing the performance of the mixed signal delay locked loop in different process corners, and the results obtained from the top-level testing are then used to test sub-components of the mixed signal delay locked loop.Type: GrantFiled: March 21, 2003Date of Patent: November 14, 2006Assignee: Sun Microsystems, Inc.Inventors: Kian Chong, Dean Liu, Claude R. Gauthier
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Patent number: 7136798Abstract: A method, multi-computer media and apparatus that uses an economics model to manage the demand and the resource satisfying that demand for multi-computer memory. The present invention quantifies demand as a function of space, and computer resource as a function of time, so that a computational system can meet an application demand.Type: GrantFiled: July 19, 2002Date of Patent: November 14, 2006Assignee: International Business Machines CorporationInventors: Gary Ditlow, Daria Rose Dooling, David Erin Moran, Stephen D. Thomas, Ralph James Williams
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Patent number: 7136797Abstract: The apparatus comprises the syntax checking section that checks the syntax of a device model according to a check table showing the relation between the syntax of the device model showing electrical characteristics of a semiconductor device and an amendment when deviating from the syntax. The syntax error amendment creating section corrects the device model according to a corresponding amendment when a description deviating from the syntax is checked by the syntax checking section.Type: GrantFiled: July 19, 2001Date of Patent: November 14, 2006Assignee: Fujitsu LimitedInventors: Masaki Tosaka, Toshio Karino, Tatsuo Koizumi, Jiro Yoneda, Megumi Nagata, Hiroyuki Orihara, Hikoyuki Kawata
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Patent number: 7136796Abstract: An exemplary method and system for generating integrated circuit (IC) simulation information regarding the effect of design and fabrication process decisionn includes creating and using a data store of profile-based information comprising metrology signal, structure profile data, process control parameters, and IC simulation attributes. An exemplary method and system for generating a simulation data store using signals off test gratings that model the effect of an IC design and/or fabrication process includes creating and using a simulation data store generated using test gratings that model the geometries of the IC interconnects. The interconnect simulation data store may be used in-line for monitoring electrical and thermal properties of an IC device during fabrication. Other embodiments include utilizing a metrology simulator and various combinations of a fabrication process simulator, a device simulator, and/or circuit simulator.Type: GrantFiled: February 28, 2002Date of Patent: November 14, 2006Assignee: Timbre Technologies, Inc.Inventors: Nickhil Jakatdar, Xinhui Niu, Junwei Bao
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Patent number: 7132845Abstract: In a method and system for testing a test sample (190), a simulation program (130) is used to augment test results provided by a legacy test system (101). The legacy test system (101) includes a measuring device (110) providing a test input (112) to the test sample (190) and receiving a test output (116) from the test sample (190) in response to the test input (112). The simulation program (130) simulates the test sample (190) by predicting a simulated output (134) of the test sample (190) in response to receiving a simulated input (132). A plurality of simulated failures is simulated in the simulation program (130), with each simulated failure generating a corresponding simulated output. The simulation program (130) includes a model (140) for the measuring device (110), the model (140) providing the simulated input (132). A comparator (160) compares the test output (134) with the simulated output (134) to determine a match.Type: GrantFiled: August 19, 2005Date of Patent: November 7, 2006Assignee: Texas Instruments IncorporatedInventors: Michael Anthony Lamson, Jay Michael Lawyer, Roger Joseph Stierman
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Patent number: 7133809Abstract: A system, device, and method for time-domain equalizer training uses a two-pass auto-regressive moving average model. A communication channel is first modeled using p1 poles and q1 zeros to form a first shortened channel impulse response having a first approximation H1(z)=B1(z)/1+A1(z), wherein q1, is greater than a predetermined cyclic prefix length. A time-mirrored image of the first shortened channel impulse response is then formed, and the resulting time-mirrored image of the first shortened channel impulse response is modeled using p2 poles and q2 zeros to form a second shortened channel impulse response having a second approximation H2(z)=B2(z)/1+A2(z), wherein q2 is less than or equal to the predetermined cyclic prefix length. The time-domain equalizer coefficients are determined by combining A1(z) and A2(1/z) with an appropriate amount of delay.Type: GrantFiled: April 4, 2000Date of Patent: November 7, 2006Assignee: Nortel Networks LtdInventors: Aleksandar Purkovic, Steven A. Tretter
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Patent number: 7134100Abstract: Techniques for accelerating power estimation for a circuit comprising generating an RTL description of the circuit. A power model enhanced RTL description of the circuit is generated. A simulator is selected. The power model enhanced RTL description is modified to make it more friendly to the simulator. The simulator is run to estimate the power consumed by the circuit. Techniques using delayed computation and partitioned sampling are also provided. Power estimation systems using the above techniques area also provided.Type: GrantFiled: July 29, 2002Date of Patent: November 7, 2006Assignee: NEC USA, Inc.Inventors: Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
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Patent number: 7134110Abstract: Disclosed are novel methods and apparatus for efficiently providing critical path analysis of a design. In an embodiment, an apparatus disclosed can assist in creating a single critical path schematic which can be used to simulate both rising and falling edge delays. This saves time as only one schematic and one simulation is required instead of the two generally required.Type: GrantFiled: October 30, 2003Date of Patent: November 7, 2006Assignee: Sun Microsystems, Inc.Inventor: Abhay Gupta
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Patent number: 7133818Abstract: A method of providing accelerated post-silicon testing for a silicon hardware includes computing a simulation cumulative record of state using a plurality of test instructions and a cycle breakpoint, performing a simulation of an instrumented logic design using the plurality of test instructions and the cycle breakpoint, manufacturing the silicon hardware using the instrumented logic design, computing a silicon cumulative record of state by executing the plurality of instructions using the silicon hardware; and comparing the simulation cumulative record of state to the silicon cumulative record of state.Type: GrantFiled: April 17, 2003Date of Patent: November 7, 2006Assignee: Sun Microsystems, Inc.Inventors: Keith H. Bierman, David R. Emberson, Liang T. Chen
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Patent number: 7133816Abstract: A preemptive reloading technique is employed in a test program generator. Initialized resources are reset with needed values by reloading instructions. The actual reloaded value is chosen later, when the instruction that actually needs the value is generated. The test program generator distances the reloading instruction from the instruction that actually needs the value, thus making it possible to avoid fixed test patterns and to generate interference-free test segments during design verification.Type: GrantFiled: November 4, 2002Date of Patent: November 7, 2006Assignee: International Business Machines CorporationInventors: Allon Adir, Eitan Marcus, Michal Rimon, Amir Voskoboynik
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Patent number: 7130784Abstract: Logic simulation includes storing a first state to identify in a simulation of a logic design whether a node included in the logic design has a logic high value Logic simulation also includes storing a second state to identify in simulation of the logic design whether the node has a logic low value and storing a third state to identify in simulation of the logic design whether the node has an undefined state. The logic simulation determines an output of the node in simulation of the logic design based on the first state, the second state, and the third state.Type: GrantFiled: August 29, 2001Date of Patent: October 31, 2006Assignee: Intel CorporationInventors: William R. Wheeler, Timothy J. Fennell, Matthew J. Adiletta
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Patent number: 7127363Abstract: In one embodiment, the present invention includes a method for simulating a first stimulus into a device under test and measuring first single-ended scattering parameters caused thereby, and directly calculating a differential scattering parameter from the first single-ended scattering parameters. In certain embodiments, second single-ended scattering parameters may be obtained from a second stimulus into the device under test, and the results used to calculate the differential scattering parameter, for example, where a device under test is non-homogeneous.Type: GrantFiled: April 27, 2004Date of Patent: October 24, 2006Assignee: Intel CorporationInventor: Jeff W. Loyer
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Patent number: 7127384Abstract: A fast transient simulator of SOI MOS circuits uses fast and accurate SOI transistor table models. The simulator uses a representation of a circuit with partitions. Each of partitions is simulated separately for a short time step by numerically solving differential equations describing its transient behavior. Behavior of the whole circuit is simulated in an event driven way where each event corresponds to an integration time step for each partition. Instead of body voltage, the simulator implements a transformation and uses body charge as an independent variable in order to obtain high accuracy and high speed of simulation. Construction of SOI transistor table models results in speed and accuracy enhancements. This transformation allows the reduction of the number of table dimensions exploiting the fact that SOI transistor backgate capacitance is approximately constant.Type: GrantFiled: August 27, 2002Date of Patent: October 24, 2006Assignee: Freescale semiconductor, Inc.Inventors: Vladimir P. Zolotov, Rajendran V. Panda, Sergey V. Gavrilov, Alexey L. Glebov, Yury B. Egorov, Dmitry Y. Nadexhin