Abstract: A systematic defect analyzing method, includes: partitioning physical sites into groups to obtain a plurality of groups of physical sites according to a plurality of physical features of a chip corresponding to different potential systematic defects; utilizing a processor to compute at least one defect probability of each group of physical sites; and deriving an analysis result according to the plurality of defect probabilities corresponding to the plurality of groups of physical sites.

Abstract: A method of generating optimized memory instances using a memory compiler is disclosed. Data pertinent to describing a memory to be designed are provided, and front-end models and back-end models are made to supply a library. Design criteria are received via a user interface. Design of the memory is optimized among speed, power and area according to the provided library and the received design criteria, thereby generating memory instances.

Abstract: A system, method, and computer program product for improving circuit reliability via circuit schematic simulation. A circuit simulator may netlist and simulate a schematic with a reference stimulus and determine whether a circuit component is a candidate for stress analysis, and store candidate component circuit conditions. A stress test simulation may determine if candidate components are stressed by exposure to simulated conditions meeting a stress test criterion, and output information regarding stressed circuit components. Embodiments may simulate analog integrated circuitry, determine MOS component gate oxide layer area according to component length and width, and monitor conditions on components deemed most likely to be defective, including larger MOS components. A circuit simulator plug-in may avoid storing simulation output waveforms or performing layout based analysis.

Abstract: A method and system for optimizing the testing efforts in system of systems testing includes receiving test parameters for a new constituent system in a system of systems. Based on the received test parameters, retrieving, historical test knowledge related to the system of systems. Based on the retrieved historical test knowledge, characterizing unique parameters from the received test parameters. The unique test parameters are combined in sequence or in parallel to identify executable test parameters and one or more test cases are selected corresponding to the identified executable test parameters for execution.

Abstract: In a system and method that simulates a design including a third party IP component, a driver for the IP component is compiled and executed in a workstation implementing the simulation platform for the design. The source code for the driver is modified to allow the simulation to reroute certain functions that would cause the simulator to hang until an event occurs that would unlock the simulation. The rerouting includes storing instruction location, state information, and any other context information needed to restore a paused function. The saved information is stored in a stack that is traversed upon detection of the event.

Abstract: A computer-implemented method, an apparatus and a computer program for automatically extracting useful information for functional verification. The method comprising performing repeatedly both operating an instruction generator associated with a Design Under Test (DUT), whereby a generated instruction is determined, the generated instruction having one or more instruction attributes; and collecting information relating to the generated instruction. Based on the generated instruction and the collected information, a classification technique is utilized to classify the information based on the instruction attributes.

Abstract: A predicted-failure-evidence diagnosing section for equipment that does not depend on the equipment and does not require knowledge of the equipment is provided. On the basis of a result of a predicted-abnormality-evidence diagnosis carried out by this section on time-series data gathered from the equipment, an allowable error used for compressing the gathered data can be set and managed in order to compress the data if the result of the diagnosis is normal or to restrict the compression of the data during a period in which an evidence of a predicted abnormality is detected. Thus, the amount of data stored in a memory can be reduced.

Abstract: Techniques to automatically generate simulated information are described. A method comprises receiving, by a program builder component executed on a processor, a structured input file comprising one or more data libraries and one or more directive files to generate simulated data for a simulation database. The method further comprising producing, by the program builder component executed on the processor, a data generator program based on the structured input file, the data generator program arranged to generate the simulated data for the simulation database using multiple data generating sessions executed concurrently or sequentially. Other embodiments are described and claimed.

Abstract: In accordance with an embodiment, a simulation apparatus includes a two-dimensional section dividing processing unit, a two-dimensional simulator, a one-dimensional combining processing unit, and a three-dimensional shape combining processing unit. The two-dimensional section dividing processing unit divides a three-dimensional shape as a simulation target into at least one set of two-dimensional sections intersecting with each other and defines the three-dimensional shape as the two-dimensional sections. The two-dimensional simulator runs a two-dimensional shape simulation in each time step for each of the two-dimensional sections obtained by the dividing and acquires a two-dimensional shape. The one-dimensional combining processing unit extracts a film configuration for each intersection of the two-dimensional sections from the acquired two-dimensional shape and combines the film configurations to acquire one-dimensional film configurations.

Abstract: A computer-implemented method and non-transitory computer readable medium for circuit design verification. Formal verification is performed on a circuit design to prove a correctness of a property of the circuit design. The circuit design has a cone of influence representing a portion of the circuit design capable of affecting signals of the property. A proof core of the circuit design is identified, the proof core being a portion of the cone of influence that is sufficient to prove the correctness of the property. A coverage metric is generated that is indicative of a level of formal verification coverage provided by the property based on the proof core of the circuit design.

Abstract: A method for automatically aligning measured power-related data in a power monitoring system to a common reference point. A conductor in a power delivery system is modeled according to an equivalent pi model of a transmission line that is characterized by model parameters. The conductor is monitored on both ends by a reference monitoring device and a second monitoring device. The voltage and current are measured in either the reference monitoring device or the second monitoring device and a phase shift offset between the voltages or currents at the two devices is calculated. The calculated phase shift offset corresponds to a temporal delay between events observed at the pair of devices, and calculating and storing the phase shift offset allows a power monitoring system controller to more accurately align data received from monitoring devices.

Abstract: Disclosed are method(s), system(s), and article(s) of manufacture for creating or manipulating electrical data sets for an electronic design across multiple abstraction levels. The method identifies simulation result(s) obtained from simulation run(s) for an electronic circuit or at least a portion thereof, identifies at least a part of one or more sets of simulation results, each of which is obtained from a simulation run for the electronic circuit or at least a portion thereof at the first abstraction level, identify relevant electrical data or information for design under test instance(s) of a master library or a master cell and creates electrical data set(s), generates a view for at least some of the electrical data set(s), and hand-off the electrical data set(s) to second abstraction level. The method may further identify preexisting electrical data set(s). The method may further compare the electrical data set(s) and preexisting electrical data set(s).

Abstract: Embodiments provide systems, methods, and computer program products for mapping higher-layer circuits, links, flows, and services to lower layer circuit and connection elements to determine utilization of the lower layer circuit elements based on the high-layer traffic. Higher layer configuration data and lower layer configuration data are imported to populate a model. An inter-layer relationship is either directly or indirectly mapped from the higher layers to the lower layer. Once the inter-layer relationship is established, the higher-layer circuits, links, flows, and services are inspected using the lower layer circuit and connection elements. Circuit and packet-based utilization is determined for the lower layer elements based on the higher-layer traffic flows.

Abstract: A computer-implemented adaptive experimentation method and system is described that automatically selects and executes information gathering actions. The adaptive experimentation method and system integrates value of information considerations, experimental design, and inferences from experimental results. The experimental results may include behaviors of users of a computer-based system. The process enables an automatic, adaptive process for attaining additional information and applying the attained information in making subsequent experiment decisions.

Abstract: A network-based application development and distribution platform allows application developers to build, modify, and configure dynamic content applications (especially mobile applications) remotely, and without requiring manual software coding. Smart endpoints facilitate creation of distributable applications for multiple operating systems, form factors, access methods, and/or device types, while creating only a single product and associating the product with the desired endpoints corresponding to the operating systems, form factors, access methods, and/or device types. The platform also facilitates software updates, as updates can be made to the product once, rather than once for each version of the application.

Abstract: A system and method for dynamically designing shared content served via a content sharing source. The system includes a content size determination unit to determine a size of content sourced from the content sharing source; a shared content size allocation unit to determine a size of the shared content based on the size of the content; a shared content rules database to determine a design style associated with the shared content based on the determined size of the shared content; and a shared content transmitting unit to communicate the shared content in accordance with the design style to the content sharing source.

Abstract: A mechanism is provided for identifying failed components during data collection. For each data source combination in a plurality of data sources, a determination is made as to whether a standard deviation (?) for an estimated collection interval of the data source is above a predetermined standard deviation threshold (?th). Responsive to the standard deviation (?) for the estimated collection interval of the data source being above the predetermined standard deviation threshold (?th), an error signal is generated indicating an error in data collection with the data source.

Abstract: A method of validating functional testing of system circuitry on an integrated circuit chip, the system circuitry configured to perform a plurality of functions, the integrated circuit chip further comprising debugging circuitry under the control of a debug controller, the debugging circuitry comprising at least one debug unit. The method comprises: at the system circuitry, performing one of the plurality of functions; applying a debug configuration to the at least one debug unit; and at the at least one debug unit, monitoring for a characteristic in the system circuitry's performance of the one of the plurality of functions according to that debug configuration, and reporting to the debug controller.

Abstract: A system and a method for simulation using multiple programming languages is provided. The method can include receiving an annotated source having a first plurality of instructions written in a first programming language and receiving an annotation having a second plurality of instructions written in a second programming language and associated with an annotated instruction from the first plurality of instructions. The method can include extracting the second plurality of instructions to create a routine from the annotation. The method can include building a shared library that contains the routine. The method can include building an application object file by assigning an address to each instruction of the first plurality instructions. The method can include creating an annotation table that contains an address for the annotated instruction and an associated symbol.

Abstract: A signal transmitting-receiving circuit includes a first circuit including a first MOS transistor having a gate and a drain, a second MOS transistor having a gate and a drain connected to the gate and drain of the first MOS transistor, and a source connected to ground, and a transmitting terminal transmitting a signal connected to the drains of the first and second MOS transistors; and a second circuit including a receiving terminal receiving the signal transmitted from the transmitting terminal of the first circuit connected to the transmitting terminal, a third MOS transistor having a gate connected to the receiving terminal, a drain connected to a reference voltage generator circuit and a source connected to ground, a resistor connected between the third MOS transistor and the reference voltage generator circuit, and an output terminal connected between the resistor and the third MOS transistor.

Abstract: In one embodiment, a method for compiling an HDL specification for simulation of a circuit design is provided. Using one or more processors the circuit design is elaborated from the HDL specification. Two or more instances of a module of the elaborated design that have a same hardware configuration are determined. Simulation code that models the circuit design is generated. A first portion of the simulation code is configured to model the module having the hardware configuration. For each of the two or more instances, a second portion of the simulation code is configured to, in response to an indication to simulate the instance, execute the first portion of simulation code using a respective set of nets corresponding to the instance.

Abstract: Any primitive cells or blocks can be represented physically by a Barycenter compact model, and any black box model can also be physically represented by a Barycenter compact model physically. A hierarchical boundary condition between blocks is formulated by the Barycenter model or Barycenter compact model. Hierarchical boundary condition problems between blocks can be limited within two levels only if using the Barycenter model or Barycenter compact model.

Abstract: A computerized apparatus, method and computer product for generating tests. The apparatus comprises: a processor; an interface for obtaining a test template associated with a computerized system that comprises a template segment comprising instructions and directives or related control constructs; a test generator for generating a test associated with the template segment, comprising: a simulator for determining a state of the system associated with an execution of the test; a selector for selecting a template instruction or segment from the test template based on the state of the system; and a generator configured to generate a multiplicity of instructions based on system's state and on the selected template segment, wherein the test generator further comprises a verifier configured to verify that a previously generated instruction is in line with the current state of the system and with the selected template instruction or segment.

Abstract: Any primitive cells or blocks can be represented physically by a Barycenter compact model (or Barycenter model), and any black box model can also be physically represented by a Barycenter compact model physically. A hierarchical boundary condition between blocks is formulated by the Barycenter compact model. Hierarchical boundary condition problems between blocks can be limited within two levels only if using the Barycenter compact model.

Abstract: A design verification system automatically identifies coverage of different constraints for a static model of an electronic device. The static model can be employed by a tool, referred to as a solver, that identifies whether the mathematical relationships of the static model can be reconciled, given a set of user-defined constraints that indicate a desired configuration, or range of configurations, of the electronic device. After a solution for a particular set of user-defined constraints has been identified, a constraints adjustment module can identify, based on coverage information generated by the solver, if other sets of user-defined constraints were implicitly solved by the solver. If such other sets were implicitly solved, the adjustments module can mark the sets as solved, such that they will omitted from constraints used for subsequent solutions of the solver.

Abstract: The described implementations relate to analysis of computing programs. One implementation provides a technique that can include accessing values of input variables that are processed by test code and runtime values that are produced by the test code while processing the input variables. The technique can also include modeling relationships between the runtime values and the values of the input variables. The relationships can reflect discontinuous functions of the input variables.

Abstract: A method including accessing a first virtual prototype configured to perform a first simulation of a hardware design, identifying checkpoints within the first virtual prototype, each checkpoint including a storage state and/or behavioral state, and determining breakpoints for dividing execution of a second virtual prototype into a series of execution segments, where the second virtual prototype is configured to perform a second simulation of the hardware design, the second virtual prototype includes virtual models representing a separate portion of the hardware design, each virtual model representing a same portion of the hardware design as a corresponding virtual model of the first virtual prototype.

Abstract: A method for design simulation includes partitioning a verification task of a design (100) into a first plurality of atomic Processing Elements (PEs-108) having execution dependencies (112), each execution dependency specifying that a respective first PE is to be executed before a respective second PE. The method further includes computing an order for executing the PEs on a multiprocessor device (32), which includes a second plurality of processors (44) operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy. The order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies, irrespective of the scheduling policy. The PEs are executed on the processors in accordance with the computed order and the scheduling policy, to produce a simulation result. A performance of the design is verified responsively to the simulation result.

Abstract: Methods and apparatus for recording and visualizing transactions of a test bench simulation are disclosed. Transaction-specific data generated from a test bench simulation may be displayed in a sequence diagram view to provide a view of the transactions arranged sequentially in time.

Abstract: A system and method are provided for calculating power using a voltage waveform shape measurement from a contactless sensor. An electrically conductive medium carries alternating current (AC) electrical current, associated with an AC voltage, from a source node to a destination node. AC current is measured through the electrically conductive medium. Using a contactless sensor, an AC voltage waveform shape is measured. The power usage at the destination node is calculated in response to the AC current measurement, the measurement of the AC voltage waveform shape, and an AC voltage potential. For simplicity, the AC current and AC voltage waveform shape may both be measured at a first node located between the source node and the destination node. The AC voltage potential used in the power usage calculation may be an estimate, an actual measurement, or a value supplied by an external source (e.g., the power utility).

Abstract: A user interface to a network simulator facilitates the use of application layer parameters and application layer logic. The user interface is configured to allow the user to define the input in a graphic form, or a text/programming form, or a combination of both. The user interface provides common graphic forms for both inputting the data to the simulator as well as for displaying the resultant data from the simulator. In response, the simulator and user interface may provide updated information to reflect the impact of changes made to application layer parameters and logic.

Abstract: The verification apparatus for a semiconductor integrated circuit verifies a logic equivalence before and after modification to the circuit by replacing a memory with a divisional memory model that agrees with the memory in number of input and output pins and verifying logics at an input and an output thereof.

Abstract: Disclosed are embodiments for modeling semiconductor device performance using a single compact model despite changes in performance attribute to model parameter dependency of a single semiconductor device that occur during fitting and/or re-centering due to local layout effects (LLEs) and despite variations in this dependency across multiple related semiconductor devices due to LLEs. In one embodiment, the actual performance attribute to model parameter dependence of a single semiconductor device is fit to a reference dependence so that changes to the compact model are not required even when changes occur in the performance attribute to model parameter dependency during fitting and/or re-centering. In another embodiment, the actual performance attribute to model parameter dependence of each of multiple related semiconductor devices are fit to a reference dependence so that changes to the compact model are not required even when the performance attribute to model parameter dependency varies across the devices.

Abstract: A method for estimating the lifetime of a deep-submicron-generation integrated electronic component, linked to a wear mechanism occurring in previously defined special conditions of use, said component being of a deep submicron type, with very large-scale integration, commercially available off the shelf, wherein one assumes that the same sample population always experiences a failure due to: the most predominant failure mechanism, during the period of useful life, described by an exponential law, and the most critical wear mechanism, represented by a Weibull distribution at the end of the previous period.

Abstract: Example implementations described herein are directed to automatically determine an optimal NoC topology using heuristic based optimizations. First, an optimal orientation of ports of various hosts is determined based on the system traffic and connectivity specification. Second, the NoC routers to which the host's port are directly connected to are determined in the NoC layout. Third, an optimal set of routes are computed for the system traffic and the required routers and channels along the routes are allocated forming the full NoC topology. The three techniques can be applied in any combination to determine NoC topology, host port orientation, and router connectivity that reduces load on various NoC channels and improves latency, performance, and message transmission efficiency between the hosts.

Abstract: Various embodiments include apparatuses and methods to perform noise analysis on a circuit at a selected condition (e.g., process, voltage, and temperature) using a timing model of the circuit in which the timing model is associated with the selected condition.

Abstract: What-if simulation methods and systems are provided. A design coding in HDL (Hardware Description Language) and a simulation result corresponding to the design are provided. A what-if design scope and a what-if time window are received. A portion of the design is extracted from the design according to the what-if design scope, and primary input signals are determined during the extraction of the sub-design. Then, what-if simulation data is extracted from the simulation result according to the primary input signals and the what-if time window. A what-if test bench is generated according to the what-if simulation data, wherein the what-if simulation data is read, and the signal values are fed to a simulator according to the what-if test bench.

Abstract: This invention (900) described a method that generates and uses a test bench for verifying an electrical design module in a semiconductor manufacturing against an electrical reference model containing a sub-circuit that matches the electrical design module. The invention includes providing (902) a description of an electrical design module that includes a plurality of ports. In addition, the invention includes providing (904) a description of an electrical reference model. The invention further includes providing and or creating (92) one or more implicit defines for the reference modules that appear in hierarchy of the electrical reference model. And, the invention includes providing (906) a description file that includes one or more instance definitions. The invention parses (91) the hierarchy of the electrical design model and then processes (96) the description file. The invention then writes (97) the test bench.

Abstract: The embodiments relate to modeling resistance in a multi-fin multi-gate field effect transistor (MUGFET). In these embodiments, a design for a multi-fin MUGFET comprises a gate structure with a horizontal portion traversing multiple semiconductor fins and comprising a plurality of first resistive elements connected in series, with vertical portions adjacent to opposing sides of the semiconductor fins and comprising second resistive elements connected in parallel by the horizontal portion, and with contact(s) comprising third resistive element(s). The total gate resistance is determined based on resistance contributions from the first resistive elements, the second resistive elements and the third resistive element(s), particularly, where each resistive contribution is based on a resistance value of the resistive element, a first fraction of current from the semiconductor fins entering the resistive element and a second fraction of the current from the semiconductor fins exiting the resistive element.

Abstract: A method of circuit simulation includes: simulating, by a processing device, behavior of a heterojunction bipolar transistor device based on at least a first base-emitter voltage of the transistor to determine a first base or collector current density of the HBT device; and determining whether the application of the first base-emitter voltage to the HBT device will result in base current degradation by performing a first comparison of the first current density with a first current density limit.

Abstract: The present invention aims to simulate a response more similar to a actual machine while inhibiting load increase in analog operation. Program configuration of the present invention is a component of a simulation program for circuit design, which is executed by a computer. The computer includes an operation portion, a storage portion, a manipulation portion, and a display portion, so that the computer exerts a function of a circuit design simulator, and as a macro model of an operational amplifier for use in the circuit design simulator, enabling the computer to act by simulating a response of the operational amplifier on the circuit design simulator. The macro model of the operational amplifier includes a control portion (LMT1) for generating output exception in the event of input exception or power supply exception of the operational amplifier.

Abstract: The systems and methods of the present disclosure calibrate impedance loss model parameters associated with an electrosurgical system having no external cabling or having external cabling with a fixed or known reactance, and obtain accurate electrical measurements of a tissue site by compensating for impedance losses associated with the transmission line of an electrosurgical device using the calibrated impedance loss model parameters. A computer system stores voltage and current sensor data for a range of different test loads and calculates sensed impedance values for each test load. The computer system then predicts a phase value for each load using each respective load impedance value. The computer system back calculates impedance loss model parameters including a source impedance parameter and a leakage impedance parameter based upon the voltage and current sensor data, the predicted phase values, and the impedance values of the test loads.

Abstract: In a method for simulating temperature and electrical characteristics within an circuit, a temperature of at least one volume within the circuit as a function of a resistance within the at least one volume is repeatedly calculated and the resistance as a function of the temperature is repeatedly calculated until the temperature is within a predetermined tolerance of a previous temperature result and until the resistance is within a predetermined tolerance of a previous resistance result. Once the temperature is within a predetermined tolerance of the previous temperature result and the resistance is within a predetermined tolerance of the previous resistance, then an output indicative of the temperature is generated.

Abstract: Method and system are disclosed for statistical circuit simulation. In one embodiment, a computer implemented method for statistical circuit simulation includes providing descriptions of a circuit for simulation, wherein the descriptions include variations of statistical parameters of the circuit, partitioning the circuit into groups of netlists according to variations of statistical parameters of the circuit, simulating the groups of netlists using a plurality of processors in parallel to generate a plurality of output data files, and storing the plurality of output data files in a memory. The method of partitioning the circuit into groups of netlists includes forming the groups of netlists to be simulated in a single instruction multiple data environment, and forming the groups of netlists according to proximity of variations of statistical parameters of the circuit.

Abstract: A semiconductor integrated circuit designing method capable of minimizing a parasitic capacitance generated by an overhead in conductive lines, especially a gate line, a semiconductor integrated circuit according to the designing method, and a fabricating method thereof are provided. A method of designing a semiconductor integrated circuit having a FinFET architecture, includes: performing a pre-simulation of the semiconductor integrated circuit to be designed; designing a layout of components of the semiconductor integrated circuit based on a result of the pre-simulation, the components comprising first and second device areas and a first conductive line extending across the first and second device areas; modifying a first cutting area, that is arranged between the first and second device areas and electrically cuts the first conductive line, according to at least one design rule to minimize an overhead of the first conductive line created by the first cutting area.

Abstract: An apparatus and method for conducting fault sensitivity analysis of the analog portions of a mixed signal circuit design includes simulating the fault free circuit design, inserting a fault into the analog portion of the circuit design, simulating the circuit design with the fault during a fault interval time period, and determining whether the fault is detectable.

Abstract: The present invention discloses a method for simulating a digital circuit. comprising: acquiring a gate-level netlist of the digital circuit, the gate-level netlist indicating at least one gate circuit included in the digital circuit and a connection relationship thereof; modifying the netlist, so as to add a timing and power model of each gate circuit, which is used to calculate a time delay generated when a signal inputted to the gate circuit passes through the gate circuit and a power consumed by the gate circuit during its operation; and simulating the digital circuit based on the modified netlist. By adding into the netlist the timing and power model of each gate circuit included in the digital circuit, a power estimation of the digital circuit can be performed while a function verification is performed on the digital circuit, thus function verification is seamlessly combined with the power estimation.

Abstract: A method is provided that comprises a circuit design that includes multiple design blocks; a power intent specification file that defines a power domain within the circuit design and that identifies design instances within the power domain and that defines a control function to selectively transition the defined power domain between multiple respective power supply values; using a digital simulator to simulate operation of the digital representation while using an analog simulator to simulate operation of the analog representation; wherein simulating the digital representation includes transitioning the defined power domain between supply values from among the multiple respective supply values; wherein simulating the analog representation includes periodically storing in a storage location a power supply value currently in use during digital simulation of the digital representation; and wherein simulating the analog representation includes using the stored currently in use power supply value to supply voltage

Abstract: The described embodiments concern verifying operation of a device, where the device may have one or more inputs and/or one or more outputs. At least one input and/or output is associated with an intelligent connector. An intelligent connector is a combination of a signal transport path and a data structure. The signal transport path may be electrical conductors leading to the device or a physical connector associated with the device. The data structure contains the name of a variable transported by the associated physical connector, an address of the variable itself as a value in memory, and further information of a source device that produces the variable, at least in the form of address or pointer to the source device data structure and the addresses of all destination devices that consume the variable.

Abstract: A specialized low drop-out voltage regulator (LDO) computer system stores a generalized base model of an LDO. The base model includes values representing a circuit topology and a set of analog behavior blocks associated with the generalized LDO. Values of a set of operational parameters associated with a specific model of LDO are input to the specialized LDO computer system from a data sheet associated with the specific model of LDO. The specialized LDO computer system transforms the set of operational parameters into a computer model of the specific LDO. The LDO-specific computer model is output as a netlist or as a set of instantiation control values to control external hardware such as an integrated circuit die tooling system or a computer graphical display system.