Abstract: A method of validating functional testing of system circuitry on an integrated circuit chip, the system circuitry configured to perform a plurality of functions, the integrated circuit chip further comprising debugging circuitry under the control of a debug controller, the debugging circuitry comprising at least one debug unit. The method comprises: at the system circuitry, performing one of the plurality of functions; applying a debug configuration to the at least one debug unit; and at the at least one debug unit, monitoring for a characteristic in the system circuitry's performance of the one of the plurality of functions according to that debug configuration, and reporting to the debug controller.

Abstract: A signal transmitting-receiving circuit includes a first circuit including a first MOS transistor having a gate and a drain, a second MOS transistor having a gate and a drain connected to the gate and drain of the first MOS transistor, and a source connected to ground, and a transmitting terminal transmitting a signal connected to the drains of the first and second MOS transistors; and a second circuit including a receiving terminal receiving the signal transmitted from the transmitting terminal of the first circuit connected to the transmitting terminal, a third MOS transistor having a gate connected to the receiving terminal, a drain connected to a reference voltage generator circuit and a source connected to ground, a resistor connected between the third MOS transistor and the reference voltage generator circuit, and an output terminal connected between the resistor and the third MOS transistor.

Abstract: In one embodiment, a method for compiling an HDL specification for simulation of a circuit design is provided. Using one or more processors the circuit design is elaborated from the HDL specification. Two or more instances of a module of the elaborated design that have a same hardware configuration are determined. Simulation code that models the circuit design is generated. A first portion of the simulation code is configured to model the module having the hardware configuration. For each of the two or more instances, a second portion of the simulation code is configured to, in response to an indication to simulate the instance, execute the first portion of simulation code using a respective set of nets corresponding to the instance.

Abstract: A system and a method for simulation using multiple programming languages is provided. The method can include receiving an annotated source having a first plurality of instructions written in a first programming language and receiving an annotation having a second plurality of instructions written in a second programming language and associated with an annotated instruction from the first plurality of instructions. The method can include extracting the second plurality of instructions to create a routine from the annotation. The method can include building a shared library that contains the routine. The method can include building an application object file by assigning an address to each instruction of the first plurality instructions. The method can include creating an annotation table that contains an address for the annotated instruction and an associated symbol.

Abstract: Any primitive cells or blocks can be represented physically by a Barycenter compact model, and any black box model can also be physically represented by a Barycenter compact model physically. A hierarchical boundary condition between blocks is formulated by the Barycenter model or Barycenter compact model. Hierarchical boundary condition problems between blocks can be limited within two levels only if using the Barycenter model or Barycenter compact model.

Abstract: A computerized apparatus, method and computer product for generating tests. The apparatus comprises: a processor; an interface for obtaining a test template associated with a computerized system that comprises a template segment comprising instructions and directives or related control constructs; a test generator for generating a test associated with the template segment, comprising: a simulator for determining a state of the system associated with an execution of the test; a selector for selecting a template instruction or segment from the test template based on the state of the system; and a generator configured to generate a multiplicity of instructions based on system's state and on the selected template segment, wherein the test generator further comprises a verifier configured to verify that a previously generated instruction is in line with the current state of the system and with the selected template instruction or segment.

Abstract: Any primitive cells or blocks can be represented physically by a Barycenter compact model (or Barycenter model), and any black box model can also be physically represented by a Barycenter compact model physically. A hierarchical boundary condition between blocks is formulated by the Barycenter compact model. Hierarchical boundary condition problems between blocks can be limited within two levels only if using the Barycenter compact model.

Abstract: A design verification system automatically identifies coverage of different constraints for a static model of an electronic device. The static model can be employed by a tool, referred to as a solver, that identifies whether the mathematical relationships of the static model can be reconciled, given a set of user-defined constraints that indicate a desired configuration, or range of configurations, of the electronic device. After a solution for a particular set of user-defined constraints has been identified, a constraints adjustment module can identify, based on coverage information generated by the solver, if other sets of user-defined constraints were implicitly solved by the solver. If such other sets were implicitly solved, the adjustments module can mark the sets as solved, such that they will omitted from constraints used for subsequent solutions of the solver.

Abstract: A method including accessing a first virtual prototype configured to perform a first simulation of a hardware design, identifying checkpoints within the first virtual prototype, each checkpoint including a storage state and/or behavioral state, and determining breakpoints for dividing execution of a second virtual prototype into a series of execution segments, where the second virtual prototype is configured to perform a second simulation of the hardware design, the second virtual prototype includes virtual models representing a separate portion of the hardware design, each virtual model representing a same portion of the hardware design as a corresponding virtual model of the first virtual prototype.

Abstract: The described implementations relate to analysis of computing programs. One implementation provides a technique that can include accessing values of input variables that are processed by test code and runtime values that are produced by the test code while processing the input variables. The technique can also include modeling relationships between the runtime values and the values of the input variables. The relationships can reflect discontinuous functions of the input variables.

Abstract: A method for design simulation includes partitioning a verification task of a design (100) into a first plurality of atomic Processing Elements (PEs-108) having execution dependencies (112), each execution dependency specifying that a respective first PE is to be executed before a respective second PE. The method further includes computing an order for executing the PEs on a multiprocessor device (32), which includes a second plurality of processors (44) operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy. The order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies, irrespective of the scheduling policy. The PEs are executed on the processors in accordance with the computed order and the scheduling policy, to produce a simulation result. A performance of the design is verified responsively to the simulation result.

Abstract: Methods and apparatus for recording and visualizing transactions of a test bench simulation are disclosed. Transaction-specific data generated from a test bench simulation may be displayed in a sequence diagram view to provide a view of the transactions arranged sequentially in time.

Abstract: A system and method are provided for calculating power using a voltage waveform shape measurement from a contactless sensor. An electrically conductive medium carries alternating current (AC) electrical current, associated with an AC voltage, from a source node to a destination node. AC current is measured through the electrically conductive medium. Using a contactless sensor, an AC voltage waveform shape is measured. The power usage at the destination node is calculated in response to the AC current measurement, the measurement of the AC voltage waveform shape, and an AC voltage potential. For simplicity, the AC current and AC voltage waveform shape may both be measured at a first node located between the source node and the destination node. The AC voltage potential used in the power usage calculation may be an estimate, an actual measurement, or a value supplied by an external source (e.g., the power utility).

Abstract: A user interface to a network simulator facilitates the use of application layer parameters and application layer logic. The user interface is configured to allow the user to define the input in a graphic form, or a text/programming form, or a combination of both. The user interface provides common graphic forms for both inputting the data to the simulator as well as for displaying the resultant data from the simulator. In response, the simulator and user interface may provide updated information to reflect the impact of changes made to application layer parameters and logic.

Abstract: The verification apparatus for a semiconductor integrated circuit verifies a logic equivalence before and after modification to the circuit by replacing a memory with a divisional memory model that agrees with the memory in number of input and output pins and verifying logics at an input and an output thereof.

Abstract: Disclosed are embodiments for modeling semiconductor device performance using a single compact model despite changes in performance attribute to model parameter dependency of a single semiconductor device that occur during fitting and/or re-centering due to local layout effects (LLEs) and despite variations in this dependency across multiple related semiconductor devices due to LLEs. In one embodiment, the actual performance attribute to model parameter dependence of a single semiconductor device is fit to a reference dependence so that changes to the compact model are not required even when changes occur in the performance attribute to model parameter dependency during fitting and/or re-centering. In another embodiment, the actual performance attribute to model parameter dependence of each of multiple related semiconductor devices are fit to a reference dependence so that changes to the compact model are not required even when the performance attribute to model parameter dependency varies across the devices.

Abstract: A method for estimating the lifetime of a deep-submicron-generation integrated electronic component, linked to a wear mechanism occurring in previously defined special conditions of use, said component being of a deep submicron type, with very large-scale integration, commercially available off the shelf, wherein one assumes that the same sample population always experiences a failure due to: the most predominant failure mechanism, during the period of useful life, described by an exponential law, and the most critical wear mechanism, represented by a Weibull distribution at the end of the previous period.

Abstract: What-if simulation methods and systems are provided. A design coding in HDL (Hardware Description Language) and a simulation result corresponding to the design are provided. A what-if design scope and a what-if time window are received. A portion of the design is extracted from the design according to the what-if design scope, and primary input signals are determined during the extraction of the sub-design. Then, what-if simulation data is extracted from the simulation result according to the primary input signals and the what-if time window. A what-if test bench is generated according to the what-if simulation data, wherein the what-if simulation data is read, and the signal values are fed to a simulator according to the what-if test bench.

Abstract: Example implementations described herein are directed to automatically determine an optimal NoC topology using heuristic based optimizations. First, an optimal orientation of ports of various hosts is determined based on the system traffic and connectivity specification. Second, the NoC routers to which the host's port are directly connected to are determined in the NoC layout. Third, an optimal set of routes are computed for the system traffic and the required routers and channels along the routes are allocated forming the full NoC topology. The three techniques can be applied in any combination to determine NoC topology, host port orientation, and router connectivity that reduces load on various NoC channels and improves latency, performance, and message transmission efficiency between the hosts.

Abstract: Various embodiments include apparatuses and methods to perform noise analysis on a circuit at a selected condition (e.g., process, voltage, and temperature) using a timing model of the circuit in which the timing model is associated with the selected condition.

Abstract: This invention (900) described a method that generates and uses a test bench for verifying an electrical design module in a semiconductor manufacturing against an electrical reference model containing a sub-circuit that matches the electrical design module. The invention includes providing (902) a description of an electrical design module that includes a plurality of ports. In addition, the invention includes providing (904) a description of an electrical reference model. The invention further includes providing and or creating (92) one or more implicit defines for the reference modules that appear in hierarchy of the electrical reference model. And, the invention includes providing (906) a description file that includes one or more instance definitions. The invention parses (91) the hierarchy of the electrical design model and then processes (96) the description file. The invention then writes (97) the test bench.

Abstract: The embodiments relate to modeling resistance in a multi-fin multi-gate field effect transistor (MUGFET). In these embodiments, a design for a multi-fin MUGFET comprises a gate structure with a horizontal portion traversing multiple semiconductor fins and comprising a plurality of first resistive elements connected in series, with vertical portions adjacent to opposing sides of the semiconductor fins and comprising second resistive elements connected in parallel by the horizontal portion, and with contact(s) comprising third resistive element(s). The total gate resistance is determined based on resistance contributions from the first resistive elements, the second resistive elements and the third resistive element(s), particularly, where each resistive contribution is based on a resistance value of the resistive element, a first fraction of current from the semiconductor fins entering the resistive element and a second fraction of the current from the semiconductor fins exiting the resistive element.

Abstract: A method of circuit simulation includes: simulating, by a processing device, behavior of a heterojunction bipolar transistor device based on at least a first base-emitter voltage of the transistor to determine a first base or collector current density of the HBT device; and determining whether the application of the first base-emitter voltage to the HBT device will result in base current degradation by performing a first comparison of the first current density with a first current density limit.

Abstract: The present invention aims to simulate a response more similar to a actual machine while inhibiting load increase in analog operation. Program configuration of the present invention is a component of a simulation program for circuit design, which is executed by a computer. The computer includes an operation portion, a storage portion, a manipulation portion, and a display portion, so that the computer exerts a function of a circuit design simulator, and as a macro model of an operational amplifier for use in the circuit design simulator, enabling the computer to act by simulating a response of the operational amplifier on the circuit design simulator. The macro model of the operational amplifier includes a control portion (LMT1) for generating output exception in the event of input exception or power supply exception of the operational amplifier.

Abstract: The systems and methods of the present disclosure calibrate impedance loss model parameters associated with an electrosurgical system having no external cabling or having external cabling with a fixed or known reactance, and obtain accurate electrical measurements of a tissue site by compensating for impedance losses associated with the transmission line of an electrosurgical device using the calibrated impedance loss model parameters. A computer system stores voltage and current sensor data for a range of different test loads and calculates sensed impedance values for each test load. The computer system then predicts a phase value for each load using each respective load impedance value. The computer system back calculates impedance loss model parameters including a source impedance parameter and a leakage impedance parameter based upon the voltage and current sensor data, the predicted phase values, and the impedance values of the test loads.

Abstract: In a method for simulating temperature and electrical characteristics within an circuit, a temperature of at least one volume within the circuit as a function of a resistance within the at least one volume is repeatedly calculated and the resistance as a function of the temperature is repeatedly calculated until the temperature is within a predetermined tolerance of a previous temperature result and until the resistance is within a predetermined tolerance of a previous resistance result. Once the temperature is within a predetermined tolerance of the previous temperature result and the resistance is within a predetermined tolerance of the previous resistance, then an output indicative of the temperature is generated.

Abstract: Method and system are disclosed for statistical circuit simulation. In one embodiment, a computer implemented method for statistical circuit simulation includes providing descriptions of a circuit for simulation, wherein the descriptions include variations of statistical parameters of the circuit, partitioning the circuit into groups of netlists according to variations of statistical parameters of the circuit, simulating the groups of netlists using a plurality of processors in parallel to generate a plurality of output data files, and storing the plurality of output data files in a memory. The method of partitioning the circuit into groups of netlists includes forming the groups of netlists to be simulated in a single instruction multiple data environment, and forming the groups of netlists according to proximity of variations of statistical parameters of the circuit.

Abstract: A semiconductor integrated circuit designing method capable of minimizing a parasitic capacitance generated by an overhead in conductive lines, especially a gate line, a semiconductor integrated circuit according to the designing method, and a fabricating method thereof are provided. A method of designing a semiconductor integrated circuit having a FinFET architecture, includes: performing a pre-simulation of the semiconductor integrated circuit to be designed; designing a layout of components of the semiconductor integrated circuit based on a result of the pre-simulation, the components comprising first and second device areas and a first conductive line extending across the first and second device areas; modifying a first cutting area, that is arranged between the first and second device areas and electrically cuts the first conductive line, according to at least one design rule to minimize an overhead of the first conductive line created by the first cutting area.

Abstract: An apparatus and method for conducting fault sensitivity analysis of the analog portions of a mixed signal circuit design includes simulating the fault free circuit design, inserting a fault into the analog portion of the circuit design, simulating the circuit design with the fault during a fault interval time period, and determining whether the fault is detectable.

Abstract: The present invention discloses a method for simulating a digital circuit. comprising: acquiring a gate-level netlist of the digital circuit, the gate-level netlist indicating at least one gate circuit included in the digital circuit and a connection relationship thereof; modifying the netlist, so as to add a timing and power model of each gate circuit, which is used to calculate a time delay generated when a signal inputted to the gate circuit passes through the gate circuit and a power consumed by the gate circuit during its operation; and simulating the digital circuit based on the modified netlist. By adding into the netlist the timing and power model of each gate circuit included in the digital circuit, a power estimation of the digital circuit can be performed while a function verification is performed on the digital circuit, thus function verification is seamlessly combined with the power estimation.

Abstract: The described embodiments concern verifying operation of a device, where the device may have one or more inputs and/or one or more outputs. At least one input and/or output is associated with an intelligent connector. An intelligent connector is a combination of a signal transport path and a data structure. The signal transport path may be electrical conductors leading to the device or a physical connector associated with the device. The data structure contains the name of a variable transported by the associated physical connector, an address of the variable itself as a value in memory, and further information of a source device that produces the variable, at least in the form of address or pointer to the source device data structure and the addresses of all destination devices that consume the variable.

Abstract: A method is provided that comprises a circuit design that includes multiple design blocks; a power intent specification file that defines a power domain within the circuit design and that identifies design instances within the power domain and that defines a control function to selectively transition the defined power domain between multiple respective power supply values; using a digital simulator to simulate operation of the digital representation while using an analog simulator to simulate operation of the analog representation; wherein simulating the digital representation includes transitioning the defined power domain between supply values from among the multiple respective supply values; wherein simulating the analog representation includes periodically storing in a storage location a power supply value currently in use during digital simulation of the digital representation; and wherein simulating the analog representation includes using the stored currently in use power supply value to supply voltage

Abstract: A specialized low drop-out voltage regulator (LDO) computer system stores a generalized base model of an LDO. The base model includes values representing a circuit topology and a set of analog behavior blocks associated with the generalized LDO. Values of a set of operational parameters associated with a specific model of LDO are input to the specialized LDO computer system from a data sheet associated with the specific model of LDO. The specialized LDO computer system transforms the set of operational parameters into a computer model of the specific LDO. The LDO-specific computer model is output as a netlist or as a set of instantiation control values to control external hardware such as an integrated circuit die tooling system or a computer graphical display system.

Abstract: A method, computer program product, and computer system for analyzing code to improve efficiency of simulating a hardware system. A computer identifies one or more functions calling an application programming interface of a hardware simulator simulating the hardware system. In response to determining that left hand sides of respective one or more Boolean expressions are associated with the one or more functions calling the application programming interface and right hand sides are not associated with the one or more functions calling the application programming interface, the computer identifies the respective one or more Boolean expressions as one or more improvement points in source code for verifying a hardware model of the hardware system.

Abstract: A method and circuit for device specific configuration of an operating voltage is provided. A circuit design is analyzed to determine a maximum gate-level delay for the circuit design. A minimum voltage value corresponding to the maximum gate-level delay is determined along with a default voltage value corresponding to a default gate-level delay. A voltage scaling factor corresponding to the minimum voltage and default voltage values is determined. The circuit design is synthesized such that the synthesized design includes the voltage scaling value. The synthesized design specifies setting an operating voltage to a value of a startup voltage value scaled by the voltage scaling value.

Abstract: In the verification of an electronic design such as a microprocessor, a set of generic transaction types is applied to a unit in a unit simulation environment and then the same set of generic transaction types is applied to the unit in a larger (e.g., element) simulation environment using an abstraction layer which can interface with both a unit translation layer of the unit simulation environment and an element translation layer of the element simulation environment. The abstraction layer may comprise a generic driver interface which issues generic commands having command parameters including a command type, an address, and operand data. The invention can be extended to multiple units which make up the element, or to multiple elements in the element environment. The invention can further be extended in a hierarchical fashion to other levels of simulation environments, e.g., unit-element-system.

Abstract: A system, method, and computer program product are provided for applying a callback function to data values. In use, a plurality of data values and a callback function are identified. Additionally, the callback function is recursively applied to the plurality of data values in order to determine a result. Further, the result is returned.

Abstract: A 3-D multi-physics design environment (“3-D design environment”) for designing and simulating multi-physics devices such as MEMS devices is discussed. The 3-D design environment is programmatically integrated with a system modeling environment that is suitable for system-level design and simulation of analog-signal ICs, mixed-signal ICs and multi-physics systems. A parameterized MEMS device model is created in a 3-D graphical view in the 3-D design environment using parameterized model components that are each associated with an underlying behavioral model. After the MEMS device model is completed, it may be exported to a system modeling environment without subjecting the model to preliminary finite element meshing.

Abstract: An analog circuit simulator includes a processor that is configured to search design data for analog circuits and an analog node connecting the analog circuits; collect variable information that concerns voltage and current variables and is related to input to and output from the analog node; convert the variable information into time functions; and compute the time functions upon each occurrence of a given event and execute simulation of the analog node.

Abstract: In accordance with an exemplary simulation technique, an improved selective application of Newton-Raphson iterations can improve accuracy while ensuring good performance. In this method, selectively applying Newton-Raphson iteration in a simulation of a unit of the integrated circuit design can include determining second order effects to define a linearity value. Newton-Raphson iteration is performed when the linearity value is less than a linearity threshold and convergence of the simulation is not achieved.

Abstract: Techniques for emulation-based functional qualification are disclosed that use an emulation platform to replace simulation in mutation-based analysis. A method for functional qualification of an integrated circuit design includes receiving an integrated circuit design having one or more mutations. Emulation setup and activation simulation are performed in parallel to maximize computing resources. A prototype board can then be programed according to the integrated circuit design and a verification module. A set of test patterns and response generated by a simulation of the integrated circuit using the set of test patterns are stored in a memory of the prototyping board allowing enumeration of mutants to occur at in-circuit emulation speed.

Abstract: A dataset comprising a plurality of hardware component entries and one or more connection entries is processed. Each hardware component entry indicates a hardware component for simulation. Each connection entry indicates a plurality of hardware components to be connected. A plurality of simulated hardware components is created based, at least in part, on the plurality of hardware component entries. A simulated connection between a first simulated hardware component of the plurality of simulated hardware components and a second simulated hardware component of the plurality of simulated hardware components is created based, at least in part, on a connection entry of the one or more connection entries.

Abstract: A dataset comprising a plurality of hardware component entries and one or more connection entries is processed. Each hardware component entry indicates a hardware component for simulation. Each connection entry indicates a plurality of hardware components to be connected. A plurality of simulated hardware components is created based, at least in part, on the plurality of hardware component entries. A simulated connection between a first simulated hardware component of the plurality of simulated hardware components and a second simulated hardware component of the plurality of simulated hardware components is created based, at least in part, on a connection entry of the one or more connection entries.

Abstract: The present disclosure relates to a configurable modular card. The card comprises a board, at least one processor and at least one memory on the board, a configurable input/output unit comprising a plurality of configurable inputs and outputs, a bus for providing electronic data exchange there between, and a power supply comprising a plurality of configurable power supply circuits. The configurable input/output unit has a predefined output for sending a broadcast message and a predefined input for receiving a broadcast response message. The processor configures the plurality of inputs and outputs of the configurable input/output unit based on the broadcast response message. The processor configures the plurality of power circuits of the power supply based on the broadcast response message. The processor generates testing signals to the plurality of inputs and outputs of the configurable input/output unit and to the plurality of power circuits of the power supply.

Abstract: The present invention is achieved as software which operates on a computer system and which performs calculation by receiving various data as inputs, and which outputs values. The present invention is applicable to a coarse-grained system architecture model including the foregoing event-driven simulation and receives, as inputs, execution time T and the number of memory accesses, N, in the simulation step of the model. Thus, various estimates at the occurrence of memory access conflict are obtained at a simulation speed sufficient for evaluating the effect of the memory access conflict and comparing it with many alternative architectures without information on the correct timing of memory accesses in consideration of memory synchronous accesses and arbitration. The results of this simulation are estimated simulation-step execution time T? under memory access conflict and memory-bandwidth utilization factors {U?i} in individual simulation steps under memory access conflict.

Abstract: A system having a function block execution framework. Function blocks may be for use in a control system design. These blocks may be selected from a library of a function block engine. Selected function blocks may be executed for operational purposes. They may be continuously executed by a processor to maintain operational status. However, since a function block engine and a resulting system of function blocks may be operated with battery power, executions of function blocks may be reduced by scheduling the executions of function blocks to times only when they are needed. That means that the processor would not necessarily have to operate continuously to maintain continual execution of the function blocks and thus could significantly reduce consumption of battery power.

Abstract: Using an adaptive square mesh for parasitic extraction, small squares of a predetermined minimum size will be placed where accuracy in the parasitic calculations is most critical—around edges, contacts and vias, and corners. Then, in areas where the parasitic analysis is less critical, for example in open spaces, a more coarse grid consisting of larger squares may be used to calculate the parasitic values in those spaces. Squares in the mesh may increase in size gradually to provide more accurate results.

Abstract: A design apparatus generates an optimal design condition by design space exploration. The apparatus including a source code parsing (301) which parses source code and generates a parse tree, a cluster generation task (302) which generates clusters based on the parse tree, each of the clusters including a group of source codes which can operate independently, a log file task (303) which generates a log file based on a structure of the cluster, and a comparison task (304) which compares a first log file of a previous cluster with a second log file of a current cluster and re-uses previous exploration result based on a comparison result, the first log file being obtained from a previous design space exploration, the second log file being generated from a current operation.

Abstract: A system, method and computer program product for sorting Integrated Circuits (chips), particularly microprocessor chips, and particularly that predicts chip performance or power for sorting purposes. The system and method described herein uses a combination of performance-predicting parameters that are measured early in the process, and applies a unique method to project where the part, e.g., microprocessor IC, will eventually be sorted. Sorting includes classifying the IC product to a subset of a family of products with the product satisfying certain performance characteristics or specifications, in the early stages of manufacturing, e.g., before the end product is fully fabricated.

Abstract: A method of constructing an optimized network simulation environment according to the present invention includes the steps of identifying communication equipment models for relaying a message to/from real equipments out of communication equipment models within a network model, as major models, calculating the order of abstraction priority for major models, performing batch-mode abstraction for non-major models, driving a simulation, determining whether a difference between a simulation execution time and an actual time spent is within an allowable delay value, performing adaptive abstraction for the major models, and evaluating a result of the simulation. If the method according to the present invention is used, a real-time simulation having fidelity and reliability for the function and operation of real equipments can be guaranteed.