Abstract: A 3-D multi-physics design environment (“3-D design environment”) for designing and simulating multi-physics devices such as MEMS devices is discussed. The 3-D design environment is programmatically integrated with a system modeling environment that is suitable for system-level design and simulation of analog-signal ICs, mixed-signal ICs and multi-physics systems. A parameterized MEMS device model is created in a 3-D graphical view in the 3-D design environment using parameterized model components that are each associated with an underlying behavioral model. After the MEMS device model is completed, it may be exported to a system modeling environment without subjecting the model to preliminary finite element meshing.

Abstract: A method, computer program product, and computer system for analyzing code to improve efficiency of simulating a hardware system. A computer identifies one or more functions calling an application programming interface of a hardware simulator simulating the hardware system. In response to determining that left hand sides of respective one or more Boolean expressions are associated with the one or more functions calling the application programming interface and right hand sides are not associated with the one or more functions calling the application programming interface, the computer identifies the respective one or more Boolean expressions as one or more improvement points in source code for verifying a hardware model of the hardware system.

Abstract: A method and circuit for device specific configuration of an operating voltage is provided. A circuit design is analyzed to determine a maximum gate-level delay for the circuit design. A minimum voltage value corresponding to the maximum gate-level delay is determined along with a default voltage value corresponding to a default gate-level delay. A voltage scaling factor corresponding to the minimum voltage and default voltage values is determined. The circuit design is synthesized such that the synthesized design includes the voltage scaling value. The synthesized design specifies setting an operating voltage to a value of a startup voltage value scaled by the voltage scaling value.

Abstract: In the verification of an electronic design such as a microprocessor, a set of generic transaction types is applied to a unit in a unit simulation environment and then the same set of generic transaction types is applied to the unit in a larger (e.g., element) simulation environment using an abstraction layer which can interface with both a unit translation layer of the unit simulation environment and an element translation layer of the element simulation environment. The abstraction layer may comprise a generic driver interface which issues generic commands having command parameters including a command type, an address, and operand data. The invention can be extended to multiple units which make up the element, or to multiple elements in the element environment. The invention can further be extended in a hierarchical fashion to other levels of simulation environments, e.g., unit-element-system.

Abstract: A system, method, and computer program product are provided for applying a callback function to data values. In use, a plurality of data values and a callback function are identified. Additionally, the callback function is recursively applied to the plurality of data values in order to determine a result. Further, the result is returned.

Abstract: An analog circuit simulator includes a processor that is configured to search design data for analog circuits and an analog node connecting the analog circuits; collect variable information that concerns voltage and current variables and is related to input to and output from the analog node; convert the variable information into time functions; and compute the time functions upon each occurrence of a given event and execute simulation of the analog node.

Abstract: In accordance with an exemplary simulation technique, an improved selective application of Newton-Raphson iterations can improve accuracy while ensuring good performance. In this method, selectively applying Newton-Raphson iteration in a simulation of a unit of the integrated circuit design can include determining second order effects to define a linearity value. Newton-Raphson iteration is performed when the linearity value is less than a linearity threshold and convergence of the simulation is not achieved.

Abstract: Techniques for emulation-based functional qualification are disclosed that use an emulation platform to replace simulation in mutation-based analysis. A method for functional qualification of an integrated circuit design includes receiving an integrated circuit design having one or more mutations. Emulation setup and activation simulation are performed in parallel to maximize computing resources. A prototype board can then be programed according to the integrated circuit design and a verification module. A set of test patterns and response generated by a simulation of the integrated circuit using the set of test patterns are stored in a memory of the prototyping board allowing enumeration of mutants to occur at in-circuit emulation speed.

Abstract: A dataset comprising a plurality of hardware component entries and one or more connection entries is processed. Each hardware component entry indicates a hardware component for simulation. Each connection entry indicates a plurality of hardware components to be connected. A plurality of simulated hardware components is created based, at least in part, on the plurality of hardware component entries. A simulated connection between a first simulated hardware component of the plurality of simulated hardware components and a second simulated hardware component of the plurality of simulated hardware components is created based, at least in part, on a connection entry of the one or more connection entries.

Abstract: A dataset comprising a plurality of hardware component entries and one or more connection entries is processed. Each hardware component entry indicates a hardware component for simulation. Each connection entry indicates a plurality of hardware components to be connected. A plurality of simulated hardware components is created based, at least in part, on the plurality of hardware component entries. A simulated connection between a first simulated hardware component of the plurality of simulated hardware components and a second simulated hardware component of the plurality of simulated hardware components is created based, at least in part, on a connection entry of the one or more connection entries.

Abstract: The present invention is achieved as software which operates on a computer system and which performs calculation by receiving various data as inputs, and which outputs values. The present invention is applicable to a coarse-grained system architecture model including the foregoing event-driven simulation and receives, as inputs, execution time T and the number of memory accesses, N, in the simulation step of the model. Thus, various estimates at the occurrence of memory access conflict are obtained at a simulation speed sufficient for evaluating the effect of the memory access conflict and comparing it with many alternative architectures without information on the correct timing of memory accesses in consideration of memory synchronous accesses and arbitration. The results of this simulation are estimated simulation-step execution time T? under memory access conflict and memory-bandwidth utilization factors {U?i} in individual simulation steps under memory access conflict.

Abstract: The present disclosure relates to a configurable modular card. The card comprises a board, at least one processor and at least one memory on the board, a configurable input/output unit comprising a plurality of configurable inputs and outputs, a bus for providing electronic data exchange there between, and a power supply comprising a plurality of configurable power supply circuits. The configurable input/output unit has a predefined output for sending a broadcast message and a predefined input for receiving a broadcast response message. The processor configures the plurality of inputs and outputs of the configurable input/output unit based on the broadcast response message. The processor configures the plurality of power circuits of the power supply based on the broadcast response message. The processor generates testing signals to the plurality of inputs and outputs of the configurable input/output unit and to the plurality of power circuits of the power supply.

Abstract: A system having a function block execution framework. Function blocks may be for use in a control system design. These blocks may be selected from a library of a function block engine. Selected function blocks may be executed for operational purposes. They may be continuously executed by a processor to maintain operational status. However, since a function block engine and a resulting system of function blocks may be operated with battery power, executions of function blocks may be reduced by scheduling the executions of function blocks to times only when they are needed. That means that the processor would not necessarily have to operate continuously to maintain continual execution of the function blocks and thus could significantly reduce consumption of battery power.

Abstract: Using an adaptive square mesh for parasitic extraction, small squares of a predetermined minimum size will be placed where accuracy in the parasitic calculations is most critical—around edges, contacts and vias, and corners. Then, in areas where the parasitic analysis is less critical, for example in open spaces, a more coarse grid consisting of larger squares may be used to calculate the parasitic values in those spaces. Squares in the mesh may increase in size gradually to provide more accurate results.

Abstract: A design apparatus generates an optimal design condition by design space exploration. The apparatus including a source code parsing (301) which parses source code and generates a parse tree, a cluster generation task (302) which generates clusters based on the parse tree, each of the clusters including a group of source codes which can operate independently, a log file task (303) which generates a log file based on a structure of the cluster, and a comparison task (304) which compares a first log file of a previous cluster with a second log file of a current cluster and re-uses previous exploration result based on a comparison result, the first log file being obtained from a previous design space exploration, the second log file being generated from a current operation.

Abstract: A system, method and computer program product for sorting Integrated Circuits (chips), particularly microprocessor chips, and particularly that predicts chip performance or power for sorting purposes. The system and method described herein uses a combination of performance-predicting parameters that are measured early in the process, and applies a unique method to project where the part, e.g., microprocessor IC, will eventually be sorted. Sorting includes classifying the IC product to a subset of a family of products with the product satisfying certain performance characteristics or specifications, in the early stages of manufacturing, e.g., before the end product is fully fabricated.

Abstract: A method for changing, by using a computer, an arrangement of strings that are arranged along an inner periphery of a graphic and partially overlap one another is offered. The computer arranges the strings in a radial pattern from a reference point determined within the graphic, determines whether overlapping strings are present, and moves the reference point in a direction to separate from the overlapping strings when the computer determines that the overlapping strings are present.

Abstract: A method of constructing an optimized network simulation environment according to the present invention includes the steps of identifying communication equipment models for relaying a message to/from real equipments out of communication equipment models within a network model, as major models, calculating the order of abstraction priority for major models, performing batch-mode abstraction for non-major models, driving a simulation, determining whether a difference between a simulation execution time and an actual time spent is within an allowable delay value, performing adaptive abstraction for the major models, and evaluating a result of the simulation. If the method according to the present invention is used, a real-time simulation having fidelity and reliability for the function and operation of real equipments can be guaranteed.

Abstract: A system and a method are disclosed for concurrently simulating multiple parameters of a design of an electrical circuit. A first simulation time and a first set of environmental parameters is determined and the design is simulated for the determined first simulation time. Multiple simulation engines, each analyzing on simulation parameter, simulate the design based on the first set of environmental parameters and the first set of environmental parameters are updated based on the results of each of the simulation engines. A determination is made whether the simulation results have converged. If the simulation results have not converged, each of the analysis engines simulated the design using the updated set of environmental parameters. If the simulation results are determined to be convergent, the simulation system determines a second simulation time and repeats the simulation process for the second simulation time.

Abstract: An apparatus and method are provided for communicating with a plurality of physical memory circuits. In use, at least one virtual memory circuit is simulated where at least one aspect (e.g. power-related aspect, etc.) of such virtual memory circuit(s) is different from at least one aspect of at least one of the physical memory circuits. Further, in various embodiments, such simulation may be carried out by a system (or component thereof), an interface circuit, etc.

Abstract: A fixed-outline floorplanning approach for mixed-size modules is disclosed. Firstly, evenly distribute mixed-size circuit modules to whole chip area based on different requirements such as wire-length, routability, or thermal in the global distribution stage. To maintain the global distribution result and satisfy the fixed-outline constraint, generate a slicing tree by recursively applying partition algorithm to divide modules distributed in a given region into several sub-regions. Then, to remove overlap between circuit modules and find a best solution, use bottom-up shape curve merging and top-down back tracing procedure to generate a slicing tree. The shape curve for each leaf in the tree is built first by enumerated packing. Then, the curves in the tree are merged iteratively from bottom to top, and feasible solutions in the shape curve of the root node are identified according to the fixed-outline constraint. Finally, the best solution is determined by a top-down back tracing procedure.

Abstract: A method for modeling a conductor in a substrate and a dielectric coating formed between the conductor and the substrate includes meshing a surface of the conductor into multiple conductor cells, each cell including a corresponding node in network topology, modeling a first displacement current flowing from each cell through the substrate, and modeling a second displacement current flowing from each cell through the dielectric coating. Modeling the first displacement current includes determining a first branch connecting the node corresponding to each conductor cell to ground, the first branch having at least a first capacitance. Modeling the second displacement current includes determining a coating capacitance connected in series between the node corresponding to each conductor cell and the first branch, the coating capacitance representing a capacitive effect of the dielectric layer.

Abstract: Performing a transient analysis with a compact FET model that is predominantly intended for DC analysis, such as an IDDQ leakage model, to enable toggling logic states in sequential logic circuits that cannot otherwise be examined in a DC analysis. An embodiment enables examining the DC or AC conditions of any logic state of any logic circuit in a DC or AC analysis, and additionally, it eliminates a potentially long execution time of a transient analysis with a DC model. Further solved is the present need to run two simulations and to maintain two netlists in order to overcome being unable to toggle certain logic states in the DC analysis. The invention achieves the aforementioned in a single simulation with a single netlist that calculates the DC operating circuit conditions with a model A on the fly at predetermined times or in certain logic states, during a transient analysis with a model B.

Abstract: In a method of simulating electrical characteristics of a circuit board having a plurality of features, the plurality of features is projected onto a planar construct. A Delaunay triangulation routine for generating a triangular mesh that corresponds to the single planar construct is executed on the digital computer. A routine that generates a Voronoi diagram corresponding to the triangular mesh. An equivalent circuit for each triangle is determined. The equivalent circuit includes exactly three sub-circuits that couple a vertex within the triangle to a vertex within an adjacent triangle and exactly one sub-circuit that couples the vertex within the triangle to a reference plane. A routine solves, for each triangle, an equation describing an electrical characteristic value based on the equivalent circuit corresponding to the triangle. A routine for generating a human-perceptible indication of the electrical characteristic value for each triangle is executed on the digital computer.

Abstract: A system, method, and computer program product for automatically approximating conventional Monte Carlo statistical device model evaluation for circuit simulation with drastic speed improvements, while preserving significant accuracy. Embodiments enable quick inspection of the effects of process mismatch variations on single devices and even large circuits compared to standard computationally prohibitive Monte Carlo analysis. Statistical device model variation is calculated as if all such variation is due to changes in threshold voltage, even though other physical phenomena are known to contribute. Threshold voltage variation is modeled as a function of statistical variation, device size, and working bias condition. Circuit simulation is faster when the full internal device model parameter set is not rebuilt for every Monte Carlo analysis iteration. Embodiments are compatible with both conventional SPICE and newer Fast SPICE simulations.

Abstract: A system and methods are provided for verifying a hardware design for an electronic circuit. The method may include: providing a hardware design description for the electronic circuit; extracting a set of design constraints from the hardware design description, where the set of design constraints represents the electronic circuit in terms of signals and logical operations performed on the signals; creating an abstraction model from the set of design constraints, where the abstraction model abstracts one or more of the logical operations in the set of design constraints by replacing the abstracted logical operations with uninterpreted functions; and property checking the abstraction model in relation to one or more design properties. When a violation in the electronic circuit is detected by the property checking step, the feasibility of the violation is then checked and, if the violation is deemed infeasible, the abstraction model is refined.

Abstract: A behavior model is provided, which is configured to simulate one aspect of the behavior of a component apart from the component model for the component. The behavior model can be included in a circuit model used to simulate operation of a circuit. The circuit model can include a component model for a component and a corresponding behavior model, which is located in parallel or series with the component model. The component model and behavior model can collectively simulate all of the behavior of the component within the circuit. In an embodiment, the behavior model simulates snapback behavior exhibited by the component.

Abstract: A circuit simulation apparatus acquires wiring connection information indicating connection data in an electric circuit, selects a component constituting the circuit based on the wiring connection information, performs a setting of replacing the selected component with each resistor having different resistance values, generates at least one of netlists using the acquired wiring connection information and at least one of the set resistance values, calculates a value of an equivalent power source and a value of an internal resistance thereof for a part of the circuit using the acquired wiring connection information and at least one of the generated netlists, and calculates a resistance value of the selected component and a power consumption for the resistance value using the value of the equivalent power source and the value of the internal resistance.

Abstract: A netlist description that includes embedded code segments for describing a circuit is preprocessed in order to replace the embedded code segments with corresponding preprocessed code segments, where the preprocessed code segments include netlist code that can be parsed and executed. To perform this preprocessing, programming languages that include scripting operations are identified for the embedded code segments in the netlist description. A pipeline preprocessor that includes preprocessors for the identified programming languages is configured to sequentially process the netlist description and replace the embedded code segments with the corresponding preprocessed code segments.

Abstract: A method for simulating a circuit includes running a first prototype of the circuit a predetermined number of cycles behind a second prototype of the circuit, and running a hardware emulator of the circuit in accordance with an input trace received by the first prototype and the second prototype.

Abstract: A method for modeling a transistor includes providing a transistor model having at least a source node, a drain node, and a gate node, simulating operation of a device using the transistor model in a computing apparatus, and generating an offset voltage at the gate node depending on a magnitude of a current passing through the device.

Abstract: In a circuit simulation tool in a computer system having one or more computer processors and computer-readable storage, a method for characterizing a driven oscillator circuit having an oscillator coupled to a time-varying input signal includes retrieving information provided in a circuit description of the oscillator circuit. The method also includes forming a frequency-domain harmonic balance equation for the oscillator circuit using the retrieved information provided in the circuit description of the oscillator circuit. The harmonic balance equation includes a first differential operator in a frequency domain of the input signal and a product of a differential operator in a second frequency domain of the oscillator and a frequency variable of the oscillator. The frequency variable is independent of the frequency domain of the input signal. The method further includes solving the harmonic balance equation to obtain a waveform description of the oscillator circuit.

Abstract: Mechanisms are provided for predicting effects of soft errors on an integrated circuit device design. A data processing system is configured to implement a unified derating tool that includes a machine derating front-end engine used to generate machine derating information, and an application derating front-end engine used to generate application derating information, for the integrated circuit device design. The machine derating front-end engine executes a simulation of the integrated circuit device design to generate the machine derating information. The application derating front-end engine executes an application workload on existing hardware similar in architecture to the integrated circuit device design and injects a fault into the existing hardware during execution of the application workload to generate application derating information.

Abstract: A method for visually verifying an implementation of a design is described. The method includes integrating logical design data, physical design data, and physical implementation data into a common data format and graphically displaying the commonly formatted data to provide a visualization of the design, the visualization including a spatial context component associated with the physical implementation data.

Abstract: The present disclosure relates to a computer-implemented method for simulating an analog and mixed-signal circuit design having a digital circuit segment connected to an analog circuit segment at a connection point. The method may include inserting a bidirectional interface element at the connection point located between the digital circuit segment and the analog circuit segment. The method may further include splitting the digital circuit segment into a plurality of transistor network models to provide for bidirectional transfer of data between the analog circuit segment and the digital circuit segment.

Abstract: The subject application relates to a method and system for power delivery network analysis. The present disclosure is directed towards a computer-implemented method for analyzing a power delivery network (PDN) system. The method may include receiving at least one of a chip power model, a package power model and a board power model at the computing device and co-simulating at least two of the chip power model, the package power model, and the board power model. Numerous other features are also within the scope of the present disclosure.

Abstract: Systems and methods for performing multi-message transaction based performance simulations of SoC IP cores within a Network on Chip (NoC) interconnect architecture by accurately imitating full SoC behavior are described. The example implementations involve simulations to evaluate and detect NoC behavior based on execution of multiple transactions at different rates/times/intervals, wherein each transaction can contain one or more messages, with each message being associated with a source agent and a destination agent. Each message can also be associated with multiple parameters such as rate, size, value, latency, among other like parameters that can be configured to indicate the execution of the transaction by a simulator to simulate a real-time scenario for generating performance reports for the NoC interconnect.

Abstract: A computer-readable, non-transitory medium stores a program that causes a computer to execute a process including acquiring a unique coefficient that is unique to a device in a circuit under test and is included in a function expressing fluctuation of leak current of the device; detecting as a group and based on the unique coefficient, devices having an identical or similar characteristic; converting first random variables into a single second random variable, the first random variables expressing fluctuation of leak current unique to each of the detected devices; yielding a function that expresses fluctuation of leak current of the detected devices, using the second random variable; and outputting the yielded function.

Abstract: Verification IPs for the verification of semiconductor chip designs are designed to support specific interface protocols. Verification IP is expensive or unavailable to test devices with interfaces of uncommon protocols. Verification IP that uses a generic interface protocol, used in conjunction with simple adapters between interfaces of the VIP that use the generic protocol and interfaces of the device under test that use specific protocols, are reused to test interfaces with different specific protocols if the generic protocol supports a superset of the features of the specific protocols.

Abstract: A method for simulation of lithography overlay is disclosed which comprises storing alignment parameters used to align a semiconductor wafer prior to a lithography step; storing process control parameters used during the lithography step on the semiconductor wafer; storing overlay parameters measured after the lithography step; calculating alternative alignment parameters and alternative process control parameters. The alternative alignment parameters and the alternative process control parameters are added to cleansed overlay parameters to obtain simulated lithography overlay data.

Abstract: A method for automatic design of a circuit evaluates thermal effects and electrical effects in a coupled way. A description of the circuit is obtained in terms of a list of simulator nodes or netlist. Using the description, the electrical behavior of the circuit and the thermal behavior of the circuit is simulated. The simulation includes configuring the simulation operation for operating with descriptions of models or sub-circuits of the circuit that are defined using a thermal node. An equivalent current generator is connected to the thermal node to force an equivalent current representing dissipated power. A voltage that is produced on the thermal node is associated with an increase in temperature of the model or sub-circuit with respect to the global temperature.

Abstract: A simulation instructing unit instructs a simulation unit, which generates signal characteristics, to generate the signal characteristics. A characteristic value extracting unit extracts, from the signal characteristics, characteristic values for distinguishing between a signal characteristic generated by setting a first simulation parameter and a signal characteristic generated by a second simulation parameter. A simulation parameter determining unit determines a first mapping relationship from the characteristic values to the simulation parameters with the characteristic values obtained by setting a plurality of set values in the simulation parameters and with the set values.

Abstract: A method of generating an application programming interface (API) for an electronic circuit. A graphical user interface is displayed through which a user can initiate generation of the API. A component is selected from a plurality of components for placement in said electronic circuit. The component represents an implementable function in the electronic circuit. The component is configured using the graphical user interface. The data pertaining to the selected component and the configuration of the component is stored. The graphical user interface is utilized to access the stored data. The interface is initiated to invoke a processing of said data which causes a generation of the application programming interface. The application interface is for controlling the function of the component in said electronic circuit.

Abstract: A computing device may be used to create a model that includes a block. The block may represent a function corresponding to a simulation. Measurement points may be inserted into the model. The model may be used to create a simulation, and the measurement points may be used to measure operational characteristics corresponding to the block.

Abstract: Aspects of the invention relate to techniques for mask rule checking based on curvature information. The curvature information comprises convex curvature information and concave curvature information. The convex curvature information for a vertex of a mask feature may comprise a convex curvature value derived based on the size of a circle that passes through the vertex, is tangent to an edge and does not cross any other edges. The concave curvature information for the vertex may comprise a concave curvature value derived based on the size of a circle that is tangent to two edges that form the vertex and does not cross any other edges, and of which distance from the vertex measured from the nearest point is no more than a predetermined number. The generated curvature information is compared with threshold curvature information to determine mask rule violations.

Abstract: Accurate simulation of two-terminal resistive random access memory (RRAM) behavior is accomplished by solving equations including state variables for filament length growth, filament width growth, and temperature. Such simulations are often run in a SPICE environment. Highly accurate models simulate the dynamic nature of filament propagation and multiple resistive states by using a sub-circuit to represent an RRAM cell. In the sub-circuit, voltages on floating nodes control current output while the voltage dropped across the sub-circuit controls growth and temperature characteristics. Properly executed, such a sub-circuit can accurately model filament growth at all phases of conductance including dynamic switching and a plurality of resistive states.

Abstract: A heat dissipation simulator of a component on a printed circuit board (PCB) includes a simulation board and a simulated heat source. The simulation board includes an iron layer and a plastic layer. The simulated heat source includes a simulation chip, a thermal, and a heat sink. The simulation chip, the thermal piece, and the heat sink are mounted on the simulation board in that order. The heat dissipation simulator replaces a sample of the PCB with the component for simulating working states of the component on the PCB.

Abstract: Methods for producing layout data for devices are described. One method includes using a genetic algorithm to determine a structure of a thermally-operated actuator. Another method includes receiving a three-dimensional model of a device, a design-rule set, and parameter ranges. Layout data are produced for devices having various combinations of parameter values in the parameter ranges.

Abstract: The present invention relates to the field of power line carrier communication simulation technology, and more particularly to a method and system for simulating power line carrier communication system. In the simulation model of the sending end and the simulation model of the receiving end constructed by the simulation method and system, each of the channel encoding model and the channel decoding model includes a simulation model of a ARM core chip and a peripheral logic circuit of the ARM core chip, the sending end includes a simulation model of a RS error correction encoding algorithm of the ARM core chip, and the receiving end includes a simulation model of a RS error correction decoding algorithm of the ARM core chip.

Abstract: A method for design simulation includes partitioning a verification task of a design (100) into a first plurality of atomic Processing Elements (PEs-108) having execution dependencies (112), each execution dependency specifying that a respective first PE is to be executed before a respective second PE. The method further includes computing an order for executing the PEs on a multiprocessor device (32), which includes a second plurality of processors (44) operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy. The order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies, irrespective of the scheduling policy. The PEs are executed on the processors in accordance with the computed order and the scheduling policy, to produce a simulation result. A performance of the design is verified responsively to the simulation result.