Abstract: Sum and carry signals are formed representing a product of a first and a second operand. A bias signal is formed having a value determined by a sign of a product of the first and the second operand. An output signal is provided based on an addition of the sum signal, the carry signal, a sign-extended addend, and the bias signal. A portion of the output signal, a saturated minimum value, or a saturated maximum value, is selected as a final result based on the sign of the product and a sign of the output signal.

Abstract: A specialized processing block for a programmable logic device includes circuitry for performing multiplications and sums thereof, as well as circuitry for performing floating point operations. The floating point circuitry preferably includes rounding and normalization circuitry. To perform mantissa multiplications, the floating point circuitry preferably relies on the aforementioned multipliers of the specialized processing block.

Abstract: An apparatus for expanding an immediate vector of restricted data structures may include logic connected to a first memory and a second memory connected to the logic. The first memory may store the immediate vector of restricted data structures that specify distinct floating point numbers. The immediate vector may have a fixed number of bits. The logic may expand the vector of restricted data structures into a number of corresponding expanded data structures that also specify the distinct floating point numbers. Each of the expanded data structures may also have the fixed number of bits. The second memory may store the number of corresponding expanded data structures.

Abstract: A computer-implemented method for executing a floating-point calculation where an exact value of an associated result cannot be expressed as a floating-point value is disclosed. The method involves: generating an estimate of the associated result and storing the estimate in memory; calculating an amount of error for the estimate; determining whether the amount of error is less than or equal to a threshold of error for the associated result; and if the amount of error is less than or equal to the threshold of error, then concluding that the estimate of the associated result is a correctly rounded result of the floating-point calculation; or if the amount of error is greater than the threshold of error, then testing whether the floating-point calculation constitutes an exception case.

Abstract: Methods, apparatus and systems are disclosed for the generation of range-constrained test cases for verification of designs of arithmetic floating point units. Given three ranges of floating point numbers Rx, Ry, Rz, a floating point operation (op), and a rounding-mode (round), three floating point numbers x, y, z are generated such that x?Rx, y?Ry, z?Rz, and z=round ( x op y). Solutions are provided for add and subtract operations. Range constraints are imposed on the input operands and on the result operand of floating point add and subtract instructions to target corner cases when generating test cases for use in verification of floating point hardware.

Abstract: A multiplier circuit that operates on a novel complex data format where the real and imaginary parts of the source and result operands are represented by single precision floating point numbers. The invention provides direct support for complex numbers in floating point representation, thus reducing the number of instructions and processor cycles with improved performance.

Abstract: The subject matter disclosed herein provides methods and systems for converting fixed-point soft bit values, provided by a demapper, into floating-point soft bits values. In one aspect, there is provided a method. The method may include receiving, from a demapper, soft bits formatted as a fixed-point value. Moreover, the soft bits may be converted from the fixed-point value to a floating-point value. The floating-point value is punctured to remove a bit. The converted soft bits are provided to a buffer to enable decoding of the buffered soft bits. Related systems, apparatus, methods, and/or articles are also described.

Abstract: Methods, apparatus and systems are disclosed for the generation of range-constrained test cases for verification of designs of arithmetic floating point units. Given three ranges of floating point numbers Rx, Ry, Rz, a floating point operation (op), and a rounding-mode (round), three floating point numbers x, y, z are generated such that x?Rx, y?Ry, z?Rz, and z=round ( x op y). Solutions are provided for add and subtract operations. Range constraints are imposed on the input operands and on the result operand of floating point add and subtract instructions to target corner cases when generating test cases for use in verification of floating point hardware.

Abstract: Digit counts c? after the decimal point of attribute values in a structured document are acquired (S404). The detected attribute values are transformed into value character strings that represent integer values by manipulating the decimal point positions of the attribute values in accordance with a maximum digit count of the acquired digit counts (S406). The transformed value character strings and the maximum digit count C are encoded (S407).

Abstract: Methods, apparatus and systems are disclosed for the generation of range-constrained test cases for verification of designs of arithmetic floating point units. Given three ranges of floating point numbers Rx, Ry, Rz, a floating point operation (op), and a rounding-mode (round), three floating point numbers x, y, z are generated such that x ? Rx, y ? Ry, z ? Rz, and z=round ( x op y). Solutions are provided for add and subtract operations. Range constraints are imposed on the input operands and on the result operand of floating point add and subtract instructions to target corner cases when generating test cases for use in verification of floating point hardware.

Abstract: Techniques for providing arbitrary precision floating number (APFN) processing are disclosed. In some aspects, an APFN store may be used to store a large number (i.e., an APFN) having many significant digits, which in turn may enable a high degree of precision in mathematical operations. An APFN module may be used to create and define the APFN store. The APFN module may enable a user to define a precision (significant digits) for the large number that corresponds to the size of an array of bytes in the APFN store that are allocated for storing the large number. In further aspects, the APFN store may be used to store additional intermediary data and a resultant.

Abstract: A floating point (FP) shifter for use with FP adders providing a shifted FP operand as a power of the exponent base (usually two) multiplied by a FP operand. First arithmetic processor using at least one FP shifter with FP adder. FP adder for N FP operands creating FP result, where N is at least three. Second arithmetic processor including at least one FP adder for N operands. Descriptions of FP shifter and FP adder for implementing their operational methods. Implementations of FP shifter and FP adder.

Abstract: A compiler (or interpreter) detects source language instructions performing arithmetic operations using a fixed point format (preferably packed decimal). Where the operation can be performed without loss of precision or violation of other constraints of the source language, the compiler automatically converts the operands to a floating point format (preferably Decimal Floating Point (DFP)) having hardware support, and re-converts results to the original fixed point format. Preferably, the compiler may combine multiple operations and instructions in an expression tree, analyze the tree, and selectively convert where possible. The compiler preferably performs a heuristic cost judgment in determining whether to use a particular conversion.

Abstract: An interface to a dynamically configurable arithmetic unit can include data alignment modules, where each data alignment module receives input variables being associated with one or more arithmetic expressions. The interface can include multiplexers coupled to the data alignment modules, wherein a data alignment module has outputs coupled to a first multiplexer. The first multiplexer can have a selection line and an output coupled to an input port of the dynamically configurable arithmetic unit. The interface can include a second multiplexer having input instructions and the selection line, where each instruction is associated with one of the arithmetic expressions and has an operation to be performed by the dynamically configurable arithmetic unit. The second multiplexer is configurable to provide selected ones of the input instructions to the dynamically configurable arithmetic unit through an output of the second multiplexer responsive to the selection line.

Abstract: A data processing apparatus and method includes multiplier logic operable to multiply the first and second n-bit significands to produce a pair of 2n-bit vectors. Half adder logic is arranged to produce a plurality of carry and sum bits representing a corresponding plurality of most significant bits of the pair of 2n-bit vectors. The first adder logic then performs a first sum operation with a first rounded result and a second adder logic performs a second sum operation with a second rounded result. The required n-bit result is then derived from either the first rounded result or the second rounded result. The data processing apparatus takes advantage of a property of the half adder form to enable a rounding increment value to be injected prior to performance of the first and second sum operations without requiring full adders to be used to inject the rounding increment value.

Abstract: A normalization factor for a current frame of a signal may be determined. The normalization factor may depend on an amplitude of the current frame of the signal. The normalization factor may also depend on values of states after one or more operations were performed on a previous frame of a normalized signal. The current frame of the signal may be normalized based on the normalization factor that is determined. The states' normalization factor may be adjusted based on the normalization factor that is determined.

Abstract: A math coprocessor 1300 includes a multiply-accumulate unit 1600. Multiplier-accumulate unit 1600 includes a multiplier array 1603 for selectively multiplying first and second operands, the first and second operands having a data type selected from the group including floating point and integer data types. An adder 1604 selectively performs addition and subtraction operations on third and fourth operands, the third and fourth operands selected by multiplexer circuitry from the contents of a set of associated source registers, data output from multiplier array 1603 and data output from adder 1604.

Abstract: Embodiments of the present invention include code generation methods. In one embodiment, a table of patterns is generated. Each pattern in the table includes an FMA (fused multiply-add) DAG (Directed Acyclic Graph), a canonical form equivalent of the FMA DAG, and a shape corresponding to the canonical form equivalent. Incoming floating-point expressions are matched against the patterns in the table during compilation of a program to obtain optical sequences of FMA, FMS (fused multiply-subtract), and FNMA (fused negate multiply-add) instructions as compiled instructions for computing the floating point expressions.

Abstract: Detection of whether a result of a floating point operation is safe. Characteristics of the result are examined to determine whether the result is safe or potentially unsafe, as defined by the user. An instruction is provided to facilitate detection of safe or potentially unsafe results.

Abstract: Disclosed herein is a floating-point number arithmetic circuit for efficiently supplying data to be performed arithmetic operation. The floating-point number arithmetic circuit includes an floating-point number arithmetic unit for performing a predetermined floating-point number arithmetic operation on a floating-point number of a predetermined precision, and a converting circuit for converting data into the floating-point number of predetermined precision and supplying the floating-point number of the predetermined precision to at least either one of input terminals of the floating-point number arithmetic unit.

Abstract: The invention set forth herein describes a mechanism for efficiently performing extended precision operations on multi-word source operands. Corresponding data words of the source operands are processed together via each instruction of a cascading sequence of instructions. State information generated when each instruction is processed is stored in condition code flags. The state information is optionally used in the processing of subsequent instructions in the sequence and/or accumulated with previously set state information.

Abstract: A floating-point processing unit for a succession of floating-point operations. An exponent adjustor is coupled to receive numerical inputs and configured to generate first adjusted values from the numerical inputs. The first adjusted values have equivalent exponents as between corresponding first adjusted values. A first operation specific floating-point processing unit (OFPU) is coupled to receive the first adjusted values and includes first arithmetic circuitry configured for a first floating-point operation on the first adjusted values to provide first numerical results. The first numerical results are not normalized prior to a second floating-point operation.

Abstract: According to embodiments of the subject matter disclosed in this application, decimal floating-point multiplications and/or decimal fixed-point multiplications may be implemented using existing hardware for binary number operations. The implementation can be carried out in software, in hardware, or in a combination of software and hardware. Pre-calculated constants that are approximations to negative powers of 10 and stored in binary format may be used for rounding multiplication results to a designated precision by multiplying the results with a pre-calculated constant. Additionally, several parts of a decimal multiplication may be carried out in parallel. Furthermore, a simple comparison with a constant instead of an expensive remainder calculation may be used for midpoint detection and exactness determination.

Abstract: A method for transmitting the value of a parameter in a compressed form, the method comprising the steps of: accepting successive numbers representing the value of a parameter; manipulating each number, the manipulation comprising placing the number in a form comprising a mantissa and an exponent, and defining a transmission mantissa to be transmitted; transmitting to a receiver, in turn, the transmission mantissas only of the successive numbers; and receiving the transmission mantissas of the successive numbers at the receiver, characterised by the steps of maintaining a record, at the receiver, of a receiver variable, the receiver variable initially corresponding to the exponent of an initial number; formulating at the receiver, for each received transmission mantissa, a reconstructed number comprising at least the transmission mantissa and an exponent corresponding to the receiver variable; and altering the receiver variable in a first manner if the transmission mantissa of the current number fulfils a fir

Abstract: The present invention provides a solution to the shortcomings of the traditional two's complement system that is commonly utilized in modern computing systems and digital signal processors for calculating harmonic analysis using a discrete time-frequency transform. In the negative two's complement processor a n-bit number, A, has a sign bit, an?1, and n?1 fractional bits, an?2, an?3, . . . , a0. The value of an n-bit fractional negative two's complement number is: A = a n - 1 + ? i = 0 n - 2 ? - a i ? 2 i - n + 1 .

Abstract: A computer system comprises a processing unit configured to process fixed size data words comprising at least one exponent field of variable size and a mantissa of variable size; an input device configured to provide data words to the processing unit; and an output device configured to output data words processed by the processing unit.

Abstract: Systems and methods for encoding floating point numbers. A system can include encoding logic which encodes invalid floating point representations as valid data. Decoding logic can be used to recognize the invalid floating point representations and map can provide the invalid floating point representations to valid data values. The decoding logic then can provide the valid data values so that operations on the valid data values can be performed in accordance with instructions received from an associated program.

Abstract: A computer system execute summation processing even if the computing sequence is not adhered to in a system for computing a sum of floating point data of a plurality of nodes. Each node sends floating point data to a reduction mechanism, and the reduction mechanism computes the sums only for a group of which exponent sections have a highest value and a group of which exponent sections have a second highest value, and adds the sum of the group of which the exponent sections have a highest value and the sum of the group of which the exponent sections have a second highest value. By this, the consistency of the computation result can be guaranteed even if the sum is computed regardless the computing sequence of the values.

Abstract: Apparatus and methods are provided to perform floating point operations that are adaptive to the precision formats of input operands. The apparatus includes adaptive conversion logic and a tagged register file. The adaptive conversion logic receives the input operands, where each of the input operands is of a corresponding precision. The adaptive conversion logic also records the corresponding precision for use in subsequent floating point operations. The tagged register file is coupled to the adaptive conversion logic. The tagged register file stores the each of the input operands, and stores the corresponding precision and furthermore associates the corresponding precision with the each of the input operands. The subsequent floating point operations are performed at a precision level according to the corresponding precision.

Abstract: A method of generating a test case from a given test case structure, the method including generating instructions for the given test case structure, propagating predefined results in a backwards manner, randomly generating remaining operands of the test case structure in a forwards manner, and calculating a result for the test case by determining missing input operands and storing these input operands in both the temporary register file and the initial register file, and calculating missing results and storing all results in the temporary register file.

Abstract: In this invention we describe a new type of computer—infinity computer—that is able to operate with infinite, infinitesimal, and finite numbers in such a way that it becomes possible to execute the usual arithmetical operations with all of them. For the new computer it is shown how the memory for storage of these members is organized and how the new arithmetic logic unit (NALU) executing arithmetical operations with them works.

Abstract: Method to convert a hexadecimal floating point number (H) into a binary floating point number by using a Floating Point Unit (FPU) with fused multiply add with an A-register a B-register for two multiplicand operands and a C-register for an addend operand, wherein a leading zero counting unit (LZC) is associated to the addend C-register, wherein the difference of the leading zero result provided by the LZC and the input exponent (E) is calculated by a control unit and determines based on the Raw-Result-Exponent a force signal (F) with special conditions like ‘Exponent Overflow’, ‘Exponent Underflow’, and ‘Zero Result’.

Abstract: A method, system and program product are provided for establishing one or more decimal floating point (DFP) operand for facilitating testing of a decimal floating point instruction. The method includes obtaining an encoded DFP operand previously generated for testing the decimal floating point instruction, and logically modifying at least one bit of the encoded DFP operand without decoding the encoded DFP operand to obtain an additional encoded DFP operand. In one embodiment, m sequential bits of the encoded DFP operand, n randomly generated bits (wherein n=m), and a logical operation (such as an AND, OR, XOR or SHIFT) are employed in modifying the previously generated, encoded DFP operand.

Abstract: According to embodiments of the subject matter disclosed in this application, decimal floating-point additions and/or decimal fixed-point additions may be implemented using existing hardware for binary number operations. The implementation can be carried out in software, in hardware, or in a combination of software and hardware. Pre-calculated constants that are approximations to negative powers of 10 and stored in binary format may be used for rounding addition results to a designated precision by multiplying the results with a pre-calculated constant. Additionally, several parts of a decimal multiplication may be carried out in parallel. Furthermore, a simple comparison with a constant instead of an expensive remainder calculation may be used for midpoint detection and exactness determination.

Abstract: An apparatus for expanding an immediate vector of restricted data structures may include logic connected to a first memory and a second memory connected to the logic. The first memory may store the immediate vector of restricted data structures that specify distinct floating point numbers. The immediate vector may have a fixed number of bits. The logic may expand the vector of restricted data structures into a number of corresponding expanded data structures that also specify the distinct floating point numbers. Each of the expanded data structures may also have the fixed number of bits. The second memory may store the number of corresponding expanded data structures.

Abstract: A numeric value display method uses a display processing section. When an operation to read out a numeric value from storage means and display it is executed, if the numeric value has a greater number of digits than the number of digits which can be displayed on a numeric value display device, the display processing section divides the numeric value into a predetermined number of digits and displays a part of the numeric value on the numeric value display device in such a manner that it is possible to know which part of the numeric value is displayed. Moreover, each time operation keys are pressed, the display processing section resets a display diction variable (P) required for controlling the display position for each of the divided parts of digits preset and switches the part of the numeric value to be output to the numeric value display device.

Abstract: A floating point unit includes a floating point adder to perform a floating point addition operation between first and second floating point numbers each having an exponent and a mantissa. The floating point unit also includes an alignment shifter that may calculate a shift value corresponding to a number of bit positions to shift the second mantissa such that the second exponent value is the same as the first exponent value. The alignment shifter may detect an overshift condition, in which the shift value is greater than or equal to a selected overshift threshold value. The selected overshift threshold value comprises a base 2 number in a range of overshift values including a minimum overshift threshold value and a maximum overshift threshold value, and which has a largest number of a consecutive of bits that are zero beginning at a least significant bit.

Abstract: Systems and methods for managing floating point variables are described in the present disclosure. According to one example, an embodiment of a method includes analyzing a constraint on a floating point variable in a system that supports both floating point variables and integer variables. The constraint is designed to have the ability to numerically limit the domain of the floating point variable. The method also includes determining whether or not the floating point variable can be handled as an integer variable and converting the floating point variable to a pseudo integer variable when it is determined that the floating point variable can be handled as an integer variable. This conversion of the floating point variable to a pseudo integer variable allows the domain of the floating point variable to be processed as an integer domain.

Abstract: Techniques for providing arbitrary precision floating number (APFN) processing are disclosed. In some aspects, an APFN store may be used to store a large number (i.e., an APFN) having many significant digits, which in turn may enable a high degree of precision in mathematical operations. An APFN module may be used to create and define the APFN store. The APFN module may enable a user to define a precision (significant digits) for the large number that corresponds to the size of an array of bytes in the APFN store that are allocated for storing the large number. In further aspects, the APFN store may be used to store additional intermediary data and a resultant.

Abstract: A residue generator for calculation and correction of a residue value. The residue generator includes a residue-generation tree connected with an operand register at an input of the residue generator including a plurality of register-bits receiving and carrying bits of numerical data.

Abstract: A method and system for performing a binary mode and hexadecimal mode Multiply-Add floating point operation in a floating point arithmetic unit according to a formula A*C+B, wherein A, B and C operands each have a fraction and an exponent part expA, expB and expC and the exponent of the product A*C is calculated and compared to the exponent of the addend under inclusion of an exponent bias value dedicated to use unsigned biased exponents, wherein the comparison yields a shift amount used for aligning the addend with the product operand, wherein a shift amount calculation provides a common value CV for both binary and hexadecimal according to the formula (expA+expC?expB+CV).

Abstract: A method for conversion between a decimal floating-point number and an order-preserving format has been disclosed. The method encodes numbers in the decimal floating-point format into a format which preserves value ordering. This encoding allows for fast and direct string comparison of two values. Such an encoding provides normalized representations for decimal floating-point numbers and supports type-insensitive comparisons. Type-insensitive comparisons are often used in database management systems, where the data type is not specified for values to compare. In addition, the original decimal floating-point format can be recovered from the order-preserving format.

Abstract: In a binary floating point processor, the exponents of each of the various types of operands are recoded into an internal format, by biasing the exponents with the minimum exponent value of the result precision (“Emin”), i.e., the recoded value of the exponent is the represented value of the exponent minus Emin. Emin depends only on the result precision of the instruction that is currently being executed in the binary floating point processor. The exponent computations are then performed in this new format. The underflow check for all result precisions is a check against zero and overflow checks are performed against a positive number that depends on the result precision. The exponent values are in a 2's complement representation, so the underflow check simply becomes a check of the sign bit.

Abstract: An embodiment of the present invention is a technique to perform floating-point operations. A floating-point (FP) squarer squares a first argument to produce an intermediate argument. The first and intermediate arguments have first and intermediate mantissas and exponents. A FP multiply-add (MAD) unit performs a multiply-and-add operation on the intermediate argument, a second argument, and a third argument to produce a result having a result mantissa and a result exponent. The second and third arguments have second and third mantissas and exponents, respectively.

Abstract: A method and apparatus for perfectly lossless and minimal-loss interconversion of digital color data between spectral color spaces (RGB) and perceptually based luma-chroma color spaces (Y?CBCR) is disclosed. In particular, the present invention provides a process for converting digital pixels from R?G?B? space to Y?CBCR space and back, or from Y?CBCR space to R?G?B? space and back, with zero error, or, in constant-precision implementations, with guaranteed minimal error. This invention permits digital video editing and image editing systems to repeatedly interconvert between color spaces without accumulating errors. In image codecs, this invention can improve the quality of lossy image compressors independently of their core algorithms, and enables lossless image compressors to operate in a different color space than the source data without thereby becoming lossy.

Abstract: A mantissa/exponent splitter splits an input value X=(1+X1/223)×(2?X2) into a mantissa X1 and an exponent X2. An interpolation processor references the mantissa/exponent splitter using the mantissa X1 and determines a power value (log2(1+X1/223)) through an interpolation process. A logarithmic calculator determines a logarithmic value Z=log2XY=Y(X2+log2 (1+X1/223)) from the exponent X2 and the power value from the interpolation processor. The integer/fraction splitter splits the logarithmic value Z into an integer Zint and a fraction Zamari. The interpolation processor references a power of fraction table storage unit in response to the fraction Zamari and determines a power value (2?Zamari)through the interpolation process. The power calculator determines XY=2?Z=(2?Zamari)×(2?Zint), thereby resulting in the input value X to the power of Y.

Abstract: The forcing of the result or output of a rounder portion of a floating point processor occurs only in a fraction non-increment data path within the rounder and not in the fraction increment data path within the rounder. The fraction forcing is active on a corner case such as a disabled overflow exception. A disabled overflow exception may be detected by inspecting the normalized exponent. If a disabled overflow exception is detected, the round mode is selected to execute only in the non-increment data path thereby preventing the fraction increment data path from being selected.

Abstract: Data processing apparatus and method perform data processing operations on floating point data elements. The data processing apparatus has processing logic for performing data processing operations on the floating point data elements, and decode logic operable to decode a data processing instruction in order to determine a corresponding data processing operation to be performed by the processing logic. The data processing instruction has an m-bit immediate value encoded therein. Further, constant generation logic is provided to perform a logical operation on the m-bit immediate value in order to generate an n-bit floating point constant for use as at least one input floating point data element for the processing logic when performing the corresponding data processing operation. The values “n” and “m” are integers, and n is greater than m. This approach provides a particularly efficient technique for generating floating point constants.

Abstract: A computation processor outputs whether a carry-out is generated, by incrementing a result of computation by 1, during rounding of the result of the computation. The computation processor includes a computing unit that performs the computation; a shift amount calculating unit that calculates a shift amount of the result of the computation; a normalizing unit that performs normalization of the result of the computation, by using the shift amount; a predicting unit that, when the result of the computation is shifted by an amount equal to or more than a predetermined shift amount by using the shift amount, predicts whether each of bits in a predetermined region of a shift result is 1, in parallel with the normalization; and a detecting unit that detects a generation of the carry-out, by receiving a normalized result from the normalizing unit and a predicted result from the predicting unit.

Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.