Abstract: A method (and structure) for executing linear algebra subroutines, includes, for an execution code controlling operation of a floating point unit (FPU) performing the linear algebra subroutine execution, unrolling instructions to preload data into a floating point register (FReg) of the FPU. The unrolling generates an instruction to load data into the FReg and the instruction is inserted into a sequence of instructions that execute the linear algebra subroutine on the FPU.

Abstract: A method and system are described for performing an arithmetic operation such as multiplication or division of a fixed point variable measured at runtime by a floating point constant known at compile-time. The floating point constant is converted into a mantissa and a base-2 exponent at compile-time. The mantissa and exponent are preferably combined into a single unit (a word) of memory. At runtime either single multiplication and accumulation or matrix multiplication and accumulation is preferably achieved by a microprocessor or DSP instruction designed to use the mantissa-exponent pairs stored in a word of memory. The microprocessor instruction multiplies a fixed point runtime variable x by the mantissa and the result is shifted to the right or left as indicated by the exponent, which is preferably a 2's complement number. The complete instruction sequence to perform the multiplication can be made reentrant and can be pipelined.

Abstract: During operation of an encoder, a signal vector (x) is received. A first multi-precision operand (??k) will be generated based on the signal vector to be encoded. A mantissa operand and an exponent operand are generated. Both the mantissa operand and the exponent operand are representative of a second multi-precision operand that is based on the signal vector to be encoded. A portion of ??k is selected to be modified based on the exponent operand. A part of ??k is modified based on the mantissa operand to produce a modified multi-precision operand (??k+1). Finally, a multi-precision codeword is generated for use in a corresponding decoder.

Abstract: A computer emulates a fixed-point operation that is normally performed on fixed-point operands, by use of a floating-point operation that is normally performed on floating-point operands. Several embodiments emulate a fixed-point operation by: expanding at least one fixed-point operand into a floating-point representation (also called “floating-point equivalent”), performing, on the floating-point equivalent, a floating-point operation that corresponds to the fixed-point operation, and reducing a floating-point result into a fixed-point result. The just-described fixed-point result may have the same representation as the fixed-point operand(s) and/or any user-specified fixed-point representation, depending on the embodiment. Also the operands and the result may be either real or complex, and may be either scalar or vector. The above-described emulation may be performed either with an interpreter or with a compiler, depending on the embodiment.

Abstract: In modern iterative coding systems such as LDPC decoder and turbo-convolutional decoder in which the invention may be used, the core computations can often be reduced to a sequence of additions and subtractions alternating between logarithm and linear domains A computationally efficient and robust approximation method for log and exp functions is described which involves using a simple bit mapping between fixed point fractional data format and floating point format. The method avoids costly lookup tables and complex computations and further reduces the core processing to a sequence of additions and subtractions using alternating fixed point and floating point processing units.

Abstract: Methods, apparatus and systems are disclosed for the generation of range-constrained test cases for verification of designs of arithmetic floating point units. Given three ranges of floating point numbers Rx, Ry, Rz, a floating point operation (op), and a rounding-mode (round), three floating point numbers x, y, z are generated such that x?Rx, y?Ry, z?Rz, and z=round ( x op y). Solutions are provided for add and subtract operations. Range constraints are imposed on the input operands and on the result operand of floating point add and subtract instructions to target corner cases when generating test cases for use in verification of floating point hardware.

Abstract: Methods, apparatus and systems are disclosed for the generation of range-constrained test cases for verification of designs of arithmetic floating point units. Given three ranges of floating point numbers Rx, Ry, Rz, a floating point operation (op), and a rounding-mode (round), three floating point numbers x, y, z are generated such that x ? Rx, y ? Ry, z ? Rz, and z=round ( x op y). Solutions are provided for add and subtract operations. Range constraints are imposed on the input operands and on the result operand of floating point add and subtract instructions to target corner cases when generating test cases for use in verification of floating point hardware.

Abstract: A computer is programmed to emulate a fixed-point operation that is normally performed on fixed-point operands, by use of a floating-point operation that is normally performed on floating-point operands. Several embodiments of the just-described computer emulate a fixed-point operation by: expanding at least one fixed-point operand into a floating-point representation (also called “floating-point equivalent”), performing, on the floating-point equivalent, a floating-point operation that corresponds to the fixed-point operation, and reducing a floating-point result into a fixed-point result. The just-described fixed-point result may have the same representation as the fixed-point operand(s) and/or any user-specified fixed-point representation, depending on the embodiment. Also depending on the embodiment, the operands and the result may be either real or complex, and may be either scalar or vector.

Abstract: A method for accuracy-aware analysis of a program involving obtaining source code for the program comprising a floating point variable, instrumenting the source code to associate an accuracy-aware tracking structure with the floating-point variable to obtain instrumented source code, compiling to instrumented source code to obtain instrumented compiled code, and executing the instrumented compiled code, wherein executing the instrumented compiled code comprises using the accuracy-aware tracking structure to track an operation on the floating-point variable.

Abstract: A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. For composition and decomposition, one or more instructions may be employed, including one or more convert instructions.

Abstract: A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format.

Abstract: A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format.

Abstract: A method of streamlining floating-point conversions includes determining a source coefficient and a source exponent of an input value represented by a floating-point number in a source base; estimating an approximated target exponent (ATE) using the source coefficient and the source exponent, in the event the source coefficient has a non-zero value; determining whether the ATE exceeds a maximum exponent so as to result an overflow, and outputting a predefined overflow value in the event of an overflow; determining whether the ATE exceeds a minimum exponent so as to result an underflow, and outputting a predefined underflow value in the event of an underflow; and in the event the ATE does not result in either an overflow or underflow, converting the input value to an output value represented by a converted coefficient, a converted base and the exponent of the output value.

Abstract: A method and system including transmitting data in an architectural format between execution units in a multi-type instruction set architecture and converting data received in the architectural format to an internal format and data output in the internal format to the architectural format based on an operation code and a data type of a microinstruction.

Abstract: High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, significantly less overhead is incurred than would be incurred with specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic.

Abstract: The present invention concerns a method for transcoding a N bits word into a M bits word with M<N. The invention is applicable in various fields and more particularly in the display field. The method comprises the following steps:-breaking down the N bits word into an exponent part and a mantissa part having each a size which varies according to the value of said N bits word, the size of the mantissa part increasing with the value of said N bits word, and -encoding the exponent part of the N bits word into a variable number of bits A and removing, if need be, least significant bits of the mantissa part in order to obtain a mantissa with a variable number of bits B, with A+B=M.

Abstract: Circuitry is provided for performing a non-arithmetic operation in relation to at least one number. The circuitry includes a first part for carrying out the non-arithmetic operation in relation to the at least one number, the first part providing a result. A second part is arranged to identify at least one characteristic of the at least one number and to provide an output and correction circuitry for providing, if necessary, a correct result in dependence on the output of the second part, wherein said first and second parts are arranged to operate in parallel.

Abstract: Using different number of data bits to represent points in corresponding different sections of a high order monotonic curve in a floating point format. More number of data bits are used to represent one section of the curve, while correspondingly fewer data bits are used to represent another section of the curve. In one embodiment, the differences of mantissa values of successive points are stored in a memory to obtain compression, but with different number of bits for different sections of the curve. The absolute values of the exponents for each section are also stored. The high order monotonic curve may represent a de-gamma curve and used in processing video signals which are to be de-gamma corrected.

Abstract: To provide a floating point arithmetic circuit for efficiently defecting an error, which has a large numerical error, with a less circuit amount, the floating point arithmetic circuit comprises a first arithmetic unit for outputting a first arithmetic result, a second arithmetic unit for outputting a second arithmetic result, and a comparison circuit for making a comparison between the first and the second arithmetic results by a predetermined bit width.

Abstract: A compiler (or interpreter) detects source language instructions performing arithmetic operations using a fixed point format (preferably packed decimal). Where the operation can be performed without loss of precision or violation of other constraints of the source language, the compiler automatically converts the operands to a floating point format (preferably Decimal Floating Point (DFP)) having hardware support, and re-converts results to the original fixed point format. Preferably, the compiler may combine multiple operations and instructions in an expression tree, analyze the tree, and selectively convert where possible. The compiler preferably performs a heuristic cost judgment in determining whether to use a particular conversion.

Abstract: An apparatus and method for floating point exception prediction and recovery. In one embodiment, a processor may include instruction fetch logic configured to issue a first instruction from one of a plurality of threads and to successively issue a second instruction from another one of the plurality of threads. The processor may also include floating-point arithmetic logic configured to execute a floating-point instruction issued by the instruction fetch logic from a given one of the plurality of threads, and further configured to determine whether the floating-point instruction generates an exception, and may further include exception prediction logic configured to predict whether the floating-point instruction will generate the exception, where the prediction occurs before the floating-point arithmetic logic determines whether the floating-point instruction generates the exception.

Abstract: A multi-stage floating-point accumulator includes at least two stages and is capable of operating at higher speed. In one design, the floating-point accumulator includes first and second stages. The first stage includes three operand alignment units, two multiplexers, and three latches. The three operand alignment units operate on a current floating-point value, a prior floating-point value, and a prior accumulated value. A first multiplexer provides zero or the prior floating-point value to the second operand alignment unit. A second multiplexer provides zero or the prior accumulated value to the third operand alignment unit. The three latches couple to the three operand alignment units. The second stage includes a 3-operand adder to sum the operands generated by the three operand alignment units, a latch, and a post alignment unit.

Abstract: A method for providing a 16-bit floating point data representation where the 16-bit floating point data representation may be operated upon by a microprocessors native floating point instruction set. The method contemplates the use a variety of techniques for converting the 16-bit floating point number into a representative native floating point value. Thereafter, the native microprocessor floating point instruction set may perform operations upon the converted data. Upon completion, the native floating point data representation may be converted back into the 16-bit floating point value.

Abstract: A computing system is adapted to calculate an exponent portion of a floating point data type, and is preferably employed in calculating powers of two in a computer language processing environment supporting a union declaration functionality and a left shift functionality. Accordingly, an input receives an exponent value, and a bias application module biases the exponent value based on a selected precision of a floating point data type. Also, a storage module stores the exponent value in a storage variable having a size determined based on the selected precision. Further, a left shift application module shifts the exponent value left by a number of bits determined based on the selected precision. Finally, an output returns the storage variable as the floating point data type having the selected precision.

Abstract: A high precision floating point emulator and associated method for emulating subject program code on a target machine where the subject machine base operands possess a different precision than the target machine. The high precision floating point emulator is provided for the emulation of subject program code instructions having a higher precision than that supported by the target machine architecture by utilizing intermediate calculations having values with a higher precision than that supported by the target machine.

Abstract: Computing an output interval includes producing a first result from a conditional selection using a first operand, a second operand, and a third operand, the operands respectively including a second input interval upper-point, a first input interval upper-point, and a first input interval lower-point. Next, computing an output interval includes producing a second result from the conditional selection, the operands respectively including a second input interval upper-point, the first input interval upper-point, and the first input interval lower-point. Furthermore, computing an output interval includes producing a third result from a conditional division using the first operand, the second operand, and the third operand, the operands respectively including the first result, the second input interval upper-point, and the second input interval lower-point.

Abstract: A floating point max/min circuit for determining the maximum or minimum of two floating point operands includes a first analysis circuit configured to determine a format of a first floating point operand of the two floating point operands based upon floating point status information encoded within the first floating point operand, a second analysis circuit configured to determine a format of a second floating point operand of the two floating point operands based upon floating point status information encoded within the second floating point operand, a decision circuit, coupled to the first analysis circuit and to the second analysis circuit and responding to a function control signal that indicates the threshold condition is one of a maximum of the two floating point operands and a minimum of the two floating point operands, for generating at least one assembly control signal based on the format of a first floating point operand, the format of a second floating point operand, and the function control signal,

Abstract: Computing an output interval includes producing a first product resulting from a conditional multiplication using a first operand, a second operand, and a third operand. Next a second product is produced resulting from the conditional multiplication using the first operand, the second operand, and the third operand. Then a third product is produced resulting from the conditional multiplication using the first operand, the second operand, and the third operand. Next a fourth product is produced resulting from the conditional multiplication using the first operand, the second operand, and the third operand. And finally, the output interval is produced including an output interval lower-point and an output interval upper-point, the output interval lower-point being the minimum of the first product and the third product, and the output interval upper-point being the maximum of the second product and the fourth product.

Abstract: A method and apparatus for accumulating arbitrary length strings of input values, such as floating point values, in a layered tree structure such that the order of adds at each layer is maintained. The accumulating utilizes a shared adder, and includes means for directing initial inputs and intermediate result values.

Abstract: A floating point comparator circuit for comparing a plurality of floating point operands includes a plurality of analysis circuits, one for each of the floating point operands, configured to determine a format of each of the floating point operands based upon floating point status information encoded within each of the floating point operands, and a result generator circuit coupled to the analysis circuits, the result generator circuit configured to generate a result signal based on the format determined by each analysis circuit and based on a comparative relationship among the floating point operands. The format of each of the floating point operands may be from a group including: not-a-number (NaN), infinity, normalized, denormalized, zero, invalid operation, overflow, underflow, division by zero, exact, and inexact.

Abstract: A floating point total order comparator circuit for comparing a first floating point operand and a second floating point operand includes a first analysis circuit for determining a format of the first floating point operand based upon floating point status information encoded within the first floating point operand, a second analysis circuit for determining a format of the second floating point operand based upon floating point status information encoded within the second floating point operand, and a result generator circuit coupled to the analysis circuits for producing a result indicating a total order comparative relationship between the first floating point operand and the second floating point operand based on the format of the first floating point operand and the format of the second floating point operand. The result can condition the outcome of a floating point instruction.

Abstract: A floating point unit (FPU) for processing denormal numbers in floating point notation, a method of processing such numbers in an FPU and a computer system employing the FPU or the method. In one embodiment, the FPU includes: (1) a load unit that receives a denormal number having an exponent portion of a standard length from a source without the FPU and transforms the denormal number into a normalized number having an exponent portion of an expanded length greater than the standard length, (2) a floating point execution core, coupled to the load unit, that processes the normalized number at least once to yield a processed normalized number, the expanded length of the exponent portion allowing the processed normalized number to remain normal during processing thereof and (3) a store unit, coupled to the floating point execution core, that receives the processed normalized number and transforms the processed normalized number back into a denormal number having an exponent portion of the standard length.

Abstract: One embodiment of the present invention provides a system that solves a global optimization problem specified by a function ƒ and a set of equality constraints q1(x)=0 (i=1, . . . , r), wherein ƒ is a scalar function of a vector x=(x1, x2, x3, . . . xn). During operation, the system receives a representation of the function ƒ and the set of equality constraints and stores the representation in a memory within a computer system. Next, the system and performs an interval global optimization process to compute guaranteed bounds on a globally minimum value of the function ƒ(x) subject to the set of equality constraints. Performing this interval global optimization process involves, applying term consistency to the set of equality constraints over a subbox X, and excluding portions of the subbox X that violate the set of equality constraints.

Abstract: A method and system perform a rounding step of a floating point computation on at least one floating point operand to preserve an inexact status. Inexact status information generated from the rounding step may be encoded within the result, instead of requiring a separate floating point status register for the inexact status information. In one embodiment, inexact status information is preserved by determining whether the at least one operand is inexact. Further, an intermediate result of the floating point computation is analyzed to determine whether it is inexact. Finally, the intermediate result is rounded based on whether the at least one operand is inexact and whether the intermediate result is inexact to preserve an inexact status of the at least one operand and the intermediate result.

Abstract: Embodiments consistent with the principles of the present invention provide improved results, compared to IEEE Std. 754, for floating point operations used in interval arithmetic calculations. One embodiment consistent with the principles of the present invention provides a method of enhancing support of an interval computation when performing a floating point arithmetic operation, comprising the steps, performed by a processor, of receiving a first floating point operand, receiving a second floating point operand, executing the floating point arithmetic operation on the first floating point operand and the second floating point operand, determining whether a NaN substitution is necessary, producing a floating point result if the NaN substitution is determined to be unnecessary, and substituting an alternative value as the floating point result if the NaN substitution is determined to be necessary.

Abstract: The present invention provides for saving power in a floating point unit. Bypass logic is coupled to the input of the aligner and the multiplier. An aligner bypass is coupled to the output of the aligner and an output of the bypass logic. A multiplier bypass is coupled to the output of the multiplier and an output of the bypass logic. The aligner bypass and the multiplier bypass transmit the output of the aligner and multiplier, or the bypass logic, as a function of an aligner bypass signal and a multiplier bypass signal, respectively. An adder is coupled to the output of the aligner bypass and the multiplier bypass. Clock disable logic is used to selectively enable and disable at least portions of the aligner, multiplier and bypass logic. This is done based on the operation and on the value of the operands.

Abstract: A processor having a floating point execution unit with improved parallelism in the adder (add/subtract) unit is disclosed. A preferred aspect of the invention is a new use of the compare logic in the floating point execution unit, coupled with an end-around-carry bit value calculator, to allow the correct rounding choice of the operands to be made before the mantissa portions of the operands are subtracted (added) rather than after.

Abstract: According to the invention, optimization of an application by elimination of redundant operand conversions is disclosed. According to one embodiment, the optimization comprises receiving an application that includes one or more operations, with one or more operands of the operations being converted from a first format to a second format before performing an operation; determining the origin of the one or more operands that are converted from the first format to the second format; and if the origin of any of the one or more operands that are converted from the first format to a second format is a conversion from the second format to the first format, then eliminating the redundant conversion from the second format to the first format and from the first format to the second format.

Abstract: A floating point operand testing circuit includes an analysis circuit and a result generator circuit coupled to the analysis circuit. The analysis circuit determines the status of a floating point operand based upon data within the operand. An operand buffer may supply the operand to the analysis circuit. The result generator circuit is responsive to at least one control signal and asserts a result signal if the floating point analysis circuit matches the floating point status to a predetermined format specified by the control signal. The result signal can condition the outcome of a floating point instruction. The result generator may also respond to multiple control signals asserted when testing a single operand for different formats, such as not-a-number (NaN), infinity, normalized, denormalized, invalid operation, overflow, underflow, division by zero, exact, and inexact.

Abstract: Floating-point units (FPUs) and processors having a “flush-to-nearest” operating mode that provides improved accuracy over a conventional “flush-to-zero” mode. The FPU or processor includes an operand processing section and an operand flush section. For each floating-point operation, the operand processing section receives and processes one or more input operands to provide a preliminary result. The operand flush section determines whether the preliminary result falls within one of a number of ranges of values and sets the preliminary result to one of a number of set values if the preliminary result falls within one of the ranges. In a specific implementation, a first range of values is defined to include values greater than zero and less than half of a minimum normalized number (i.e., 0<|y|<+amin/2), a second range of values is defined to include values equal to or greater than +amin/2 and less than +an, (i.e.

Abstract: An extended exponent floating point unit performs an extended exponent floating point operation on a plurality of operands to produce a product of the plurality of operands. The extended exponent floating point unit groups the plurality of operands into at least one group, determines a plurality of scale factors for the plurality of operands, respectively, and provides a running sum of the plurality of scale factors. The extended exponent floating point unit further scales the plurality of operands to obtain a plurality of scaled operands, multiplies the plurality of scaled operands to obtain a group product, and scales the group product to obtain a scaled group product. The scaled group product is adjusted based on the running sum. The plurality of operands are grouped such that when all the plurality of scaled operands in the at least one group are multiplied an overflow or underflow will not occur.

Abstract: A floating point unit capable of converting a 64-bit integer number to a floating point format is provided. The floating point unit includes an 11-bit zero/one complement detect circuitry in an exponent datapath of the floating point unit, where the 11-bit zero/one complement detect circuitry is used to determine a shift count for a right shifter in a large exponent difference mantissa datapath of the floating point unit. The 11-bit zero/one complement detect circuitry determines shift counts based on particular bit groupings of the 64-bit operand.

Abstract: A method and system determine a high part of a floating point operand. Exponent field bits and fraction field bits of a result are set to a zero if the determined format is an infinity format or an overflow format. The exponent field bits and the fraction field bits of the result are set to corresponding exponent field bits and corresponding fraction field bits of the floating point operand if the determined format is a not-a-number (NaN) format. At least one of the fraction field bits of the result is adaptively cleared if the determined format is a denormalized format or a delimited format.

Abstract: A self-timed transmission system and method are disclosed. An encoder encodes first and second data operands that are each defined on separate respective first and second sets of logic paths onto the same third set of logic paths by changing the encoding scheme. The first and second data operands are mathematically related, making this re-encoding process possible. A device, for example, a shifter, bus network, multiplexer, or buffer, processes the first and second data separately, successively in time, and in a self-timed manner, and communicates the processed first and second data onto a fourth set of logic paths. A decoder receives the processed first and second data in succession from the device on the fourth set of logic paths. The decoder decodes the first and second data onto separate respective fifth and sixth sets of logic paths, which have an encoding that corresponds to the original first and second sets of logic paths.

Abstract: Methods and systems are provided for fast computation of reciprocal square root for floating-point numbers. A piece-wise linear approximation of the result mantissa is computed in two cycles and used as the input to an iteration sequence that converges cubically. Three iterations produce a result with accuracy sufficient for computer graphic applications. The initial estimate and input operand are scaled to minimize final adjustments to the result mantissa and final exponent adjustments required by the algorithm are performed concurrently with any adjustment required by rounding. A pipelined implementation of the algorithm produces a result with a latency of 24 and a repeat rate of 21 clock cycles.

Abstract: The present invention provides a vector floating point unit (FPU) comprising a product-terms bus, a summation bus, a plurality of FIFO (first in first out) registers, a crossbar operand multiplexor coupled, a floating point multiplier, and a floating point adder. The floating point multiplier and the floating point adder are disposed between the crossbar operand multiplexor and the product-terms and summation buses, and are in parallel to each other. The invention also provides the configuration register and the command register in order to provide flexible architecture and the capability to fine-tune the performance to a particular application. The invention performs the multiplication operation and the addition operation in a pipelined fashion. Once the pipeline is filled, the invention outputs one multiplication output and one addition output at each clock cycle.

Abstract: A math coprocessor 1300 includes a multiply-accumulate unit 1600. Multiplier-accumulate unit 1600 includes a multiplier array 1603 for selectively multiplying first and second operands, the first and second operands having a data type selected from the group including floating point and integer data types. An adder 1604 selectively performs addition and subtraction operations on third and fourth operands, the third and fourth operands selected by multiplexer circuitry from the contents of a set of associated source registers, data output from multiplier array 1603 and data output from adder 1604.

Abstract: An engine control ECU includes a microcomputer, which includes CPU, RAM, ROM, FPU and I/O. The FPU performs floating-point calculations and the CPU carries out operations other than the floating-point calculations. The CPU checks whether non-numeric exists, and performs backup processing when the non-numeric is found. In the backup processing, the RAM data is initialized by writing default values harmless to control as the RAM data. In addition to or alternative to the initialization, the CPU disables a floating-point calculation of the FPU. Without using the FPU, the CPU performs engine control operations by using integer data instead of floating-point data.

Abstract: A circuit (10) for multiplying two floating point operands (A and C) while adding or subtracting a third floating point operand (B) removes latency associated with normalization and rounding from a critical speed path for dependent calculations. An intermediate representation of a product and a third operand are selectively shifted to facilitate use of prior unnormalized dependent resultants. Logic circuitry (24, 42) implements a truth table for determining when and how much shifting should be made to intermediate values based upon a resultant of a previous calculation, upon exponents of current operands and an exponent of a previous resultant operand. Normalization and rounding may be subsequently implemented, but at a time when a new cycle operation is not dependent on such operations even if data dependencies exist.

Abstract: An exponent part extraction section extracts a bit series from the exponent part of an inputted floating point data. A mantissa part extraction section extracts the uppermost K bits from the mantissa part of the floating point data. A first conversion section inputs the output e from the exponent part extraction section and outputs the value of a function X(e) thereof. A second conversion section inputs the output f from the mantissa part extraction section and outputs the value of a function Y(f) thereof. A multiplier section multiplies together these values. By setting suitable tables in advance in the first and the second conversion sections, the calculation of the v^p for an item v of floating point data can be performed.