Abstract: A dataflow graph for an application has operation units that are configured to be producers and consumers of tensors. A write access pattern of a particular producer specifies an order in which the particular producer generates elements of a tensor, and a read access pattern of a corresponding consumer specifies an order in which the corresponding consumer processes the elements of the tensor. The technology disclosed detects conflicts between the producers and the corresponding consumers that have mismatches between the write access patterns and the read access patterns. A conflict occurs when the order in which the particular producer generates the elements of the tensor is different from the order in which the corresponding consumer processes the elements of the tensor. The technology disclosed resolves the conflicts by inserting buffers between the producers and the corresponding consumers.

Abstract: A server system comprising storage devices, processing devices and a storage fabric all operating according to a storage fabric protocol. The storage fabric comprises a plurality of individual switches having a modular design from which an overall switch is built, and the individual switches have individual respective configuration settings which determine which processing devices are allocated to use which of the storage devices. The system comprises an API enabling a software control function to configure the overall switch. The API is operable to receive from the control function an overall mapping of the storage devices to the processing devices instead of requiring the individual configuration settings of each of the individual switches to be specified by the control function, the API being configured to convert the overall mapping into the individual configuration settings of the individual switches to produce the overall mapping.

Abstract: A system includes logic stored in the memory and executable by the processor to cause the processor to obtain the set of primary data objects and the set of residual data objects, each residual data object of the set of residual data objects being associated with, and representative of rounding that led to, a respective primary data object of the set of primary data objects, to evaluate, for each residual data object of the set of residual data objects, whether removal of the residual data object breaches a data integrity rule, to cause the processor to, for each residual data object of the set of residual data objects for which the removal breaches the data integrity rule, implement an optimization to attempt to identify at least one adjustment to the set of primary data objects, the set of residual data objects, or both the set of primary data objects and the set of residual data objects, that allows the removal to proceed without breaching the data integrity rule, to remove, from the set of residual data o

Abstract: A server system includes a primary server, at least one synchronous backup server, and at least one asynchronous backup server. The primary server includes a first processor. The at least one synchronous backup server, each includes a second processor configured to back up data of the primary server in a synchronous manner. The at least one asynchronous backup server, each includes a third processor configured to back up data of the primary server in an asynchronous manner. The first processor is configured to control each of one or more of the at least one asynchronous backup server to operate as a synchronous backup server when a number of the at least one synchronous backup server decreases due to a failure in at least one server included in the server system.

Abstract: According to some example embodiments of the inventive concepts, there is provided a method of operating a stacked memory device including a plurality of memory dies stacked in a vertical direction, the method including receiving a command and an address from a memory controller, determining a stack ID indicating a subset of the plurality of memory dies by decoding the address, and accessing at least two memory dies among the subset of memory dies corresponding to the stack ID such that the at least two memory dies are non-adjacent.

Abstract: According to one embodiment, a memory module includes: a memory die including a dynamic random access memory (DRAM) banks, each including: an array of DRAM cells arranged in pages; a row buffer to store values of one of the pages; an input/output (IO) module; and an in-memory compute (IMC) module including: an arithmetic logic unit (ALU) to receive operands from the row buffer or the IO module and to compute an output based on the operands and one of a plurality of ALU operations; and a result register to store the output of the ALU; and a controller to: receive, from a host processor, operands and an instruction; determine, based on the instruction, a data layout; supply the operands to the DRAM banks in accordance with the data layout; and control an IMC module to perform one of the ALU operations on the operands in accordance with the instruction.

Abstract: A controller configured to control memory chips in communication with the controller is provided. The controller comprises: a host interface configured to receive a request from a host; an address mapper configured to, upon receipt of both a turbo write request for writing data to one or more high-speed storage blocks at a high speed to and a normal write request for writing data to one or more storage blocks at a lower speed, allocate a first plane including a memory block configured to perform write operations in a single level cell mode at the high speed to a first plane group in order to respond to the turbo write request, and allocate a second plane to a second plane group at the slower speed in order to respond to the normal write request; and a memory interface configured to control the memory chips.

Abstract: Host data stored in one or more source physical extents of non-volatile data storage is identified as valid and determined to be infrequently written by host I/O requests, and is therefore compressed to generate a highly compressed version of the valid host data. The highly compressed version is then stored into at least one target physical extent. The valid host data may be initially compressed before it is stored in the source physical extent(s), and may be re-compressed to generate the highly compressed version. If the valid host data is also infrequently read, it may be recompressed using larger blocks of host data than were used to perform the initial compression. The performance tier of the target physical extent may be different from (e.g. lower than) the performance tier of the source physical extent. The technology may be embodied in a background process such as a garbage collector.

Abstract: Described herein is a system and method of journaling of a streaming anchor resource. An input node can store a value of a property associated with the streaming data in a persistent indexed data structure. The input node can generate an anchor that describes a particular point in time in a data stream. The anchor can include an index into the persistent indexed data structure of the stored value of the property associated with the streaming data. The generated anchor and streaming data can be provided to the downstream node. During recovery of a downstream node, the input node can utilize a received anchor to retrieve a value of a property associated with the streaming data from the persistent indexed data structure, and, provide a batch of data based upon the received anchor and the retrieved property value.

Abstract: A buffer circuit includes a primary interface, a secondary interface, and an encoder/decoder circuit. The primary interface is configured to communicate on an n-bit channel, wherein n parallel bits on the n-bit channel are coded using data bit inversion (DBI). The secondary interface is configured to communicate with a plurality of integrated circuit devices on a plurality of m-bit channels, each m-bit channel transmitting m parallel bits without using DBI. And the encoder/decoder circuit is configured to translate data words between the n-bit channel of the primary interface and the plurality of m-bit channels of the secondary interface.

Abstract: Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller is configured to transition between read turns and writes turn according to a turn schedule. In some embodiments, the memory controller also receives reports from circuitry requesting memory transactions and determines a current latency tolerance value based on the reports. In some embodiments, the memory controller is configured to switch from a write turn to a read turn prior to a scheduled switch based on the current latency tolerance meeting a threshold value.

Abstract: Resolving segmented constant pools in a virtual machine managed runtime. An embodiment includes allocating, using one or more processors of a computing device, for each specialization created in a class of specializations, a constant pool (CP) cache, assigning an owner to each segment of constant pools, maintaining, in a memory of the computing device, a list of specializations in the class, and copying, upon determining that a CP segment entry visible to the specialization is resolved in the owner, the entry to a specializations cache of the memory. An embodiment includes assigning a new specialized CP segment as an owner of that CP segment and adding a new entry associated with the new specialization to a template class owners table, retrieving, based on looking for entry at runtime, a slot pointed to in the owners table and resolving the CP entry in the constant pool cache of the owner.

Abstract: A system and method for efficiently transferring address mappings and data access permissions corresponding to the address mappings. A computing system includes at least one processor and memory for storing a page table. In response to receiving a memory access operation comprising a first address, the address translation unit is configured to identify a data access permission based on a permission index corresponding to the first address, and access data stored in a memory location of the memory identified by a second address in a manner defined by the retrieved data access permission. The address translation unit is configured to access a table to identify the data access permission, and is configured to determine the permission index and the second address based on the first address. A single permission index may correspond to different permissions for different entities within the system.

Abstract: Methods, systems, and devices for memory with a virtual page size are described. Memory cells may be accessed in portions or page sizes that are tailored to a particular use or application. A variable page size may be defined that represents a subset or superset of memory cells in a nominal page size for the array. For example, memory cells associated with a page size of a memory array may be accessed with commands to a memory array. Each command may contain a particular addressing scheme based on the page size of the memory array and may activate one or more sets of memory cells within the array. The addressing scheme may be modified based on the page size of the memory array. Upon activating a desired set of memory cells, one or more individual activated cells may be accessed.

Abstract: A read latency reduction method includes receiving a read request sent by a host, where the read request includes location indication information of requested data, obtaining, from read voltage management information based on a first physical location indicated by the location indication information, a read voltage corresponding to a first storage area in which the first physical location is located, the flash array includes a plurality of storage areas, the read voltage management information includes a correspondence between a storage area and a read voltage, and the read voltage in the read voltage management information is dynamically updated, and obtaining the requested data based on the read voltage corresponding to the first storage area, and sending the requested data to the host.

Abstract: A communication field, more particularly to a method for providing near field communication device information for a user and a system therefor, where the method includes: when a near field communication device receives a command for reading a near field communication data exchange format file, writing the near field communication device information and a preset application identifier into the near field communication data exchange format file and sending the near field communication data exchange format file to a terminal; obtaining, by the terminal, an application identifier and the near field communication device information from the near field communication data exchange format file; initiating an application corresponding to the application identifier and storing the near field communication device information to a position readable by the application. The method provides a great convenience for a user to obtain the near field communication device information.

Abstract: Methods, systems, and devices for wireless communication are described. To encode a vector of bits using a polar code, an encoder may allocate information bits of the vector to polarized bit-channels associated with a channel (e.g., a set of unpolarized bit-channels) used for a transmission. In some cases, the polarized bit-channels may be partitioned into groups associated with different values of some associated reliability metric (s). The information bits may be allocated to the polarized bit-channels based on the reliability metrics of the different polarized bit-channels and the overall capacity of a transmission. That is, the bit locations of a transmission may depend on the reliability metrics of different polarized bit-channels and the overall capacity of the transmission. To facilitate puncturing, the overall capacity of the transmission may be adjusted and the unpolarized bit-channels may be partitioned into polarized bit-channels based on the adjusted capacity.

Abstract: A storage volume functioning at least in part as cache for a tiered storage system, the storage volume having an in-memory write extent consisting of write-accessed grains retrieved from a plurality of hot extents in a first tier of the tiered storage system, where the in-memory write extent is a same size as a block erase size of a solid-state drive tier of the tiered storage system. The storage volume further having an in-memory read extent consisting of read-accessed grains retrieved from the plurality of hot extents in the first tier of the tiered storage system.

Abstract: A method includes receiving a request from a protocol publisher to install a protocol at the protocol database, the request including a global unique identifier (GUID) and a first protocol pointer. The GUID and the first protocol pointer are stored at an entry at a protocol database. A root key received from the protocol publisher is stored at the entry at the protocol database. A request including the GUID is received from a protocol consumer, and in response, the protocol consumer is provided with a random number. A reference GUID is generated based on the random number and the root key, and the reference GUID is stored at the entry of the protocol database.

Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of streams. The controller restricts the host to a maximum number of streams that can be in the open and active state at a time. Open streams can be switched to the closed state, and vice versa, upon a predetermined amount of time expiring. The maximum number of open streams is based on one or more amounts of time to: generate parity data, copy the parity data from the RAM2 to the RAM1, update the parity data, switch a stream from the open and active state to the closed state, and the amount of space in a temporary RAM1 buffer.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems in which a memory device can include a voltage regulator for adjusting a supply voltage to an output voltage and providing the output voltage to other devices external to the memory device (e.g., other memory devices in the same memory system, processors, graphics chipsets, other logic circuits, expansion cards, etc.). A memory device may comprise one or more external inputs configured to receive a supply voltage having a first voltage level; a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage having a second voltage level different from the first voltage level; one or more memories configured to receive the output voltage from the voltage regulator; and one or more external outputs configured to supply the output voltage to one or more connected devices.

Abstract: An example method of enriching a storage provider of a virtualized computing system with metadata managed by a container orchestrator executing in the virtualized computing system is described. The method includes detecting, by a metadata sync service executing as an extension of the container orchestrator, metadata that is included in a persistent volume-based (PV-based) object managed by the container orchestrator, the PV-based object referencing a persistent volume; and pushing, by the metadata sync service, the metadata to the storage provider to augment a storage volume object managed by the storage provider, the storage volume object referencing a storage volume backing the persistent volume.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for allocating cache resources according to page-level attribute values. In one implementation, the system includes one or more integrated client devices and a cache. Each client device is configured to generate at least a memory request. Each memory request has a respective physical address and a respective page descriptor of a page to which the physical address belongs. The cache is configured to cache memory requests for each of the one or more integrated client devices. The cache comprises a cache memory having multiple ways. The cache is configured to distinguish different memory requests using page-level attributes of respective page descriptors of the memory requests, and to allocate different portions of the cache memory to different respective memory requests.

Abstract: Even though storage systems are different in types, storage pools in a plurality of storage systems are integrated, and a storage volume is created in a suited storage pool corresponding to a storage requirements. In an information system where a plurality of storage systems (a disk array, an SDS system, and an HCI system) is present, when creating the storage volume using requested storage requirements as parameters, a storage management server selects a storage pool that satisfies the storage requirements based on comparison of the storage requirements and characteristic information held in first management information (a storage pool management table), the server creates the storage volume in the selected storage pool, and the server adds an entry relating to the created storage volume to second management information (a volume management table).

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for tracking memory usage. One of the methods includes implementing an instance of a memory usage tracker (MUT) in each process running in a node of a computer system. The MUT initiates a free process for a memory chunk. A current generation of the memory chunk is determined. The MUT determines whether the mapping element's generation precedes the current generation. If the mapping element's generation is old, the MUT treats the long-living rollover account as the owner of the memory chunk to be freed and if the current generation and the mapping element's generation match, then the MUT considers the owner associated with the mapping element as the owner of the chunk. The MUT then adjusts the balance of the determined memory account and/or sub-account and the balance of the mapping element by the freed memory amount.

Abstract: Compression of data is facilitated by locating matches within the data to be compressed. A first technique is used to determine whether there is at least one matching string in the data to be compressed, and a second technique, different from the first technique, is used to determine whether there is at least one matching record in the data to be compressed. Based on there being at least one matching string in the data to be compressed, at least one indication of the at least one matching string is provided to an encoder to facilitate compression of the data. Further, based on there being at least one matching record in the data to be compressed, at least one indication of the at least one matching record is provided to the encoder to facilitate compression of the data. It is transparent to the encoder whether the first technique or the second technique is used to provide one or more matches.

Abstract: Example distributed storage systems, controller nodes, and methods provide selective allocation of redundant data blocks to background operations. Background operations may be identified targeting a data unit stored in redundant data blocks in a storage pool with a plurality of storage elements. A subset of data units may be selected for the background operation and the system components including those data units may be isolated. Data requests to the isolated system components may be selectively prevented while the background operation executes on the subset of data units in the isolated system components.

Abstract: Data of a vector storage request pertaining to one or more disjoint, non-adjacent, and/or non-contiguous logical identifier ranges are stored contiguously within a log on a non-volatile storage medium. A request consolidation module modifies one or more sub-requests of the vector storage request in response to other, cached storage requests. Data of an atomic vector storage request may comprise persistent indicators, such as persistent metadata flags, to identify data pertaining to incomplete atomic storage requests. A restart recovery module identifies and excludes data of incomplete atomic operations.

Abstract: Presented herein are methods and systems for adjusting code files to apply memory protection for dynamic memory regions supporting run-time dynamic allocation of memory blocks. The code file(s), comprising a plurality of routines, are created for execution by one or more processors using the dynamic memory. Adjusting the code file(s) comprises analyzing the code file(s) to identify exploitation vulnerable routine(s) and adding a memory integrity code segment configured to detect, upon execution completion of each vulnerable routine, a write operation exceeding from a memory space of one or more of a subset of most recently allocated blocks allocated in the dynamic memory to a memory space of an adjacent block using marker(s) inserted in the dynamic memory in the boundary(s) of each of the subset's blocks. In runtime, in case the write operation is detected, the memory integrity code segment causes the processor(s) to initiate one or more predefined actions.

Abstract: A wearable device includes one or more sensors of information from a subject. The wearable device may have an electronic assembly supported by a base. The electronic assembly may include a sensor data collection system configured to control collection of sensor data related to one or more characteristics of a subject and one or more processors. the sensor data collection system may include a controller configured to control sequencing and scheduling of the sensor data collection, and a buffer configured to receive and buffer data corresponding to the sensor data collected from the one or more sensors in accordance with a signal provided by the controller. The one or more processors may be configured to receive the buffered data from the buffer in accordance with a wake signal; process the received data; and output the processed data.

Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: maintaining first management information for identifying a first management unit in the rewritable non-volatile memory module; collecting first valid data from the first management unit according to the first management information without reading first mapping information from the rewritable non-volatile memory module in a data merge operation, and the first mapping information includes logical-to-physical mapping information related to the first valid data; and storing the collected first valid data into a recycling unit.

Abstract: In accordance with one embodiment of the present disclosure, a method for determining the similarity between a first data set and a second data set is provided. The method includes performing an entropy analysis on the first and second data sets to produce a first entropy result, wherein the first data set comprises data representative of a first one or more computer files of known content and the second data set comprises data representative of a one or more computer files of unknown content; analyzing the first entropy result; and if the first entropy result is within a predetermined threshold, identifying the second data set as substantially related to the first data set.

Abstract: A barrier-free atomic transfer method of multiword data is described. In the barrier-free method, a producer processor deconstructs an original parameter set of data into a deconstructed parameter set; and performs a series of single-copy-atomic writes to a series of single-copy-atomic locations. Each single-copy-atomic location in the series of single-copy-atomic locations comprises a portion of the deconstructed parameter set and a sequence number. A consumer processor can read the series of single-copy-atomic locations; verifies that the sequence number for each single-copy-atomic location in the series of single-copy-atomic locations is consistent (e.g., are all the same sequence number); and reconstructs the portions of deconstructed parameter set into the original parameter set.

Abstract: The invention relates to a tiered storage system comprising tiers of data storage. The tiered storage system further comprises a processor; and a memory coupled to the processor. The memory comprises instructions which, when executed by the processor, cause the processor to: receive usage data descriptive of usage of memory extents stored by the tiered storage system; identify periodic usage patterns of the memory extents at least partially by calculating a correlation coefficient between the usage data and a predetermined list of conditions; determine a projected data usage for each of the memory extents using the periodic usage patterns, wherein the projected data usage is temporally dependent; sort the memory extents into usage bins according to the projected data usage; and control the tiers of data storage to migrate the at memory extents between the tiers of data storage using temporal changes of the sorting into the usage bins.

Abstract: Provided is a distributed storage system which can reduce a load on a network between storage apparatuses when an access request is received and improve responsiveness. In the distributed storage system, the storage device includes a data area and a cache area; a node becomes an owner node when receiving a transfer of charge of an LU from another node in a non-storage state where LU data is not stored in a data area; the processor of the owner node receives a read request for an LU that is in charge, obtains data of a target area based on data of the storage device of another node when the data of the target area is not stored in the data area or the cache area of the owner node, and transmits the data to a request source and stores it in a cache area.

Abstract: A method of writing data in a storage device including sequentially receiving a plurality of data write commands, sequentially assigning a plurality of write data corresponding to the plurality of data write commands to a plurality of buffer groups by determining continuity of logical addresses of the plurality of write data such that each of the plurality of buffer groups temporarily stores some of the plurality of write data included in a respective single stream and having consecutive logical addresses, assigning a plurality of serial numbers to the plurality of write data, respectively, based on an order in which the plurality of write data are assigned to the plurality of buffer groups, programming the plurality of write data temporarily stored in the plurality of buffer groups into a plurality of memory blocks, and updating a logical-to-physical mapping table based on the plurality of serial numbers may be provided.

Abstract: In one approach, a computer storage device has one or more pivot tables and corresponding bit maps stored in volatile memory. The storage device has non-volatile storage media that stores data for a host device. The pivot tables and bit maps are used to determine physical addresses of the non-volatile storage media for logical addresses received in commands from the host device that are determined to be within a sequential address range (e.g., LBAs that are part of a prior sequential write operation by the host device). When a command is received by the storage device that includes a logical address within the sequential address range, then one of the pivot tables and its corresponding bit map are used to determine the physical address of the non-volatile storage media that corresponds to the logical address.

Abstract: Optimizing database table scans in presence of SMDO records is provided. An SMDO record corresponding to a most recent span of rows for a column associated with a query predicate is read. It is determined whether a condition for excluding a span of rows is true for the SMDO record based on a type of the query predicate. In response to determining that a condition for excluding a span of rows is not true for the SMDO record, the most recent span of rows is added to a list of spans of rows to scan. It is determined whether a condition for excluding all preceding spans of rows is true for the SMDO record based on the type of the query predicate. In response to determining that a condition for excluding all preceding spans of rows is true for the SMDO record, reading the set of SMDO records is stopped.

Abstract: An aspect includes reading a first page and a corresponding second page from a storage device. The first page specifies a metadata page stored in persistent storage and having logical addresses of metadata, and the second page associates logical block addresses (LBAs) with corresponding physical locations for the metadata. An aspect also includes reading data for a RAID stripe according to an associated physical offset in the second page, accessing a stripe counter from the second page, and comparing the stripe counter from the second page to a stripe counter held in memory. Upon determining the stripe counter from the second page is not the same, a third page is loaded, and a physical location of the data is read from the third page that provides a hash value of the data and corresponding physical location. The physical location of the data is accessed, and the second page is updated.

Abstract: A metadata track stores metadata corresponding to both a first customer data track and a second customer data track. In response to receiving a first request to perform a write on the first customer data track from a two track write process, exclusive access to the first customer data track is provided to the first request, and shared access to the metadata track is provided to the first request. In response to receiving a second request to perform a write on the second customer data track from the two track write process, exclusive access to the second customer data track is provided to the second request, and shared access to the metadata track is provided to the second request prior to providing exclusive access to the metadata track to at least one process that is waiting for exclusive access to the metadata track.

Abstract: A multi-processor system includes multiple processors arranged in multiple clusters. Different clusters have different power and performance characteristics. The system includes a task scheduler to schedule tasks to the processors. The task scheduler, in response to detection of a scheduling event trigger, is operative to identify a scheduling objective between a first objective of energy optimization and a second objective of load balance. The scheduling objective is identified based on at least respective operating frequencies and loading of all processors in a highest-capacity cluster of the multiple clusters. According to the identified scheduling objective, the task scheduler schedules a given task to a processor selected among the processors in the multiple clusters.

Abstract: A method, computer program product, and computer system for identifying, by a computing device, a current persisted value of a reclamation pool. A default value of the reclamation pool may be identified. The current persisted value may be compared with the default value to determine which is a higher value. The current persisted value may be selected as a minimum memory operating state of the reclamation pool when the current persisted value is higher than the default value. The default value may be selected as the minimum memory operating state of the reclamation pool when the default value is higher than the current persisted value plus a multiplier defining a threshold size.

Abstract: The present disclosure includes an interface for memory having a cache and multiple independent arrays. An embodiment includes a memory device having a cache and a plurality independent memory arrays, a controller, and an interface configured to communicate a plurality of commands from the controller to the memory device, wherein the interface includes a pin configured to activate upon a first one of the plurality of commands being received by the memory device and deactivate once all of the plurality of commands have been executed by the memory device.

Abstract: The time required for recovery in a distributed computing system can be reduced. At least one node (for example a server) or a different computer (for example a management server) are provided in the distributed computing system which includes a plurality of nodes existing at a plurality of sites. One or more sites at which one or more nodes that hold one or more datasets identical to one or more datasets held by a node to be recovered are identified. For the recovery, it is determined, on the basis of the one or more identified sites, a restore destination site that is a site of a node to which the one or more identical datasets are to be restored from among the plurality of sites.

Abstract: Apparatuses, systems, kits, methods and storage medium associated with using different electrical energy source types with an electric vehicle are disclosed herein.

Abstract: Provided are a computer program product, system, and method for determining an optimal storage environment for data sets and for migrating data sets. Metadata for each application indicates storage pools used by the application to store data sets, wherein each storage pool is configured in one of a plurality of storage environments using different organization schemes to store data sets. The metadata for at least one application indicates storage pools to store the data sets for the application that are allocated from different storage environments. The metadata for an application is processed to determine a data set for the application stored in a first storage pool implemented in a first storage environment that should be stored in a second storage environment. The determined data set from the first storage pool to a second storage pool implemented in the second storage environment.

Abstract: A gateway for use in a computing system to interface a host with the subsystem for acting as a work accelerator to the host, the gateway having an streaming engine for controlling the streaming of batches of data into and out of the gateway in response to pre-compiled data exchange synchronisation points attained by the subsystem, wherein the streaming of batches of data is selectively via at least one of an accelerator interface, a data connection interface, a gateway interface and an memory interface, wherein the streaming engine is configured to perform data preparation processing of the batches of data streamed into the gateway prior to said batches of data being streamed out of the gateway, wherein the data preparation processing comprises at least one of: data augmentation; decompression; and decryption.

Abstract: Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first semiconductor chip and a second semiconductor chips that are stacked with each other via through substrate vias (TSVs) provided in one of the first semiconductor chip and the second semiconductor chip. The first semiconductor chip and the second semiconductor chips communicate with each other by use of data bus inversion data that have been encoded using a DBI algorithm.

Abstract: The present disclosure is directed to systems and methods for mitigating or eliminating the effectiveness of a side-channel based attack, such as one or more classes of an attack commonly known as Spectre. Novel instruction prefixes, and in certain embodiments one or more corresponding instruction prefix parameters, may be provided to enforce a serialized order of execution for particular instructions without serializing an entire instruction flow, thereby improving performance and mitigation reliability over existing solutions. In addition, improved mitigation of such attacks is provided by randomizing both the execution branch history as well as the source address of each vulnerable indirect branch, thereby eliminating the conditions required for such attacks.

Abstract: The present application provides methods and systems for memory management of a kernel space and a user space. An exemplary system for memory management of the kernel space and the user space may include a first storing unit configured to store a first root page table index corresponding to the kernel space. The system may also include a second storing unit configured to store a second root page table index corresponding to the user space. The system may further include a control unit communicatively coupled to the first and second registers and configured to: translate a first virtual address to a first physical address in accordance with the first root page table index for an operating system kernel, and translate a second virtual address to a second physical address in accordance with the second root page table index for a user process.