Abstract: A high-availability network device cluster role synchronization technique for devices configured with multiple network controllers is disclosed. An HA node may contain information regarding a role within a cluster for that HA node. This information should properly be maintained or erased based on a type of failover for an HA device. For example, if there is a loss of the active controller that causes only a controller failover, changes to the role of the HA node may not be necessary. Thus, an election process within a cluster may be avoided. However, if a failover of an entire HA node occurs (or restart of an HA node), role information prior to the restart may not be applicable and an election process may need to be initiated such that the cluster may continue to function. Different types of roles may exist for nodes within a cluster.

Abstract: Systems, methods, and other embodiments associated with transmission of messages over a blockchain network are described. In one embodiment, a method includes extracting message data from a source database. The message data is evaluated to identify a message type of the message. A message template is selected from a set of message templates based upon the message template corresponding to the message type of the message. The message data is decomposed into a set of parameter values that are populated into the message template to create a transaction message in the blockchain message format. The transaction message is routed to a blockchain node for routing over the blockchain network.

Abstract: Technologies are described herein for or reducing the size of the forward mapping table in an SSD or other storage device using hashing. A physical address of a storage location within a storage media is determined for the storage of data associated with a logical block address. The data is written to the storage location and a hash value is computed from a representation of the physical address using a hash function, where the size of the hash value is smaller than the representation of the physical address and the hash value points to a plurality of separate storage locations in the storage media. The hash value is stored in the forward mapping table associated with logical block address as opposed to the representation of the physical address.

Abstract: A memory system is provided. The memory system includes a first memory device having a first latency corresponding to a first command and a second memory device having a second latency corresponding to a second command. The second latency differs from the first latency by a latency difference. The memory system further includes a host operably coupled to the first and second memory devices. The host is configured to send the first command to the first memory device at a first time, and to send the second command to the second memory device at a second time. The first time and the second time are separated by a delay corresponding to the latency difference.

Abstract: Data is migrated from a source storage device to a destination storage device using tape media. Both the source storage device and the destination storage device utilize disk drives to store data. A portion of data is detected migrating to the tape media. Metadata of the portion of data is changed to identify the portion of data as residing on the tape media. A prefetch command for the portion of data is detected. It is determined that the portion of data is stored on the tape media. In response to determining that the portion of data is stored on the tape media, the prefetch command is executing without recalling the portion of data to the disk drives. Instead, the portion of data is read directly from the tape media.

Abstract: There are provided a memory system and an operating method thereof. The memory system includes: a host for receiving and storing a host map segment; a memory device including a system block for storing map data, the memory device performing overall operations in response to an internal command; and a controller for generating the internal command for controlling the memory device in response to a host command received from the host. The controller receives the map data from the memory device and then stores the received map data, and generates the host map segment, using the map data, and then transmits the generated host map segment. A number of generatable host map segments is adjusted based on a work load calculated in a setting period.

Abstract: A Data Storage Device (DSD) includes at least one disk for storing data in a plurality of storage areas including at least a first area type for using a first data access methodology and a second area type for using a second data access methodology. It is determined whether to perform a command in a storage area of the first or second area type. If the command is to be performed in the first area type, the command is prioritized over at least one other command for the second area type. In another aspect, a value is determined representing a number of data access operations within a predetermined time period for a data storage capacity of the DSD. Storage areas of the DSD are configured as one of at least the first area type and the second area type based at least in part on the determined value.

Abstract: A method, computer-readable medium, and device for processing a stream of records are disclosed. A method may receive a registration request from a data source to join in providing a plurality of records to the stream, synchronize a timing system with the data source, receive an initial timestamp from the data source, and post the initial timestamp to a plurality of operators or a plurality of subscribers before the data source is allowed to send records into the stream.

Abstract: Provided are a computer product, method, and system to virtualize target system storage resources as virtual target storage resources. Target storage resources available at a target system are discovered over a network. A configuration is determined of virtual target storage resources mapping to the target storage resources for a host node. The configuration is registered with a virtual target. The configuration maps the virtual target storage resources to the target storage resources at the target system and an access control list of the host node allowed to access the virtual target storage resources. A query is received from the host node for the target storage resources the host node is permitted to access according to the access control list. Host discovery information is returned to the requesting host node indicating the virtual target storage resources the requesting host node is provisioned to access from the virtual target.

Abstract: A system, computer program product, and computer-implemented method for smart contract dependent resource transfer are disclosed. The system is configured to establish a smart contract between a first storage location and a second storage location, the smart contract being configured for conditionally transferring resources between the first storage location and the second storage location; monitor the first storage location to determine that a first transfer condition has been met; based on determining that the first transfer condition has been met, automatically transfer a number of resources from the second storage location to the first storage location; determine that a second transfer condition has been met; and automatically transfer the number of resources from the first storage location to the second storage location based on determining that the second transfer condition has been met.

Abstract: The operational performance and the I/O performance of Snapshots in a storage system are balanced. In a storage system, meta information of data appended to a log structured area is composed of meta information of a first tier and meta information of a second tier which correlate location information of data in a logical volume and location information of data in the log structured area. When creating a snapshot of the logical volume, a data management unit creates, in the same meta information area as a replication source, a replication of the meta information of the first tier stored in a plurality of meta information areas assigned to a plurality of controllers. A data control unit accesses the data of the log structured area from the logical volume, and accesses the data of the log structured area from the snapshot.

Abstract: A method and a device for evaluating the contents of a map, the map containing at least one first driving environment feature, including a step of recording at least one second driving environment feature by at least one sensor of at least one vehicle, a step of comparing the at least one first driving environment feature contained in the map to the at least one second, recorded driving environment feature, and a step of evaluating the contents of the map as a function of the performed comparison.

Abstract: A memory system includes a semiconductor storage device and a memory controller. The memory controller includes a command buffer and a descriptor buffer. The memory controller stores a first command received from outside in the command buffer, fetches a first descriptor from the host device, based on the stored first command, stores the fetched first descriptor in the descriptor buffer, stores a second command received from the outside in the command buffer, discards an unused part of the first descriptor from the descriptor buffer, fetches a second descriptor from the host device, based on the stored second command, and stores the fetched second descriptor at an address where the discarded part of the first descriptor was stored.

Abstract: A semiconductor apparatus may be provided. The semiconductor apparatus may include a fine training circuit configured to generate a fine result signal based on a clock signal, a data strobe signal, and a command. The semiconductor apparatus may include a coarse training circuit configured to generate a coarse result signal based on the clock signal, the data strobe signal, and the command and to set an offset of a write enable signal based on an offset control signal.

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive data for a current write operation to a memory, determine a number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory and in response to a determination that the number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory exceeds a threshold, to toggle a plurality of bits in the data for the current write operation to create an encoded data set and set an indicator bit to a value which indicates that the plurality of bits have been toggled. Other embodiments are also disclosed and claimed.

Abstract: Systems and methods for memory page hints that account for multiple page sizes. An example method may comprise: determining, by a processing device executing a guest operating system, that a memory page size of the guest operating system is different from a memory page size of a hypervisor; adding, by the guest operating system, a guest memory page released by the guest operating system to a set of guest memory pages; determining in view of the memory page size of the hypervisor that the set of guest memory pages fills a hypervisor memory page; and providing an indication to the hypervisor that the hypervisor memory page is available for reuse.

Abstract: A memory system which is accessible to a host device includes a volatile memory, a nonvolatile memory, and a memory controller that controls the volatile memory and the nonvolatile memory. The memory controller stores first data, which is stored in the volatile memory, in the nonvolatile memory, each time the memory controller stores second data, which is stored in the volatile memory, in the nonvolatile memory. The first data indicates a logical address and a deletion range designated by a deletion request received from the host device, and the second data is designated by a write request received from the host device.

Abstract: A storage device comprising: a nonvolatile memory device including a plurality of memory blocks; and a device controller configured to control the nonvolatile memory device to determine a memory block to perform a refresh operation and to control the memory block to perform the refresh operation to recover data of the memory block.

Abstract: There are provided a memory system and an operating method thereof. A memory system includes: a nonvolatile memory device that operates in response to a plurality of internal commands received thereby; and a memory controller for generating and queuing the plurality of internal commands in response to a plurality of commands received from a host, and generating and storing a processing completion bitmap index corresponding to the plurality of queued internal commands.

Abstract: A number K of N sub-channels that are defined by a code and that have associated reliabilities for input bits at N input bit positions, are to be selected to carry bits that are to be encoded. A localization area that includes multiple sub-channels and is located below fewer than K of the N sub-channels in a partial order of the N sub-channels is determined based on one or more coding parameters. The fewer than K sub-channels of the N sub-channels above the localization area in the partial order are selected, and a number of sub-channels from those in the localization area are also selected. The selected fewer than K sub-channels and the number of sub-channels selected from those in the localization area together include K sub-channels to carry the bits that are to be encoded.

Abstract: In an embodiment, a system for handling a device in latency state in a redundant storage system includes a processor configured to process a write request to a plurality of devices associated with a redundant storage system. The processor is further configured to receive a set of indications of write successes from a set of devices included in the plurality of devices other than a first device, and send an indication of a completed write to a requestor associated with the write request based at least in part on an indication that the first device meets a set of one or more criteria associated with a latency state. The system further includes a memory coupled to the processor and configured to store the write request.

Abstract: The techniques disclosed herein improve performance of file system logging by writing log data to persistent memory instead of staging in RAM before writing to disk. In one embodiment, while the log is being written, checksums are inserted, such that during recovery, the checksums can be used to distinguish good log pages from bad log pages. In this way, good log pages can be evaluated to determine whether to roll a portion of a file system transaction forward, backward, or do nothing, while bad log pages can be safely ignored. Additionally or alternatively, non-temporal copies are employed when writing data to persistent memory, thereby reducing an amount of time log data is exposed to be lost in a crash.

Abstract: A computational memory for a computer. The memory includes a memory bank having a selected-row buffer and being configured to store records up to a number, K. The memory also includes an accumulator connected to the memory bank, the accumulator configured to store up to K records. The memory also includes an arithmetic and logic unit (ALU) connected to the accumulator and to the selected row buffer of the memory bank, the ALU having an indirect network of 2K ports for reading and writing records in the memory bank and the accumulator, and the ALU further physically configured to operate as a sorting network. The memory also includes a controller connected to the memory bank, the ALU, and the accumulator, the controller being hardware configured to direct operation of the ALU.

Abstract: According to one embodiment, a memory system determines a write destination block and a write destination location in the write destination block to which write data is to be written, and notifies a host of an identifier of the write data, a block address of the write destination block, and an offset indicative of the write destination location. The memory system retrieves the write data from a write buffer of the host, and writes the write data to the write destination location. In a case where a read command to designate a physical address of first data is received before a write operation of the first data is finished, the memory system reads the first data from the write buffer of the host.

Abstract: A resistance switching memory-based accelerator configured to be connected to a host including a CPU and a system memory is provided. A resistance switching memory module includes a memory cell array including a plurality of resistance switching memory cells, and stores a kernel offloaded from the host. An accelerator core includes a plurality of processing elements, and the kernel is executed by a target processing element among the plurality of processing elements. An MCU manages a memory request generated in accordance with execution of the kernel by the target processing element. A memory controller is connected to the resistance switching memory module, and allows data according to the memory request to move between the resistance switching memory module and the target processing element, in accordance with the memory request transferred from the MCU. A network integrates the accelerator core, the plurality of processing elements, and the memory controller.

Abstract: A data processing system may include a host and a memory system, the memory system may include a volatile recovery selection register and a nonvolatile memory device, wherein the memory system checks, after being reset, a value of the recovery selection register and determines whether to perform a recovery operation on the nonvolatile memory device, and when a reset is requested from the host, the memory system sets the value of the recovery selection register and resets the nonvolatile memory device, and the host may read set first data from the memory system through a first booting operation that starts during a power-on operation, may request a reset to the memory system, and may read set second data form the memory system through a second booting operation that starts after the reset of the memory system.

Abstract: Implementations and methods herein provide a networked storage system including a plurality of physical storage devices configured to store data on a plurality of virtualized volumes, a key store configured to store a plurality of encryption keys, and a security manager configured to encrypt data stored on each of the plurality of virtualized volumes using a different key.

Abstract: Technology for a memory device operable to program memory cells in the memory device is described. The memory device can include a plurality of memory cells and a memory controller. The memory controller can receive a page of data. The memory controller can segment the page of data into a group of data segments. The memory controller can program the group of data segments to memory cells in the plurality of memory cells that are associated with an inhibit tile group (ITG). The group of data segments for the page of data can be programmed using all bits included in each of the memory cells associated with the ITG.

Abstract: The present disclosure provides a processor providing a memory architecture having M-number of processing elements each having at least N-number of processing units and a local memory. The processor comprises a first processing element of the M-number of processing elements comprising a first set of N-number of processing units configured to perform a computing operation, and a first local memory configured to store data utilized by the N-number of processing units. The processor further comprises a data hub configured to receive data from the M-number of processing elements and to provide shared data to each processing element of the M-number of processing elements.

Abstract: A method for testing memory cells under test of an integrated circuit includes allocating an access value to a memory access and granting an access credit. If the access value of the memory access does not exceed the access credit, the memory access is performed and the access credit is reduced by the access value. The memory access is performed to one memory cell or at bit level to a plurality of memory cells. A processor is connectable to a memory having a plurality of memory cells. The processor is configured to test memory cells of a protected memory area of the memory by performing memory accesses at bit level, control a counting register in such a way that a value stored in the counting register is modified according to a number of performed memory accesses, and test memory cells of the protected memory area of the memory only if the value stored in the counting register lies within a permissible value range.

Abstract: A technique is directed to storing data on a plurality of storage devices of a data storage array. The technique involves, on each storage device of the plurality of storage devices, providing large disk extents and small disk extents for allocation to RAID extents. The technique further involves forming, from the large disk extents, a user-data RAID extent to store user data for the data storage array. The technique further involves forming, from the small disk extents, an internal-metadata RAID extent to store internal metadata for the data storage array. In some arrangements, spare space is reserved on one or more storage devices between large and small disk extents.

Abstract: A cache system having cache sets, registers associated with the cache sets respectively, and a logic circuit coupled to a processor to control the cache sets according to the registers. When a connection to an address bus of the system receives a memory address from the processor, the logic circuit can be configured to: generate an extended tag from at least the memory address; and determine whether the generated extended tag matches with a first extended tag for a first cache set or a second extended tag for a second cache set of the system. Also, the logic circuit can also be configured to implement a command received from the processor via the first cache set in response to the generated extended tag matching with the first extended tag and via the second cache set in response to the generated extended tag matching with the second extended tag.

Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry operably coupled to the interface and to the memory. The processing circuitry is configured to execute the operational instructions to perform various operations and functions. The computing device detects at least one available memory device within a storage unit (SU). The computing device identifies storage capacities of each of the memory devices within the SU and identifies a DSN address range associated with the SU. The computing device maps the DSN address range to each of the memory devices within the SU based on the storage capacities to generate a memory mapping of the memory devices within the SU. The computing device then facilitates redistribution of some EDS from a first memory device to the at least one available memory device within the SU.

Abstract: Methods, systems, and devices related to zone swapping for wear leveling memory are described. A memory device can perform access operations by mapping respective logical zones associated with respective logical addresses (e.g., of an access command) to respective zones of the memory device. As the memory device receives access commands and accesses respective zones, some zones may undergo a disproportionate amount of access operations relative to other zones. Accordingly, the memory device may swap data stored in some disproportionately accessed zones. The memory device can update a correspondence of respective logical zones associated with the zones based on swapping the data so that later access operations access the desired data.

Abstract: One embodiment provides a method for optimizing data read-ahead for workflow and analytics applications including obtaining, by a processor, next file information from a workflow scheduler for next files for a next processing stage that are to be accessed by a process. Data for the next processing stage for at least one application and at least one system job is prefetched. The next files are prefetched as the prefetching data reaches an end of current inputs.

Abstract: An electronic device includes a controller; and a non-transitory computer-readable storage medium configured to store operation codes for causing the controller to execute processes. The non-transitory computer-readable storage medium includes a plurality of memory blocks. The processes include grouping the plurality of memory blocks into a plurality of super blocks; selecting a first super block among the plurality of super blocks depending on one or more logical addresses corresponding to write-requested data, and writing the data; and mapping the first super block to a first logical address range. The first logical address range is configured by successive addresses corresponding to a super block size, and a start address of the successive addresses is a start logical address of the one or more logical addresses.

Abstract: Technologies are described herein for reducing network traffic when replicating memory data across hosts. The memory data stored in a main memory of the host computer is replicated to a main memory of a second host computer. Memory data from the local data storage of the second host computer and other hosts computers that is a duplicate of memory data from the main memory is identified. Instead of sending the memory data from the main memory that is duplicated, the duplicated memory is copied from the local storage of the second computer or from one or more of the other computers to the main memory of the second host computer.

Abstract: A semiconductor memory device includes: an internal circuit; a write control circuit suitable for writing write data into the internal circuit based on a write strobe signal during a normal write operation, and writing test data into the internal circuit based on a read strobe signal during a test write operation; and a read control circuit suitable for generating the read strobe signal and outputting the read strobe signal together with read data read from the internal circuit during a normal read operation or a test read operation, and generating the read strobe signal and providing the write control circuit with the read strobe signal during the test write operation.

Abstract: A system includes a memory and at least one processor to continually analyze at least one of metrics, events, and conditions in a computer network, under normal operating conditions in the computer network, obtain a first level of data from at least one hardware device in the computer network, detect that one of a condition and an event has occurred in the computer network, automatically transmit an instruction to modify the first level of data obtained from the at least one hardware device to a second level of data more robust than the first level of data when one of the condition and the event has occurred, collect the second level of data from the at least one hardware device, and store the second level of data obtained from the at least one hardware device.

Abstract: A memory device include write leveling circuitry that is configured to receive a write command from the command interface. The write leveling circuitry also receives a data strobe (DQS) signal from a host device (e.g., processor) and receives a clock signal from the host device. The write leveling circuitry also compares phases of the DQS signal and the clock signal using a phase detector. The write leveling circuitry also generates an internal write signal (IWS) based upon the write command, and outputs a captured result of a write leveling operation based at least in part on the compared phases and the IWS.

Abstract: Example implementations relate to a capability enforcement processor. In an example, a capability enforcement processor may be interposed between a memory that stores data accessible via capabilities and a system processor that executes processes. The capability enforcement processor intercepts a memory request from the system processor and enforces the memory request based on capability enforcement processor capabilities maintained in per-process capability spaces of the capability enforcement processor.

Abstract: The technology disclosed herein includes capturing a media content from a media recording device, generating a hash of the media content, storing the media content in a storage device, and transmitting a media transaction to a distributed ledger, the media transaction comprising the location of the media content in the storage device and the hash of the media content.

Abstract: A method is applied to an electronic device, all storage space of the electronic device includes internal storage space and at least one external storage space, and the method includes: receiving a data write instruction, where the data write instruction carries target write data; selecting at least one of all the storage space as target storage space according to a preset rule, and performing a write operation in the target storage space; and after the write operation is completed, updating a virtual file that is obtained by summarizing and combining files of a same file type in all the storage space of the electronic device and that is stored in a virtual storage card, and updating a mapping relationship between a virtual storage path corresponding to the virtual storage card and a physical storage path corresponding to the target storage space.

Abstract: One embodiment is related to a method for automatically removing a mount point, comprising: determining whether a vMotion live migration has been completed for a virtual machine (VM) recovered through Instant Access from a backup storage system; after the vMotion live migration has been completed, determining whether a datastore corresponding to a backup image of the VM on the backup storage system is empty; in response to determining that the datastore corresponding to the backup image of the VM on the backup storage system is empty, removing automatically a mount point corresponding to the datastore; and after removing the mount point, freeing up storage space on the backup storage system corresponding to the datastore.

Abstract: The present invention provides a microcontroller, wherein the microcontroller includes a processor, a first memory and a cache controller. The first memory includes at least a working space. The cache controller is coupled to the first memory, and is arranged for managing the working space of the first memory, and dynamically loading at least one object from a second memory to the working space of the first memory in an object-oriented manner.

Abstract: Methods of operating a memory system comprising a plurality of memory devices include loading respective sets of termination information to a subset of memory devices of the plurality of memory devices, and, for each memory device of the subset of memory devices, storing its respective set of termination information to an array of non-volatile memory cells of that memory device. For each memory device of the subset of memory devices, its respective set of termination information comprises address information of the memory system and one or more termination values associated with that address information.

Abstract: A system and method of exitless extended page table switching includes a nested hypervisor writing pointer addresses to an extended page table list, where each pointer address is associated with an extended page table. The host hypervisor verifies that each pointer address corresponds to a guest physical address for one of the extended page tables. The host hypervisor then creates shadow extended page tables, each of which includes a shadow pointer address corresponding to a host physical address, writes, in a local page table list, each shadow pointer address and an index of each shadow extended page table, and loads the local page table list. The nested guest requests to switch between two extended page tables. The nested guest then identifies a matching entry for an extended page table in the local page table list and switches to the extended page table without triggering an exit.

Abstract: A method for scheduling tasks to a cyclic schedule, comprising maintaining a request queue, a count, the count being initialized to a given limit, and an index of a current time slot within the schedule. Periodically, if the request queue contains a reference to an urgent task among the tasks, that reference is removed from the request queue and the urgent task is dispatched and if the request queue is empty, the index is advanced to the next time slot within the schedule. If the next time slot is statically assigned to a task among the tasks, that task is dispatched, and if the next time slot is unassigned and the count is below the limit, the count is incremented and the index is further advanced to the next but one time slot.

Abstract: A storage component includes multiple nonvolatile memory cells and a storage controller that manages the storage of data in and the retrieval of data from the memory cells. A computing device includes or is coupled to the storage component. A processor of the computing device provides a processor power enable signal to the storage component, allowing the processor to turn on and off power to the memory cells as the processor deems appropriate. The storage controller provides a storage controller power enable signal that allows the storage controller to turn on and off power to the memory cells as the storage controller deems appropriate. These power enable signals are inputs to a combinatorial logic component that allows the storage controller to have power to the memory cells turned off even though the processor may deem that power to the memory cells is to be turned on.

Abstract: Memory systems include a first semiconductor memory module and a processor. The processor is configured to access the first semiconductor memory module by units of a page, and further configured to respond to an occurrence of a page fault in a specific page, which is associated with a virtual address corresponding to an access target, by adjusting a number of pages and allocating pages in the first semiconductor memory module corresponding to the adjusted number of the pages, which are associated with the virtual address.