Abstract: Technologies are described herein for reducing network traffic when replicating memory data across hosts. The memory data stored in a main memory of the host computer is replicated to a main memory of a second host computer. Memory data from the local data storage of the second host computer and other hosts computers that is a duplicate of memory data from the main memory is identified. Instead of sending the memory data from the main memory that is duplicated, the duplicated memory is copied from the local storage of the second computer or from one or more of the other computers to the main memory of the second host computer.

Abstract: A semiconductor memory device includes: an internal circuit; a write control circuit suitable for writing write data into the internal circuit based on a write strobe signal during a normal write operation, and writing test data into the internal circuit based on a read strobe signal during a test write operation; and a read control circuit suitable for generating the read strobe signal and outputting the read strobe signal together with read data read from the internal circuit during a normal read operation or a test read operation, and generating the read strobe signal and providing the write control circuit with the read strobe signal during the test write operation.

Abstract: A system includes a memory and at least one processor to continually analyze at least one of metrics, events, and conditions in a computer network, under normal operating conditions in the computer network, obtain a first level of data from at least one hardware device in the computer network, detect that one of a condition and an event has occurred in the computer network, automatically transmit an instruction to modify the first level of data obtained from the at least one hardware device to a second level of data more robust than the first level of data when one of the condition and the event has occurred, collect the second level of data from the at least one hardware device, and store the second level of data obtained from the at least one hardware device.

Abstract: A memory device include write leveling circuitry that is configured to receive a write command from the command interface. The write leveling circuitry also receives a data strobe (DQS) signal from a host device (e.g., processor) and receives a clock signal from the host device. The write leveling circuitry also compares phases of the DQS signal and the clock signal using a phase detector. The write leveling circuitry also generates an internal write signal (IWS) based upon the write command, and outputs a captured result of a write leveling operation based at least in part on the compared phases and the IWS.

Abstract: Example implementations relate to a capability enforcement processor. In an example, a capability enforcement processor may be interposed between a memory that stores data accessible via capabilities and a system processor that executes processes. The capability enforcement processor intercepts a memory request from the system processor and enforces the memory request based on capability enforcement processor capabilities maintained in per-process capability spaces of the capability enforcement processor.

Abstract: The technology disclosed herein includes capturing a media content from a media recording device, generating a hash of the media content, storing the media content in a storage device, and transmitting a media transaction to a distributed ledger, the media transaction comprising the location of the media content in the storage device and the hash of the media content.

Abstract: A method is applied to an electronic device, all storage space of the electronic device includes internal storage space and at least one external storage space, and the method includes: receiving a data write instruction, where the data write instruction carries target write data; selecting at least one of all the storage space as target storage space according to a preset rule, and performing a write operation in the target storage space; and after the write operation is completed, updating a virtual file that is obtained by summarizing and combining files of a same file type in all the storage space of the electronic device and that is stored in a virtual storage card, and updating a mapping relationship between a virtual storage path corresponding to the virtual storage card and a physical storage path corresponding to the target storage space.

Abstract: One embodiment is related to a method for automatically removing a mount point, comprising: determining whether a vMotion live migration has been completed for a virtual machine (VM) recovered through Instant Access from a backup storage system; after the vMotion live migration has been completed, determining whether a datastore corresponding to a backup image of the VM on the backup storage system is empty; in response to determining that the datastore corresponding to the backup image of the VM on the backup storage system is empty, removing automatically a mount point corresponding to the datastore; and after removing the mount point, freeing up storage space on the backup storage system corresponding to the datastore.

Abstract: The present invention provides a microcontroller, wherein the microcontroller includes a processor, a first memory and a cache controller. The first memory includes at least a working space. The cache controller is coupled to the first memory, and is arranged for managing the working space of the first memory, and dynamically loading at least one object from a second memory to the working space of the first memory in an object-oriented manner.

Abstract: Methods of operating a memory system comprising a plurality of memory devices include loading respective sets of termination information to a subset of memory devices of the plurality of memory devices, and, for each memory device of the subset of memory devices, storing its respective set of termination information to an array of non-volatile memory cells of that memory device. For each memory device of the subset of memory devices, its respective set of termination information comprises address information of the memory system and one or more termination values associated with that address information.

Abstract: A system and method of exitless extended page table switching includes a nested hypervisor writing pointer addresses to an extended page table list, where each pointer address is associated with an extended page table. The host hypervisor verifies that each pointer address corresponds to a guest physical address for one of the extended page tables. The host hypervisor then creates shadow extended page tables, each of which includes a shadow pointer address corresponding to a host physical address, writes, in a local page table list, each shadow pointer address and an index of each shadow extended page table, and loads the local page table list. The nested guest requests to switch between two extended page tables. The nested guest then identifies a matching entry for an extended page table in the local page table list and switches to the extended page table without triggering an exit.

Abstract: A method for scheduling tasks to a cyclic schedule, comprising maintaining a request queue, a count, the count being initialized to a given limit, and an index of a current time slot within the schedule. Periodically, if the request queue contains a reference to an urgent task among the tasks, that reference is removed from the request queue and the urgent task is dispatched and if the request queue is empty, the index is advanced to the next time slot within the schedule. If the next time slot is statically assigned to a task among the tasks, that task is dispatched, and if the next time slot is unassigned and the count is below the limit, the count is incremented and the index is further advanced to the next but one time slot.

Abstract: A storage component includes multiple nonvolatile memory cells and a storage controller that manages the storage of data in and the retrieval of data from the memory cells. A computing device includes or is coupled to the storage component. A processor of the computing device provides a processor power enable signal to the storage component, allowing the processor to turn on and off power to the memory cells as the processor deems appropriate. The storage controller provides a storage controller power enable signal that allows the storage controller to turn on and off power to the memory cells as the storage controller deems appropriate. These power enable signals are inputs to a combinatorial logic component that allows the storage controller to have power to the memory cells turned off even though the processor may deem that power to the memory cells is to be turned on.

Abstract: Memory systems include a first semiconductor memory module and a processor. The processor is configured to access the first semiconductor memory module by units of a page, and further configured to respond to an occurrence of a page fault in a specific page, which is associated with a virtual address corresponding to an access target, by adjusting a number of pages and allocating pages in the first semiconductor memory module corresponding to the adjusted number of the pages, which are associated with the virtual address.

Abstract: A memory system includes a memory device including plural memory blocks, each including plural pages storing data, and a controller suitable for loading data from first memory blocks among the plural memory blocks to perform command operations corresponding to plural commands and securing second memory blocks among the plural memory blocks to store data updated by the command operations. The controller can exclude the first memory blocks from the second memory blocks.

Abstract: Examples of techniques for deferred disclaim of memory pages are described herein. An aspect includes, based on freeing of a last allocation on a first memory page, placing, by a processor, the first memory page on a deferred disclaim list. Another aspect includes, based on freeing of the last allocation on the first memory page, setting, by the processor, a first hidden flag in a first page table entry corresponding to the first memory page.

Abstract: An apparatus and method for processing array of structures (AoS) and structure of arrays (SoA) data. For example, one embodiment of a processor comprises: a destination tile register to store data elements in a structure of arrays (SoA) format; a first source tile register to store indices associated with the data elements; instruction fetch circuitry to fetch an array of structures (AoS) gather instruction comprising operands identifying the first source tile register and the destination tile register; a decoder to decode the AoS gather instruction; and execution circuitry to determine a plurality of system memory addresses based on the indices from the first source tile register, to read data elements from the system memory addresses in an AoS format, and to load the data elements to the destination tile register in an SoA format.

Abstract: One example of the present disclosure includes performing a comparison operation in memory using a logical representation of a first value stored in a first portion of a number of memory cells coupled to a sense line of a memory array and a logical representation of a second value stored in a second portion of the number of memory cells coupled to the sense line of the memory array. The comparison operation compares the first value to the second value, and the method can include storing a logical representation of a result of the comparison operation in a third portion of the number of memory cells coupled to the sense line of the memory array.

Abstract: A method for execution by a dispersed storage and task (DST) processing unit that includes a processor includes generating storage unit heat data based on a plurality of temperature readings received from each of a plurality of storage units, where the storage unit heat data indicates a first hot storage unit. A pair of storage units is selected from the plurality of storage units based on the storage unit heat data, where the pair of storage units includes the first hot storage unit and a second storage unit. A data swap request is generated for transmission to the pair of storage units, where the data swap request includes an instruction to transfer at least one first data slice from the first hot storage unit to the second storage unit and to transfer at least one second data slice from the second storage unit to the first hot storage unit.

Abstract: A memory system includes a storage device including a plurality of dies in which data is stored, and a memory controller configured to control an operation of the storage device, wherein the dies store pieces of reliability grade information about the respective dies, and wherein the memory controller receives the pieces of reliability grade information from the dies, sets reference values for managing the dies depending on the received reliability grade information, and manages the respective dies based on the reference values.

Abstract: An interruption of services for a multi-tier application is avoided based on a probability of a disk failure. A criticality factor value is assigned to a component of the multi-tier application. A disk failure probability value is predicted for a disk drive of a disk volume accessed by the component. If the disk failure probability value is above a predefined probability value and the assigned criticality factor value of the component is below a predefined criticality threshold value for the disk drive, the disk drive is marked to be exchanged during a next maintenance window. Alternatively, if the disk failure probability value is above the predefined probability value and the assigned criticality factor value of the component is equal to or above the predefined criticality threshold value, an immediate full copy of data of the disk drive is performed to a newly instantiated disk volume on another disk drive.

Abstract: In one form, a data processing system includes a host integrated circuit having a memory controller, a memory bus coupled to the memory controller, and a memory module. The memory module includes a bulk memory and a memory module scratchpad coupled to the bulk memory, wherein the memory module scratchpad has a lower access overhead than the bulk memory. The memory controller selectively provides predetermined commands over the memory bus to cause the memory module to copy data between the bulk memory and the memory module scratchpad without conducting data on the memory bus in response to a data movement decision.

Abstract: Apparatuses and methods for adaptive control of memory are disclosed. One example apparatus includes a memory configured to store information. Memory of the memory is configured with two or more information depth maps. The example apparatus further includes a memory translation unit (MTU) configured to support an intermediate depth map of the memory during the migration of the information stored at the memory from a first information depth map of the two or more information depth maps to a second information depth map of the two or more information depth by maintaining mapping tables. The MTU is further configured to provide a mapped address associated with a requested address of a memory access request to the memory based on the mapping tables.

Abstract: A device, memory, method and system directed to fast data storage on a block storage device that reduces operational wear on the device. New data is written to an empty write block with a number of write blocks being reused. A location of the new data is tracked. Metadata associated with the new data is written. A lookup table may be updated based in part on the metadata. The new data may be read based the lookup table configured to map a logical address to a physical address.

Abstract: An example method of tracking memory modified by an assigned device includes allocating, by a hypervisor running a virtual machine, guest memory to a guest running on the virtual machine, where a device is assigned to the virtual machine. The method also includes reading, while the virtual machine is running on the hypervisor, a first input/output (I/O) state that indicates whether the device is currently processing one or more I/O requests, where the first I/O state is writable by the guest. The method further includes determining whether the first I/O state indicates that the device is currently processing one or more I/O requests. The method also includes determining to not transmit a memory page to a destination in response to determining that the first I/O state indicates that the device is currently processing one or more I/O requests. The memory page corresponds to the first I/O state.

Abstract: Provided are systems and methods for an address translation circuit for a memory controller. In various implementations, the address translation circuit includes an address translation table operable to include a subset of address translations for a processor memory. An address translation memory can include all address translations for the processor memory. The address translation circuit can be operable to receive an input address for a transaction to processor memory. The address translation circuit can determine an index for the address translation table by inputting the input address into a hash function. The address translation circuit can read a row from the address translation table using the index. The address translation circuit can determine whether an entry in the row includes an address translation for the input address. The address translation can generate and output a translated address using the address translation.

Abstract: A control plane for controlling transfer of data to a data plane is disclosed. In one aspect, the control plane comprises memory cells for storing a digitally coded parameter value and having a data input electrode, a data output electrode and a control electrode, n data input terminals that receive a data input value and apply it to the data input electrode of an associated memory cell, and n data output terminals coupled to a data output electrode of an associated memory cell. The control plane further comprise a first delay line having delay elements and arranged for receiving a stream of control bit values, and a second delay line having delay elements and arranged for receiving a signal for enabling the control bit values in the first delay line, wherein data is transferred in a controlled and synchronized fashion to an output electrode.

Abstract: A method for garbage collection of a volume in a log-structured file system is disclosed. The volume comprises a plurality of segments. Each of the segments comprises a plurality of blocks. An invalid block count of each of the segments is determined. The invalid block count is used as an index for ordering the segments in a garbage collection queue. A plurality of range areas are determined for the index. A migration rate of each range area is determined, and the migration rate of a given range area reflects an intensity of segment migration into/out of the given range area. A negative migration rate reflects a segment migration into the given range area. Garbage collection is performed based upon the migration rate.

Abstract: Embodiments of this disclosure are directed to an execution profiling handler configured for intercepting an invocation of memory allocation library and observing memory allocation for an executable application process. The observed memory allocation can be used to update memory allocation meta-data for tracking purposes. The execution profiling handler can also intercept indirect branch calls to prevent heap allocation from converting to execution and intercept exploitation of heap memory to block execution.

Abstract: A data storage device includes a disk and a plurality of actuators for reading and writing data on the disk in different physical realms. Each physical realm is associated with at least one logical zone domain including at least one logical zone. The at least one logical zone domain corresponds to an actuator of a plurality of actuators that accesses the physical realms associated with the at least one logical zone domain. In one aspect, reading and writing of data is enabled in one or more logical zones in response to a SATA zone activate command. In another aspect, a SATA read or write command is received indicating at least one logical address for data to read or written on the disk. Data is read or written in a physical realm using the actuator corresponding to a logical zone domain including the at least one logical address.

Abstract: Systems and methods are provided for predicting commands. A controller of a memory system includes a receiver for sequentially receiving a plurality of commands for the memory device in a plurality of windows, and a control component including a finite state machine for training multiple groups of states based on characteristics of the plurality of windows, and predicting a characteristic of next commands, which is to be received in a next window subsequent to a last window among the plurality of windows, based on the multiple groups of states.

Abstract: Disclosed is a memory system includes a memory device including a plurality of memory blocks, a write operation management circuit configured to update write operation counts for the plurality of memory blocks, a first block detector configured to detect a hot memory block based on a first operation count value corresponding to the write operation count of a first memory block on which a write operation has been performed among the plurality of memory blocks, a second detector configured to detect a cold memory block based on a second operation count value corresponding to the write operation count of each of second memory blocks adjacent to the first memory block, and a controller configured to copy, if the hot memory block and the cold memory block are detected by the first and second detectors, data of the detected hot memory block or data of the detected cold memory block.

Abstract: A method of performing deduplication by a computing device is provided. The method includes (a) as data is received by the computing device into blocks as part of write requests, creating an entry in a log for each of the blocks, each entry including information about that respective block and a digest computed from that respective block; and (b) after accumulating multiple entries in the log, processing the log for delayed deduplication, the processing including (i) retrieving digests from the log, (ii) performing lookups within a deduplication table of the retrieved digests, and (iii) performing deduplication operations based on the lookups using the information about blocks included within the log. An apparatus, system, and computer program product for performing a similar method are also provided.

Abstract: A communication unit according to the present disclosure includes: a communication circuit section that receives transmission data divided into head data and one or more subsequent data from an communicated unit over a period of a plurality of time-segments; a storage section having a storage region in which at least the transmission data received by the communication circuit section is stored; and a control section that places a limitation on an access period to cause a period of access to the storage region in a period of a time-segment in which the subsequent data is transmitted to become shorter than a period of access to the storage region in a period of a time-segment in which the head data is transmitted.

Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.

Abstract: Embodiments provide a proxy between device management messaging protocols that are used to manage devices that are I2C bus endpoints coupled to a remote access controller. A map is generated of the detected I2C bus endpoints. Mapped I2C bus endpoints that support PLDM (Platform Level Data Model) messaging are identified. Next, the mapped I2C bus endpoints that do not correspond to an identified PLDM endpoint are presumed to be IPMI (Intelligent Platform Management Interface) endpoints and are mapped accordingly. A virtual PLDM endpoint for each of the presumed IPMI I2C bus endpoints. A remote access controller is configured for use of PLDM messaging with the virtual PLDM endpoints such that these PLDM messages are translated by the proxy to equivalent IPMI commands and transmitted to the IPMI endpoints. The proxy similarly converts IPMI messages from the IPMI endpoints to equivalent PLDM messages and provided to the remote access controller via the virtual PLDM endpoint.

Abstract: A method, an apparatus, and a system have been disclosed. An embodiment of the method includes an autonomous memory device receiving a set of instructions, the memory device executing the set of instructions, combining the set of instructions with any data recovered from the memory device in response to the set of instructions into a packet, and transmitting the packet from the memory device.

Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first memory cell of the rewritable non-volatile memory module by a first read voltage level; decoding the first data by a decoding circuit; reading second data from the first memory cell by a second read voltage level; obtaining reliability information according to a first data status of the first data and a second data status of the second data, and the first data status and the second data status reflect that a first bit value of the first data is different from a second bit value of the second data; and decoding the second data by the decoding circuit according to the reliability information.

Abstract: A semiconductor memory system and an operating method thereof include a controller; and a memory device including a memory page manager, Nand pages, and multiple cache pages, wherein the Nand pages include current Nand pages and next Nand pages, wherein the current Nand pages is corresponding to a read command received from the controller, the memory page manager is configured to manage correlation of the Nand pages and the multiple cache pages, predict next Nand pages in accordance at least in part with the read command, the current Nand pages, or a combination thereof, and send the Nand pages to the controller, and the multiple cache pages contain pages loaded from the Nand pages.

Abstract: Embodiments of the present invention provide a method, system and computer program product for limiting client side data storage based upon client geolocation. In an embodiment of the invention, a method for the differentiated treatment of data at rest in a mobile device includes receiving in a cache manager a request to cache data in a cache of a mobile device. Also, a geolocation for the mobile device is retrieved contemporaneous with the receipt of the request. Thereafter, it is determined from the geolocation whether or not the mobile device is present within a restricted geographic zone. Finally, in response to determining that the mobile device is present within a restricted geographic zone, the cache manager is directed to cache the data in a cache in the mobile device. But, otherwise the cache manager is directed to cache the data in a cache disposed in the computer communications network.

Abstract: Technologies for providing shared memory for accelerator sleds includes an accelerator sled to receive, with a memory controller, a memory access request from an accelerator device to access a region of memory. The request is to identify the region of memory with a logical address. Additionally, the accelerator sled is to determine from a map of logical addresses and associated physical address, the physical address associated with the region of memory. In addition, the accelerator sled is to route the memory access request to a memory device associated with the determined physical address.

Abstract: A Data Storage Device (DSD) includes a non-volatile memory configured to store data, and control circuitry configured to receive a memory access command from a host to access data in the non-volatile memory. A location is identified in the non-volatile memory for performing the memory access command using an Address Translation Layer (ATL) that has a finer logical-to-physical granularity than a logical-to-physical granularity of a logical block-based file system executed by the host or a granularity based on a memory Input/Output (IO) transaction size of a processor of the host. The non-volatile memory is accessed at the identified location to perform the memory access command.

Abstract: The concepts relate to data handling, and more specifically to data handling scenarios where data is revised on one computer and stored on another computer. One example can obtain a set of blobs relating to revisions of a file. The example can determine a target size of datastore blobs. In an instance where a total size of the set of blobs is less than the target size, this example can aggregate the set of blobs into an individual datastore blob. Otherwise, the example can identify new or edited individual blobs of the set and aggregate the new or edited individual blobs into first datastore blobs. The example can also aggregate other individual blobs of the set into second datastore blobs.

Abstract: A memory system includes: a plurality of memory devices, each of which includes a first block and a second block; and a controller suitable for: storing data received from a host in a buffer; selecting a first block, of a memory device of the plurality of memory devices, to be programmed with the data; detecting a size of the data; controlling the memory device to program the data into the selected first block when the size is detected to be equal to a one-shot program size; determining a status of the memory device including the selected first block when the size is detected to be smaller than the one-shot program size; controlling the memory device to program the data into the selected first block when the memory device including the selected first block is determined to be in a first status; and controlling the memory device to program the data into the second block of the memory device when it is determined to be is a second status.

Abstract: Package structure with folded die arrangements and methods of fabrication are described. In an embodiment, a package structure includes a first die and vertical interposer side-by-side. A second die is face down on an electrically connected with the vertical interposer, and a local interposer electrically connects the first die with the vertical interposer.

Abstract: According to some example embodiments, a method includes receiving, a first command from a host device; determining, if the first command is part of an association group of commands by determining a first value of a first parameter of the first command in an association context table entry is greater than zero, the first parameter including a total number of commands in the association group of commands; determining, a first value of a second parameter of the first command, the second parameter including a tag value identifying the association group of commands; decrementing, the first value of the first parameter of the first command in the association context table entry; determining, if the first value of the first parameter in the association context table entry is zero; and executing, an action indicated in a third parameter of the first command.

Abstract: Techniques are provided for selectively storing data into allocation areas using streams. A set of allocation areas (e.g., ranges of block numbers such as virtual block numbers) are defined for a storage device. Data having particular characteristics (e.g., user data, metadata, hot data, cold data, randomly accessed data, sequentially accessed data, etc.) will be sent to the storage device for selective storage in corresponding allocation areas. For example, when a file system receives a write stream of hot data, the hot data may be assigned to a stream. The stream will be tagged using a stream identifier that is used as an indicator to the storage device to process data of the stream using an allocation area defined for hot data. In this way, data having different characteristics will be stored/confined within particular allocation areas of the storage device to reduce fragmentation and write amplification.

Abstract: Techniques enable offloading operations to be performed closer to where the data is stored in systems with sharded and erasure-coded data, such as in data centers. In one example, a system includes a compute sled or compute node, which includes one or more processors. The system also includes a storage sled or storage node. The storage node includes one or more storage devices. The storage node stores at least one portion of data that is sharded and erasure-coded. Other portions of the data are stored on other storage nodes. The compute node sends a request to offload an operation to the storage node to access the sharded and erasure-coded data. The storage node then sends a request to offload the operation to one or more other storage nodes determined to store one or more codes of the data. The storage nodes perform the operation on the portions of locally stored data and provide the results to the next-level up node.

Abstract: Improving the multi-site software update for extension switches by automatically assigning extension switches at each data center with a role and then providing state messages between the extension switches to stage software update operations between the various extension switches that are involved. This allows the network administrator to commence the software update process on the extension switches at each data center without waiting for any extension switch to complete operations. The extension switches communicate with each other and the software update process completes automatically, with all extension switches at all data centers updated without further network administrator input.

Abstract: Provided herein may be a storage device and a method of operating the storage device. The storage device includes a memory device including a plurality of system blocks; and a memory controller configured to perform a read reclaim operation of copying system data stored in a selected system block to another one of the plurality of system blocks using information obtained during loading of the system data into the selected system block.