Abstract: An interface of a memory sub-system can determine that a particular write command received from a host has a same address as a subsequently received write command from the host. The interface can delete the particular write command if it is still in the interface or send a signal to delete the particular write command if the write command has already been provided from the interface.

Abstract: Combined operational steps and device characteristics help preserve data against integrity threats. Data is divided into critical data and non-critical data, based on criteria such as customer requirements, workload criticality, or virtual machine criticality. Data may be generated in a compute node for storage in a storage node, for example. Critical data is stored in a battery-backed memory aperture at physical addresses where it will be flushed ahead of the non-critical data due to a flush order imposed by or on the battery-backed memory, e.g., a bottom-up NVDIMM flush order. Redundant copies of the data (especially non-critical data) may also be kept in case it does not get flushed in time. Battery-backed memory apertures are sized and located according to their battery's characteristics, and may be relocated or resized as conditions change. Flush defragging is performed to optimize use of the aperture, especially within the portion that holds critical data.

Abstract: A method of integrating a distributed ledger represented by a blockchain with a distributed storage network (DSN) begins by sending a proof of existence request to the DSN, the proof of existence request including an object name, an object version, a start time and an end time. The method continues by reading the object metadata for the sent object name. The method continues by checking a revision history from object metadata associated with the sent object name to ensure the object existed by the start time through the end time with no deletions and, if the object did not exist by the start time through the end time with no deletions, rejecting the proof of existence request and returning an error response. If the object did exist by the start time on through the end time with no deletions, the method continues by producing and returning an attestation comprising verification information related to the object.

Abstract: A first set of characteristics corresponding to a first memory device and a second set of characteristics corresponding to a second memory device are received. A first usage threshold for the first memory device based on the first set of characteristics and a second usage threshold for the second memory device based on the second set of characteristics are determined. Data is stored at the first memory device or the second memory device based on the first usage threshold for the first memory device and the second usage threshold for the second memory device.

Abstract: An apparatus comprises a host device configured to communicate over a network with first and second storage systems. The host device detects an association in at least one of the first and second storage systems between a source logical storage device of the first storage system and a target logical storage device of the second storage system, and responsive to the detected association, establishes a migration session in the host device for migration of the source logical storage device to the target logical storage device. The host device also obtains an indication from at least one of the first and second storage systems that a corresponding migration session has been activated in the first and second storage systems, and activates the previously-established migration session in the host device based at least in part on the obtained indication for migration of the source logical storage device to the target logical storage device.

Abstract: Disclosed are devices, systems and methods for polar coding and decoding for correcting deletion and insertion errors caused by a communication channel. One exemplary method for error correction includes receiving a portion of a block of polar-coded symbols that includes d?2 insertion or deletion symbol errors, the block comprising N symbols, the received portion of the block comprising M symbols; estimating, based on one or more recursive calculations in a successive cancellation decoder (SCD), a location or a value corresponding to each of the d errors; and decoding, based on estimated locations or values, the portion of the block of polar-coded symbols to generate an estimate of information bits that correspond to the block of polar-coded symbols, wherein the SCD comprises at least log2(N)+1 layers, each comprising up to d2N processing nodes arranged as N groups, each of the N groups comprising up to d2 processing nodes.

Abstract: An approach is provided for implementing near-memory data reduction during store operations to off-chip or off-die memory. A Near-Memory Reduction (NMR) unit provides near-memory data reduction during write operations to a specified address range. The NMR unit is configured with a range of addresses to be reduced and when a store operation specifies an address within the range of addresses, the NRM unit performs data reduction by adding the data value specified by the store operation to an accumulated reduction result. According to an embodiment, the NRM unit maintains a count of the number of updates to the accumulated reduction result that are used to determine when data reduction has been completed.

Abstract: An operating method of a memory system includes determining whether a write command currently provided is a sequential write command or a random write command, performing a garbage collection operation based on whether a total capacity of data provided after a preceding garbage collection operation exceeds a sequential command threshold value, when it is determined that the write command is a sequential write command, and performing the garbage collection operation based on whether a number of sequential write commands among a set number of commands currently provided, is greater than or equal to a predetermined number and whether the total capacity of the data provided after the preceding garbage collection operation exceeds the sequential command threshold value, when it is determined that the write command is a random write command.

Abstract: A memory reclamation method and apparatus, where the method includes determining a target process from a background process list when current available memory of a system is less than a memory threshold, where the background process list includes a process of one or more applications, the target process is a process among the process of the one or more applications meeting a condition that an absolute value of a difference between memory occupied by the process and a memory pressure value is less than a preset threshold, and the memory pressure value is a difference between the memory threshold and the current available memory of the system, and sending a processing instruction to a system kernel to trigger the system kernel to reclaim the memory occupied by the target process.

Abstract: According to one or more embodiments of the present invention, computer implemented method includes obtaining by an input/output (I/O) subsystem a request block that includes a command code indicating a STORE IOP-UTILIZATION DATA command for tracking resource utilization during an asynchronous execution of an instance of a CPU DEFLATE command. The method further includes, based on the command code, initiating a command response block. The command response block includes multiple entries for input/output processor (IOP) utilization, each entry corresponding to resource utilization measurements of each IOP in the I/O subsystem. The method further includes, storing, in a command response code field of the command response block, a response code indicating that the resource utilization measurements have been recorded in the entries for IOP utilization. The response block includes a length code indicating a length of the response block and the response code field.

Abstract: A method, computer program product, and computer system for identifying, by a computing device, a pattern in a super block of a logger tier. It may be determined that the pattern in the super block of the logger tier is a known pattern, wherein the known pattern indicates invalid data in the logger tier. The logger tier may be booted up by storing an unknown pattern in the super block into the logger tier, wherein the unknown pattern indicates valid data in the logger tier.

Abstract: Disclosed herein is method and system for managing storage space complexity in a storage unit. In an embodiment, operational parameters related to memory operations and storage parameters related to memory blocks of the storage unit are analyzed to estimate storage capacity of each of the memory blocks. Subsequently, the memory blocks are clustered into plurality of clusters based on the storage capacity. Further, one or more of the plurality of clusters are selected for performing future memory operations based on ranking of the plurality of clusters. In some embodiments, the present disclosure helps in dynamically managing storage space complexity in the storage unit and optimizes the storage space utilization. Also, the present disclosure automatically handles storage volumes, thereby reducing latency in memory backup operations and reducing amount of buffer/cache memory required.

Abstract: The present disclosure discloses a method and apparatus for loading an application. An embodiment of the method comprises: selecting, in a programmable read-only memory, a storage space for storing a preset data section in an executable file of an application; copying the preset data section to a memory, and relocating the preset data section based on a start address of the storage space; and copying the relocated preset data section to the storage space. A relocation of a code portion of the executable file in the memory is implemented, and the relocated code portion is then written back into the programmable read-only memory, so that the relocation of the code portion can be completed only by one erase operation for a memory block, thereby reducing system overheads during the application loading process, and reducing wear of the programmable read-only memory.

Abstract: The time required for recovery in a distributed computing system can be reduced. At least one node (for example a server) or a different computer (for example a management server) are provided in the distributed computing system which includes a plurality of nodes existing at a plurality of sites. One or more sites at which one or more nodes that hold one or more datasets identical to one or more datasets held by a node to be recovered are identified. For the recovery, it is determined, on the basis of the one or more identified sites, a restore destination site that is a site of a node to which the one or more identical datasets are to be restored from among the plurality of sites.

Abstract: A method and apparatus for reserving a usable storage space on a storage device is provided. The method includes collecting context data representing an environment surrounding the storage device; selecting at least one file from among files stored in the storage device by using at least one of the context data and user profile data; and processing the selected file and reserving a usable storage space on the storage device. The method reserves the usable storage space by using the context data or user profile data, thereby allowing efficient reserving of usable storage space without a user's manual intervention and preventing waste of unnecessary resources.

Abstract: A method, computer system, and a computer program product for soft fencing is provided. The present invention may include identifying a logical device swap occurred. The present invention may also include, in response to a logical device swap, creating a soft fence command. The present invention may then include issuing the created soft fence command.

Abstract: A non-volatile solid-state storage is provided. The non-volatile solid state storage includes a non-volatile random access memory (NVRAM) addressable by a processor external to the non-volatile solid state storage. The NVRAM is configured to store user data and metadata relating to the user data. The non-volatile solid state storage includes a flash memory addressable by the processor. The flash memory is configured to store the user data responsive to the processor directing transfer of the user data from the NVRAM to the flash memory.

Abstract: A control method of a storage device may include the steps of determining, by a storage device controller of the storage device, whether the storage device has to move internal data; deciding, by the storage device controller, a data movement allocation ratio based on at least some of internal data movement requests and the number of free pages in the storage device, when it is determined that the storage device has to move internal data; and allocating, by the storage device controller, one or more programming times to complete a first data number of internal data movement operations corresponding to at least some of the internal data movement requests and a second data number of host data write operations, such that the ratio of the first and second data numbers coincides with the data movement allocation ratio.

Abstract: A computer system includes a plurality of servers connected to each other via a communication line, each server including a memory and a processor, an OS program and a storage program. The storage program is executed by the processor, and one of the plurality of servers acts as a request source server while one of the other servers acts as a request destination server. When the request source server reads data from the request destination server, the processor of the request source server executes the storage program to transmit a data read request to the request destination server. The processor of the request destination server then executes a storage memory driver incorporated in the OS program to read the requested data from an own memory and transmit the read data to the request source server. The request source server then executes the storage program to acquire the data.

Abstract: Techniques are disclosed relating to compression of data stored at different cache levels. In some embodiments, programmable shader circuitry is configured to execute program instructions of compute kernels that write pixel data. In some embodiments, a first cache is configured to store pixel write data from the programmable shader circuitry and first compression circuitry is configured to compress a first block of pixel write data in response to full accumulation of the first block in the first cache circuitry. In some embodiments, second cache circuitry is configured to store pixel write data from the programmable shader circuitry at a higher level in a storage hierarchy than the first cache circuitry and second compression circuitry is configured to compress a second block of pixel write data in response to full accumulation of the second block in the second cache circuitry.

Abstract: Disclosed aspects relate to counter-fraud operation management. A counter-fraud operation may be executed using an initial set of parameter values for a set of parameters of the counter-fraud operation. A set of user counter-fraud activities of a user may be monitored corresponding to a user interface. A set of user feedback data may be captured to determine a feedback-driven set of parameter values for a set of parameters of the counter-fraud operation. The feedback-driven set of parameter values may be determined for the set of parameters of the counter-fraud operation. The counter-fraud operation using the feedback-driven set of parameter values may be executed.

Abstract: An information processing system comprises one or more processing platforms and implements a centralized storage provisioning and management system and a plurality of service provider storage systems coupled to the centralized storage provisioning and management system. The centralized storage provisioning and management system is configured to control provisioning and management of the service provider storage systems utilizing information collected from the service provider storage systems. The service provider storage systems may comprise respective service provider data centers, and the centralized storage provisioning and management system may comprise an additional data center separate from the service provider data centers. The centralized storage provisioning and management system may comprise a centralized control path implemented apart from the service provider storage systems.

Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

Abstract: Host data segments are received and stored in a cached data unit corresponding to a previously stored data unit currently stored in non-volatile memory. Metadata is created that identifies unmodified previously stored segments of host data in the previously stored data unit that correspond to the received host data segments, the metadata including an update flag indicating that the previously stored data unit requires updating. In response to detecting the unexpected interruption of power, the cached data unit and the metadata is written to an area of the non-volatile memory array that is different than where the previously stored data unit is currently stored. Upon resuming operation following the unexpected interruption of power, the cached data unit is identified based on the update flag, as having been saved in response to the power shutdown without the previously stored data unit being updated in the non-volatile memory array, and then reloaded into the memory cache.

Abstract: Methods, apparatus, and processor-readable storage media for generating unique virtual process identifiers are provided herein. An example computer-implemented method includes generating a virtual process identifier for a process within a given network, wherein the virtual process identifier is based at least in part on multiple items of process-related information; associating the virtual process identifier with one or more types of events to be carried out within the given network in connection with the process; filtering repetitive events from a set of processed events carried out in connection with the process, wherein filtering the repetitive events comprises identifying multiple instances of the virtual process identifier associated with multiple instances of the same type of event; and reporting, to at least one server, the processed events remaining subsequent to the filtering step.

Abstract: A computer-implemented method, according to one embodiment, includes: receiving a multi-page read request and predicting whether using a multi-plane read operation to read pages of storage space in memory which correspond to the multi-page read request will result in a bit error rate that is in a predetermined range. In response to predicting that using the multi-plane read operation to read the pages will not result in a bit error rate that is in the predetermined range, a threshold voltage shift (TVS) value is computed for the multi-plane read operation. Furthermore, the pages are read using the multi-plane read operation with the computed TVS. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: A memory controller includes a plurality of control signal pads and selectively controls a first-type memory and a second-type memory. The memory controller also includes a control signal generation unit configured to generate a control signal for controlling a selected memory. The memory controller further includes a control signal transfer unit configured to apply bits of a first control signal generated for controlling the first-type memory to respective control signal pads of the plurality of control signal pads, apply bits of a second control signal generated for controlling the second-type memory to a first control signal pad group selected among the plurality of control signal pads, and apply the second control signal to a second control signal pad group which is selected among the plurality of control signal pads independently of the first control signal pad group.

Abstract: A first signal may be received from a memory device at a first interconnect terminal of a number of interconnect terminals via a serial communication interface that indicates the memory device includes a NAND type memory device. Whether a second signal that indicates the NAND type memory device is initialized has been received from the memory device at a second interconnect terminal of the number of interconnect terminals may be determined. An operation associated with the NAND type memory device may be performed at the second interconnect terminal and a third interconnect terminal in response to determining the second signal has been received from the memory device indicating the NAND type memory device is initialized.

Abstract: A data storage apparatus in accordance with an embodiment may include a memory device, a memory controller, and a media controller. The memory device may store data. The memory controller may output a packetized request signal for the memory device and receive a response signal to the packetized request signal according to a predetermined protocol. In response to a request packet provided from the memory controller, the media controller may generate a media command corresponding to the memory device, perform a read or write operation on the memory device, generate a response packet upon completion of the read or write operation, and transmit the generated response packet to the memory controller.

Abstract: System and method are provided for storing data using programmable rules on containers for collections of data items presented through the operating environment. This invention gives a container (folders or enhanced containers) the ability to be more than a straight-forward receptacle to contain a collection of data objects and other sub-containers. The invention provides for when data is added to a container system, collecting information from the data item and any pre-existing metadata, matching the information to a container using the container's rules, and if any matching containers are found, filing of the data item proceeds into any candidate locations.

Abstract: Apparatus and methods of operating solid-state drives in a storage system are described. A method includes adjusting, by a host controller of a storage system during run-time, storage bandwidth for a storage system process responsive to an input output (I/O) write request to write data to the storage system that includes multiple solid-state storage drives by determining an allocation share for the storage system process requesting to write the data, and responsive to determining an open segment usage by the storage system process is under the allocation share for the storage system process, opening a new segment for the storage system process.

Abstract: A method and system for dynamic backup policy handshaking. Specifically, the method and system disclosed herein entail optimizing storage space utilization for backup, archiving, and/or disaster recovery-purposed data storage. That is, based on time projections until the data storage reaches capacity, the utilization of the remaining storage space may be optimized without compromising data protection in order to prolong the use of the data storage. In prolonging the utilization of the data storage, tiered data backup policies may be adjusted.

Abstract: Systems, methods, and apparatuses relating to instructions to compartmentalize memory accesses and execution (e.g., non-speculative and speculative) are described.

Abstract: Embodiments for reducing resource consumption of a similarity index in data deduplication by a processor. Only a latest generation of repository data is represented in the similarity index. Implicit deletion is applied in the similarity index. A subset of bytes of a full representative value is maintained in a similarity index entry. A respective one of a plurality of similarity units is deduplicated with a corresponding similarity unit of a previous snapshot, and a deduplication coverage thereof is examined. If a deduplication coverage threshold is not met, a similarity search is conducted and the respective one of the similarity units is deduplicated with a found similarity unit residing in the similarity index.

Abstract: A data storage system includes an accelerator pool and data silos. The accelerator pool obtains a data storage request for first data; stores a copy of the first data locally in a memory of the accelerator pool; in response to storing the copy of the first data: sends an acknowledgement to a requesting entity that generated the data storage request; and, after sending the acknowledgement, stores at least one second copy of the first data in the data silos. The acknowledgement indicates that the first data is redundantly stored in at least two different fault domains.

Abstract: Access to a memory shared between a first interface and a second interface is arbitrated. Following a request to access the memory emanating from the second interface, while current access to the memory is granted to the first interface, a count is triggered having a maximum count time. A access to the memory is authorized for the second interface at the end of occupation of the access granted to the first interface if the end of occupation finishes before the end of the maximum count time, or otherwise at the end of the maximum count time.

Abstract: An apparatus monitors an access load state of a plurality of logical volumes of a first storage device, and determines that an access load state of a subset of the plurality of logical volumes has changed from a high load state to a low load state. The apparatus migrates, when the subset of the plurality of logical volumes remains in a low load state after an elapsed setting time since the load state of the subset of the plurality of logical volumes changed from a high load state to a low load state, data stored in the subset of the plurality of logical volumes to a second storage device having an access rate lower than the first storage device.

Abstract: A method and apparatus including a cache controller coupled to a cache memory, wherein the cache controller receives a plurality of cache access requests, performs a pre-sorting of the plurality of cache access requests by a first stage of the cache controller to order the plurality of cache access requests, wherein the first stage functions by performing a presorting and pre-clustering process on the plurality of cache access requests in parallel to map the plurality of cache access requests from a first position to a second position corresponding to ports or banks of a cache memory, performs the combining and splitting of the plurality of cache access request by a second stage of the cache controller, and applies the plurality of cache access requests to the cache memory at line speed.

Abstract: Deploying client-specific applications in a storage system utilizing redundant system resources, including: identifying a redundant controller in the storage system, wherein the storage system includes at least a first controller and the redundant controller; and executing one or more applications on the redundant controller, wherein the one or more applications are executed in a container.

Abstract: Disclosed is an apparatus including a memory device. The memory device includes a memory array, a number of non-volatile memory sections configured to store a copy of operational information for the memory array, and a controller coupled to the number of non-volatile memory sections. The controller can responsive to a first wake-up operation, select a first non-volatile memory section as a starting section to retrieve the copy of operational information. The controller can responsive to a second wake-up operation, select a second non-volatile memory section as the starting section to retrieve the copy of operational information without regard to success of a prior attempt to retrieve the copy of operational information.

Abstract: Providing power to a server includes a switch with power sourcing equipment (PSE) and a server with a network interface controller (NIC) the PSE to transfer power to the NIC of the server via a network cable to change configuration settings prior to the server booting from a stand-by mode.

Abstract: Devices and techniques for temperature informed memory refresh are described herein. A temperature counter can be updated in response to a memory device write performed under an extreme temperature. Here, the write is performed on a memory device element in the memory device. The memory device element can be sorted above other memory device elements in the memory device based on the temperature counter. Once sorted to the top of these memory device elements, a refresh can be performed the memory device element.

Abstract: A method and system are provided for adapting recipes to a cooking appliance. The method includes accessing, using a computing device, first electronic data describing capabilities of a first cooking appliance; accessing, via a network interface using the computing device, second electronic data describing capabilities of a second cooking appliance; comparing the second electronic data with the first electronic data to determine differences in the capabilities of the first and second cooking appliances; altering a recipe, designed for the capabilities of the first cooking appliance, using a processor of the computing device, based on the comparison of the first and second electronic data to adapt the recipe for the second cooking appliance; and converting the adapted recipe into a workflow, provided to a user of the second cooking appliance, to enable performing the adapted recipe on the second cooking appliance.

Abstract: An I/O request processing method in a virtual machine, a device and a computer readable medium are provided. When a backend device of a Guest kernel begins to process an I/O request chain submitted by a frontend device of the Guest kernel into a shared I/O processing memory, the method obtains a starting position of the I/O request chain in the I/O processing memory; according to the starting position of the I/O request chain, sets an element corresponding to the starting position of the I/O request chain in an I/O state array as a value different from initial values of all positions; and upon finishing processing the I/O request chain, sets an element corresponding to the starting position of the I/O request chain in an I/O request state array as a value identical with initial values.

Abstract: One example method includes surveying a computing environment, creating a profile for a data source discovered during surveying of the computing environment, wherein the profile includes information concerning a particular type of the data source, and creating a map that includes the profile. These processes may be performed by a profiler. The method also includes generating a data storage capacity forecast based in part on information contained in the profile. Generation of the data storage capacity forecast may be performed by a predictive engine.

Abstract: Providing global values may include configuring a global memory to include a global counter and configuring processing cores to have private caches each including two sets of buffers, an update toggle and a read toggle. A processing core having a first private cache may perform processing to read a current value for the global counter including determining the current value of the global counter as a mathematical sum of a local counter value and a local delta value from one of the two sets of buffers of the first private cache identified by the read toggle. The processing core may perform processing to modify the global counter by a first amount by updating the local delta value from a specified one of the two set of buffers of the first private cache identified by the update toggle.

Abstract: A system includes a queue and a controller. The queue receives a transactions from masters to access a memory component. The memory component includes a plurality of rows. The controller issues a command to access a row of the plurality of rows in response to receiving a first issued transaction. The first issued transaction is issued by a first master. The controller is configured to prevent issuing an auto-precharge command to keep the row associated with the first issued transaction open if a subsequent transaction in the queue from the first master accesses a same row as the first transaction. The controller is configured to prevent issuing the auto-precharge command to keep the row associated with the first issued transaction open if the controller receives data associated with keeping the row associated with the first issued transaction open.

Abstract: A memory controller, an operating method of the memory controller, and a storage device including the memory controller are disclosed. The memory controller includes: a memory configured to store an address mapping table and a segment mapping table; and a mapping data management module configured to select at least two updated segments among a plurality of segments included in the address mapping table as page data to be stored in one page of a nonvolatile memory, wherein each of the plurality of segments includes a plurality of mapping entries representing mapping information between logical addresses and physical addresses, and wherein the segment mapping table includes physical addresses representing areas in which each of the plurality of segments is stored in the nonvolatile memory.

Abstract: Presented herein are methods and systems for adjusting code files to apply memory protection for dynamic memory regions supporting run-time dynamic allocation of memory blocks. The code file(s), comprising a plurality of routines, are created for execution by one or more processors using the dynamic memory. Adjusting the code file(s) comprises analyzing the code file(s) to identify exploitation vulnerable routine(s) and adding a memory integrity code segment configured to detect, upon execution completion of each vulnerable routine, a write operation exceeding from a memory space of one or more of a subset of most recently allocated blocks allocated in the dynamic memory to a memory space of an adjacent block using marker(s) inserted in the dynamic memory in the boundary(s) of each of the subset's blocks. In runtime, in case the write operation is detected, the memory integrity code segment causes the processor(s) to initiate one or more predefined actions.

Abstract: A number K of N sub-channels that are defined by a code and that have associated reliabilities for input bits at N input bit positions, are to be selected to carry bits that are to be encoded. A localization area that includes multiple sub-channels and is located below fewer than K of the N sub-channels in a partial order of the N sub-channels is determined based on one or more coding parameters. The fewer than K sub-channels of the N sub-channels above the localization area in the partial order are selected, and a number of sub-channels from those in the localization area are also selected. The selected fewer than K sub-channels and the number of sub-channels selected from those in the localization area together include K sub-channels to carry the bits that are to be encoded.