Abstract: A device driver includes an aggregator aggregating data blocks into one or more container objects suited for storage in an object store; and a logger for maintaining in at least one log file for each data block an identification of a container object wherein the data block is stored with an identification of the location of the data block in the container object.

Abstract: A method for dynamic storage tiering may include, but is not limited to: receiving an input/output (I/O) request from a host device; determining whether the I/O request results in a cache hit; and relocating data associated with the I/O request between a higher-performance storage device and lower-performance storage device according to the determination whether the data associated with the I/O request is stored in a cache.

Abstract: A memory storage device, a memory controller, and a method for identifying a valid data are provided. A rewritable non-volatile memory chip of the memory storage device includes physical blocks. Each of the physical blocks has physical pages. In the present method, logical blocks are configured and mapped to a portion of the physical blocks, wherein each of the logical blocks has logical pages. When a data to be written by a host system into a specific logical page is received, a substitute physical block is selected, the data is written into a specific physical page in the substitute physical block, and the address of a physical page in which a previous data corresponding to the specific logic page is written is recorded into the specific physical page. Thereby, a physical page containing the latest valid data can be identified among several physical pages corresponding to a same logical page.

Abstract: Methods, apparatuses, and computer program products for assigning a classification to a dual in-line memory module (DIMM) are provided. Embodiments include determining, by a modifier, a classification of a DIMM; and providing a visual indication of the determined classification of the DIMM, including modifying, by the modifier, a top edge of a printed circuit board of the DIMM.

Abstract: There is provided a method of operating a multipath storage system, the method comprises: identifying a primary storage control port configured to be responsible for a given LBA range and a secondary storage control port configured to have secondary responsibility for the given LBA range; reducing, in a manner unaffecting respective inbound I/O operation, outbound I/O operation related to the given LBA range and occurring at the primary storage control port, thereby causing a situation requiring switching all respective I/O requests to an alternating path; analyzing responsive changes in outbound I/O operation related to the given LBA range and occurring at the secondary storage control port, and verifying operability of switching to the alternating path in accordance with the obtained results.

Abstract: Techniques for client side translation cache prediction are provided. The techniques include obtaining meta data associated with a request, applying a cache prediction model to the meta data to automatically predict one or more translations associated with the request, and storing the one or more translations in a client translation cache.

Abstract: A method for implementing a geometric array in a computing environment is disclosed. In one embodiment, such a method includes providing an array of slots, where each slot is configured to store a pointer. Each pointer in the array points to a block of elements. Each pointer with the exception of the first pointer in the array points to a block of elements that is twice as large as the block of elements associated with the preceding pointer. Such a structure allows the geometric array to grow by simply adding a pointer to the array that points to a new block of elements that is twice as large as the block of elements associated with the preceding pointer in the array. A corresponding computer program product, as well as a method for accessing data in the geometric array, are also disclosed.

Abstract: A method, system and computer program product are provided for implementing memory migration of large system memory pages in a computer system. A large page to be migrated from a current location to a target location is converted into a plurality of smaller subpages for a processor or system page table. The migrated page is divided into first, second and third segments, each segment composed of the smaller subpages and each respective segment changes as each individual subpage is migrated. CPU and I/O accesses to respective subpages of the first segment are directed to corresponding subpages of the target page or new page. I/O accesses to respective subpages of the second segment use a dual write mode targeting corresponding subpages of both the current page and the target page. CPU and I/O accesses to the subpages of the third segment access the corresponding subpages of the current page.

Abstract: A memory management table processing method for storing a plurality of entries belonging to a plurality of memory management tables into a buffer memory of a memory storage apparatus is provided, wherein each of the entries has at least one invalid bit. The present method includes following steps. An area corresponding to each of the memory management tables is configured in the buffer memory. Invalid bit information corresponding to each of the memory management tables is recorded. The invalid bit in each of the entries is removed according to the invalid bit information corresponding to each of the memory management tables, so as to generate a valid data stream corresponding to each of the entries. Each of the valid data streams is written into the corresponding area in the buffer memory. Accordingly, the storage space of the buffer memory can be efficiently utilized.

Abstract: A management system detects a peak time period during which accesses are concentrated on a logical page included in a logical volume, and reallocates this logical page to an appropriate physical page. A management server detects an access variation of each logical volume, and selects a volume with a large access variation as a target volume. The management server measures the access status of each logical page in the target volume, and allocates a logical page to a more appropriate physical page.

Abstract: A parallel computer including compute nodes, each including two reduction processing cores, a network write processing core, and a network read processing core, each processing core assigned an input buffer. Copying, in interleaved chunks by the reduction processing cores, contents of the reduction processing cores' input buffers to an interleaved buffer in shared memory; copying, by one of the reduction processing cores, contents of the network write processing core's input buffer to shared memory; copying, by another of the reduction processing cores, contents of the network read processing core's input buffer to shared memory; and locally reducing in parallel by the reduction processing cores: the contents of the reduction processing core's input buffer; every other interleaved chunk of the interleaved buffer; the copied contents of the network write processing core's input buffer; and the copied contents of the network read processing core's input buffer.

Abstract: Systems and methods are provided for unmapping unused logical addresses at mount-time of a file system. An electronic device, which includes a non-volatile memory (“NVM”), may implement a file system that, at mount-time of the NVM, identifies all of the logical addresses associated with the NVM that are unallocated. The file system may then pass this information on to a NVM manager, such as in one or more unmap requests. This can ensure that the NVM manager does not maintain data associated with a logical address that is no longer needed by the file system.

Abstract: A method and a storage system are provided for implementing indirection tables and providing enhanced updates of the indirection tables for persistent media or disk drives, such as shingled perpendicular magnetic recording (SMR) indirection tables. A plurality of memory pools are used to store indirection data. An exception pointer table provides a pointer to an exception list for an I-Track. The exception list includes predetermined-size exception entries sorted by an offset from a start of the I-Track. An insert exception entry is provided for a new host write and merged to an updated exception list using an offset of the insert exception entry.

Abstract: The present disclosure includes methods and devices for memory block selection. In one or more embodiments, a memory controller includes control circuitry coupled to one or more memory devices having multiple Groups of planes associated therewith, each Group including at least two planes of physical blocks organized into Super Blocks, with each Super Block including a physical block from each of the at least two planes. The control circuitry is configured to receive a first unassigned logical block address (LBA) associated with a write operation and determine a particular free Super Block within a selected one of the multiple Groups to receive data associated with the write operation.

Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.

Abstract: Described embodiments provide tracking and processing of commands received by a storage device. For each received command, the storage device determines one or more requested logical block addresses (LBAs), including a starting LBA and a length of one or more LBAs of the received command. The storage device determines whether command reordering is restricted. If command reordering is not restricted, the storage device processes the received commands. Otherwise, if command reordering is restricted, the storage device conflict checks each received command. If no conflict is detected, the storage device tracks and processes the received command. Otherwise, if a conflict is detected, the storage device queues the received command.

Abstract: A method, apparatus and algorithm for quickly detecting an address match in a deeply pipelined processor design in a manner that may be implemented using a minimum of physical space in the critical area of the processor. The address comparison is split into two parts. The first part is a fast, partial address match comparator system. The second part is a slower, full address match comparator system. If a partial match between a requested address and a registry address is detected, then execution of the program or set of instructions requesting the address is temporarily suspended while a full address match check is performed. If the full address match check results in a full match between the requested address and a registry address, then the program or set of instructions is interrupted and stopped. Otherwise, the program or set of instructions continues execution.

Abstract: Examples are disclosed for allocating a block of persistent storage or accessing a block of persistent storage based on a storage service string that includes a universally unique identifier and associated metadata.

Abstract: An approach is provided in a hypervised computer system where a page table request is at an operating system running in the hypervised computer system. The operating system determines whether the page table request requires the hypervisor to process. If the determination reveals that the page table request requires the hypervisor, then the hypervisor is used to handle the request. However, if the determination reveals that the page table request does not require the hypervisor, then an indicator included in a page table entry corresponding to the request is read to determine if the page table entry is controlled by the operating system or the hypervisor. The operating system is able to update the page table entry if the indicator identifies the page table entry as being operating system controlled.

Abstract: Described embodiments provide reconstruction of logical-to-physical address mapping data for one or more sectors of a storage device at startup of a media controller. The sectors of the storage device are organized into blocks and superblocks and the address mapping data is stored in a volatile memory. At a startup condition of the media controller, a buffer layer module of the media controller allocates space in the volatile memory for one or more logical-to-physical address mapping data structures. A media layer module of the media controller determines a block type of each block of the storage device and places each block of the storage device into corresponding groups based on the determined block type of each block. The one or more blocks of each group are processed, and one or more address mapping data structures for the storage device are constructed in the allocated space in the volatile memory.

Abstract: A memory component or subsystem is provided. The memory comprises one or more memory devices and one or more write controllers within each of the one or more memory devices that each controls memory-device components to write input data values into a plurality of memory cells within a memory device that represents a unit of stored data addressed by a logical-address-space address, the write controller applying a current to the plurality of memory cells during a WRITE operation with a magnitude that corresponds to a retention value associated with the logical-address-space address.

Abstract: A data processing system includes a main storage, an input/output memory management unit (IOMMU) coupled to the main storage, a peripheral component interconnect (PCI) device coupled to the IOMMU, and a mapper. The system is configured to allocate an amount of physical memory in the main storage and the IOMMU is configured to provide access to the main storage and to map a PCI address from the PCI device to a physical memory address within the main storage. The mapper is configured to perform a mapping between the allocated amount of physical memory of the main storage and a contiguous PCI address space. The IOMMU is further configured to translate PCI addresses of the contiguous PCI address space to the physical memory address within the main storage.

Abstract: Storage management systems and methods are presented. In one embodiment, a storage management method comprises: establishing a cluster including one or more logical unit number storage components (LUNs) communicatively coupled to one or more host nodes, wherein one of the one or more nodes is a master host node; performing a LUN naming process wherein a master host node assigns a name to each of the one or more LUNs respectively, even if the one or more LUNS are communicatively coupled to a slave host node; and operating the cluster, wherein the one or more host nodes refer to the one or more LUNs by the name. In one embodiment, the master host node stores information associated with the name in a computer readable medium. The cluster can include one or more slave host nodes.

Abstract: Disclosed is an apparatus to reduce broadcasts in multiprocessors including a plurality of processors; a plurality of memory caches associated with the processors; a plurality of translation lookaside buffers (TLBs) associated with the processors; and a physical memory shared with the processors memory caches and TLBs; wherein each TLB includes a plurality of entries for translation of a page of addresses from virtual memory to physical memory, each TLB entry having page characterization information indicating whether the page is private to one processor or shared with more than one processor. Also disclosed is a computer program product and method to reduce broadcasts in multiprocessors.

Abstract: At least first nodes and second nodes of a decision tree are stored within a memory of an information handling system. The first nodes include a first parent node and first remaining nodes that descend from the first parent node. The second nodes include a second parent node and second remaining nodes that descend from the second parent node. The first nodes are grouped into a first packed node stored in first physically contiguous locations of the memory. The first nodes are sequenced in the first physically contiguous locations according to respective depth levels of the first nodes within the decision tree. The second nodes are grouped into a second packed node stored in second physically contiguous locations of the memory. The second nodes are sequenced in the second physically contiguous locations according to respective depth levels of the second nodes within the decision tree.

Abstract: A storage device and method for updating data stored in a partition of the storage device are provided. In one embodiment, a storage device is provided that contains a logical-to-physical address map and a memory with a first partition storing original data and a second partition. The storage device receives from a host device (i) a command to write updated data to a first logical address and (ii) a signature for verifying integrity of the updated data, wherein the first logical address is mapped to a physical address of the first partition. The storage device then stores the updated data in the second partition instead of the first partition and attempts to verify the signature of the updated data. If the attempt to verify the signature is successful, the storage device updates the logical-to-physical address map to map the first logical address to a physical address of the second partition.

Abstract: A data storage method includes identifying, in a set of data items associated with respective logical addresses for storage in a memory, a first subset of the logical addresses associated with the data items containing application data, and a second subset of the logical addresses associated with the data items containing parity information that has been calculated over the application data. The data items associated with the first identified subset are stored in one or more first physical memory areas of the memory, and the data items associated with the second identified subset are stored in one or more second physical memory areas of the memory, different from the first physical memory areas. A memory management task is performed independently in the first physical memory areas and in the second physical memory areas.

Abstract: According to one embodiment, an information processor includes an operator and an address protector. The address protector includes a register access interface, an address table, and an access determination module. The register access interface is configured to receive address protection information from the operator. The address table is configured to store the received address protection information. The access determination module is configured to determine whether an access to an address specified by the operator is allowable based on the address protection information, and configured to output an interrupt signal to the operator when the access is unallowable.

Abstract: In one embodiment, a processor includes a first cache and a second cache, a first core associated with the first cache and a second core associated with the second cache. The caches are of asymmetric sizes, and a scheduler can intelligently schedule threads to the cores based at least in part on awareness of this asymmetry and resulting cache performance information obtained during a training phase of at least one of the threads.

Abstract: A system and method for maintaining a pagefile of a computer system using a technique of reserving portions of the pagefile for related memory pages. Pages near one another in a virtual memory space often store related information and it is therefore beneficial to ensure that they are stored near each other in the pagefile. This increases the speed of reading data out of the pagefile because total seek time of a disk drive that stores the pagefile may decrease when adjacent pages in a virtual memory address space are read back from the disk drive. By implementing a reservation system that allows related pages to be stored adjacent to one another, the efficiency of memory management to of the computer system is increased.

Abstract: A system and method for controlling a memory card are provided. The system may include a memory card and a host. The memory card may have a plurality of data transceiving channels, and the host may selectively activate the data transceiving channels in the memory card and transmit a plurality of commands to the activated data transceiving channels.

Abstract: The invention relates to retrieving data from a storage system. One embodiment of the invention comprises receiving a write operation, establishing a correspondence relationship between a logic block address and a physical block address of the write operation, and determining whether a valid data percentage in a mapping table is greater than a predetermined threshold after the correspondence relationship is added in stored metadata. In response to the valid data percentage being less than the predetermined threshold, the embodiment adds the correspondence relationship to a B-tree data structure of stored metadata.

Abstract: A 3D stacked processor device is described which includes a processor chip and a stacked polymorphic DRAM memory chip connected to the processor chip through a plurality of through-silicon-via structures, where the stacked DRAM memory chip includes a memory with an adjustable memory portion and an adjustable cache portion such that memory can operate simultaneously in both memory and cache modes.

Abstract: An address decoding device may include a supply terminal for a supply voltage, a conductive path configured to provide an electric signal, associated with an address of at least one memory cell, and an address terminal connected to the conductive path and structured to receive the electric signal. An address decoder may be connected to the address terminal to receive the electric signal. The decoder may have a decoding operative voltage associated therewith. A switch circuit may be structured to electrically connect the address terminal to the supply terminal when the address terminal takes a threshold voltage imposed by the electric signal, and may bring the address terminal to the decoding operative voltage.

Abstract: A data preservation function is provided which, in one embodiment, includes mapping in a plurality of maps for a target storage device, map extent ranges of each map, to corresponding target extent ranges of storage locations on the target storage device. Usage of a particular map extent range by a relationship between a source extent range of storage locations on a source storage device containing data to be preserved in the source extent range, and the target extent range mapped to the map particular extent range, may be indicated by the map. In another aspect, in response to receipt of a data preservation command, a data preservation operation is performed including determining whether a map indicates availability of a map extent range mapped to the identified target extent range.

Abstract: Embodiments of the present invention address deficiencies of the art in respect to nested transaction rollback and provide a method, system and computer program product for dynamic nest level determination for nested transaction rollback. In an embodiment of the invention, a nested transaction rollback method can be provided. The method can include detecting a violation of a block of memory accessed within a set of nested transactions, retrieving a tentative rollback level for the violation, discarding a speculative state for the block of memory at each level of the set of nested transactions up to and including the tentative rollback level, refining the tentative rollback level to a lower level in the set of nested transactions, and additionally discarding a speculative state for the block of memory at additional levels in the set of nested transactions up to and including the refined rollback level.

Abstract: A method includes generating, from a representation of a first integrated circuit, a representation of a second integrated circuit. The representation of the first integrated circuit includes a plurality of representations of operative memory channel interfaces including a representation of a first operative memory channel physical interface. The representation of the second integrated circuit includes a representation of a pseudo-memory channel physical interface and at least a representation of a second operative memory channel physical interface. The generating includes replacing an instantiation of a first circuit of the representation of the first operative memory channel physical interface with an instantiation of a second circuit. The instantiation of the second circuit is a representation of a circuit that is logically equivalent to a first circuit represented by the instantiation of the first circuit.

Abstract: Methods, systems, and products are provided that display memory statistics for a keydrive that do not require the keydrive to be plugged into another device. Displaying memory statistics according to embodiments of the present invention include receiving a command resulting in a change to the memory usage of the keydrive, calculating memory statistics describing the current state of memory usage of the keydrive, storing the memory statistics in memory on the keydrive, and displaying the memory statistics on a display on the keydrive. Calculating memory statistics describing the current state of memory usage of the keydrive may be carried out by calculating a total memory usage of the keydrive. Calculating memory statistics describing the current state of memory usage of the keydrive may also be carried out by calculating a percent of total memory used.

Abstract: A memory controller that controls data transfer between a volatile memory and a non-volatile memory, wherein data being held in a plurality of volatile memories each having a refresh operation mode and a self-refresh operation mode is transferred to the non-volatile memory. When readout of data from at least one volatile memory has been finished, the volatile memory is shifted from the refresh operation mode to the self-refresh operation mode. Then, control is performed so as to return the volatile memory from the self-refresh operation mode depending on the progress of writing of data to the non-volatile memory.

Abstract: An interface for a dynamic random access memory (DRAM) includes an interface element coupled to a DRAM chip using a first attachment structure, a first portion of the first attachment structure being used to form a wide bandwidth, low speed, parallel interface, a second portion of the first attachment structure, a routing element and a through silicon via (TSV) associated with the DRAM chip being used to form a narrow bandwidth, high speed, serial interface, the interface element configured to convert parallel information to serial information and configured to convert serial information to parallel information.

Abstract: Memory mapping in small units using a segment and subsegments is described, and thus it is possible to control a memory access even using a small amount of hardware, and it is possible to reduce costs incurred by hardware. Additionally, it is possible to prevent a memory from being destroyed due to a task error in the multi-processor system.

Abstract: The present disclosure includes systems and techniques relating to non-volatile memory. A described system, for example, includes a non-volatile memory structure having a plurality of multi-level memory cells, a processing device, and a controller. The controller is configured to map a first portion of a first set of consecutive bits of a data segment to a first page associated with the plurality of multi-level memory cells, and map a second portion of the first set of consecutive bits of the data segment to a second page associated with the plurality of multi-level memory cells. The first page is associated with bits of a first significance, and the second page is associated with bits of a second significance.

Abstract: A microprocessor system having a microprocessor and a double data rate memory device having separate groups of external pins adapted to receive addressing, data, and control information and a memory controller adapted to set a burst type of the double data rate memory to interleaved or sequential by sending a signal through one of the external pins of the double data rate memory device, such that when a read command is sent by the controller, depending on the burst type set, the double data rate memory device returns interleaved or sequentially output data to the memory controller.

Abstract: A memory package and methods for writing data to and reading data from the memory package are presented. The memory package includes a volatile memory and a high-density memory. Data is written to the memory package at a bandwidth and latency associated with the volatile memory. A directory map associates a volatile memory address with data in the high-density memory. A copy of the directory map is stored in the high-density memory. The methods allow writing to and reading from the memory package using a first memory read/write interface (e.g. DRAM interface, etc.), though data is stored in a device of a different memory type (e.g. FLASH, etc.).

Abstract: The described embodiments provide a processor that executes a vector instruction. In the described embodiments, while executing instructions, the processor encounters a vector memory-accessing instruction that performs a memory operation for a set of elements in the memory-accessing instruction. In these embodiments, if an optional predicate vector is received, for each element in the memory-accessing instruction for which a corresponding element of the predicate vector is active, otherwise, for each element in the memory-accessing instruction, upon determining that addresses in the elements are likely to be arranged in a predetermined pattern, the processor predicts that the addresses in the elements are arranged in the predetermined pattern. The processor then performs a fast version of the memory operation corresponding to the predetermined pattern.

Abstract: A method has generating an access address information file from an access-destination address list including addresses of access destinations accessed by a program and access types indicating whether write access or read access is made to the individual addresses, generating a configuration-map constraint information file that includes the plurality of address ranges being included in a memory map that includes access attributes indicating whether read access or write access is permitted in the individual memory areas of the target apparatus, a page ID serving as identification information of the certain address range represented by the page and a constraint represented by an access attribute of the page, and inspecting, for each page ID, whether or not the access type for the page ID included in the access address information file contradicts the constraint represented by the access attribute for the page ID included in the configuration-map constraint information file.

Abstract: Systems for generating an identifying response pattern comprising a memory (120) used as a physically unclonable function configured for generating a response pattern dependent on physical, at least partially random characteristics of said memory may be vulnerable to freezing attacks and to aging. A memory-overwriting device (110) configured for overwriting at least a first portion of the plurality of memory locations to obscure the response pattern in the memory avoids freezing attacks. An anti-degradation device (160) configured to write to each respective location of a second portion of the plurality of memory locations an inverse of a response previously read from the memory reduces the effects of aging.

Abstract: Disclosed are techniques for allowing an increase in topology size of a serial attached SCSI expander network, as well as limiting entries in content addressable memory that are used to store address locations relating to the system topology. In accordance with one method, addresses are provided in the OAF request to reduce lookup table entries. In accordance with another embodiment, address ranges are provided in the lookup table. In addition, virtual memory techniques are used, so that either a software lookup process can be used, or a hardware process can be used, so that only the most recently used addresses are stored in the lookup table.

Abstract: Recording capacity per layer is detected from a disc and bit allocation of wobble addresses in a conventional optical disc and bit allocation in a high-density optical disc are controlled selectively to detect physical position addresses on the disc. Address detection can be performed for two kinds of discs which are equal in structure of addresses embedded in wobbles but different in bit allocation of addresses.

Abstract: In an embodiment, an address watch is established on a memory address while the execution of a first thread of a program is halted. In response to a second thread modifying memory contents at the memory address, encountering the address watch and halting, a determination is made whether a first variable in the program that represents the memory address is displayed on a user interface for the first thread. If the first variable in the program that represents the memory address is displayed on the user interface for the first thread, the value of the first variable is read and displayed on the user interface of the first thread.