Particular Access Structure Patents (Class 714/27)
  • Patent number: 7849362
    Abstract: A method and system comprises creating a test case that is dependent upon known sequences and executing the test case on an originating processor until it reaches a known point. The method further includes executing the test case on a different processor to perform an action and informing the originating processor that the action was taken. The action is verified as being occurred with the originating processor.
    Type: Grant
    Filed: December 9, 2005
    Date of Patent: December 7, 2010
    Assignee: International Business Machines Corporation
    Inventors: Robert J. Devins, David W. Milton, Pascal A. Nsame
  • Patent number: 7843807
    Abstract: Mesh access point fault reporting. In particular implementations, a method includes receiving a fault indication indicating one or more failures; collecting fault data related to the one or more failures or a state of the mesh access point; and passing the fault data to the RFID tag, which wirelessly transmits messages relating to the fault.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: November 30, 2010
    Assignee: Cisco Technology, Inc.
    Inventor: Allan Thomson
  • Patent number: 7840843
    Abstract: A testing system for an embedded system is provided. The testing system includes a plurality of devices and one or more host computers. Each device, which includes the embedded system to be tested, is connected to the host computer via a network based on the network file system protocol. The host computers are further connected with a control server, and each of the host computers comprises a root file system. The control server is configured for providing an interface for a user to set test parameters, controlling each of the host computers to invoke a test program, thereby testing the embedded system according to the test parameters, and receiving test results of the embedded system from the host computer. A related testing method is also provided.
    Type: Grant
    Filed: August 25, 2008
    Date of Patent: November 23, 2010
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Mo-Ying Tong, Hua Dong, Xue-Wen Hong, Chiang-Chung Tang, Hong-Bo Zhao
  • Patent number: 7831864
    Abstract: The invention provides a method and system for persistent context-based behavior injection in a computing system, such as in a redundant storage system or another system having a layered or modular architecture. Behaviors that are injected can be specified to have triggering conditions, such that the behavior is not injected unless the conditions are true. Triggering conditions may include a selected ordering of conditions and a selected context for each behavior. In a system having a layered architecture, behavior injection might be used to evaluate correct responses in the face of cascaded errors in a specific context or thread, other errors that are related by context, concurrent errors, or multiple errors. Behavior injection uses non-volatile memory to preserve persistence of filter context information across possible system errors, for reporting of the results of behavior injection, and to preserve information across recovery from system errors. Multiple behavior injection threads are also provided.
    Type: Grant
    Filed: May 19, 2008
    Date of Patent: November 9, 2010
    Assignee: Network Appliance, Inc.
    Inventors: Scott Schoenthal, Srinivasan Viswanathan
  • Publication number: 20100275061
    Abstract: An agent server for remotely testing an electronic device is connected to the electronic device via a control interface. The control interface includes a direct power supply and a keyboard test device. The agent server receives test requirements sent from a client via a network, supplies power to a dummy of the electronic device using the direct power supply, so as to start up the electronic device. Furthermore, the agent server operates a keyboard of the electronic device according to the test requirements using the keyboard test device, so as to establish a communication between the electronic device and another electronic device. A video camera captures video and audio information of the electronic device during the communication, and transmits the video and audio information to the client. The client analyzes the video and audio information to determine a test result of the electronic device.
    Type: Application
    Filed: September 22, 2009
    Publication date: October 28, 2010
    Applicant: CHI MEI COMMUNICATION SYSTEMS, INC.
    Inventor: CHIEN-HUNG LEE
  • Publication number: 20100268990
    Abstract: Complex on-chip interconnect fabrics, particularly those that include point-to-point interconnects and coherent routing networks, can present significant challenges for conventional trace techniques that may be applied in an effort to efficiently provide an external debugger with visibility into on-chip interconnect transactions. Embodiments described herein generate and supply separate in-circuit-trace messages including address messages and data messages, which are sent out (i.e., off-chip) to external debug tools generally without delay and coincident with the distinct, but related, trace events within address and data paths of the interconnect fabric. These separate message instances embed appropriate tag and mark values to allow the message instances to be post-processed and correlated by the external debug tools so as to reconstruct the transaction information for operations performed in the on-chip interconnect.
    Type: Application
    Filed: April 21, 2009
    Publication date: October 21, 2010
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Zheng Xu, Sanjay Deshpande, Michael Snyder
  • Patent number: 7818619
    Abstract: A test system includes a debugging system and a system under test (SUT). The debugging system includes a debugging processor that couples to an SUT processor in the SUT via a memory mapping interface bus therebetween. In one embodiment, the debugging processor operates as a master to conduct test operations on the SUT via the memory mapping interface bus. The debugging processor and the SUT processor operate together in a cluster mode to provide non-invasive debugging of the (SUT) while the SUT executes application software in a real time environment.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: October 19, 2010
    Assignee: International Business Machines Corporation
    Inventor: Steven Joseph Smolski
  • Publication number: 20100251021
    Abstract: A method and a micro telecom computing architecture (MicroTCA) system for expanding MicroTCA are provided. On a backplane of a MicroTCA system, an advanced mezzanine card (AMC) connector and a joint test action group (JTAG) testing unit connector are set into at least one AMC slot. Setting the JTAG testing unit connector by using the existing AMC slot prevents occupying exclusive backplane space by setting another JTAG slot, and thus saves backplane space. Furthermore, after the test is completed, an AMC can be plugged in and the normal use of the AMC is not affected.
    Type: Application
    Filed: June 10, 2010
    Publication date: September 30, 2010
    Inventors: Shanfu Li, Feng Hong, Cheng Chen, Longji Rao
  • Patent number: 7802139
    Abstract: A method and apparatus for providing intelligent error messaging is disclosed wherein a user of a mobile communications device is provided with descriptive error messaging information to assist the user in overcoming errors associated with the processing of electronic messages and data. For example, when the mobile device is being used to decrypt a cryptographically secured electronic message, and a problem is encountered, program logic of the device provides the user with (1) an indication of exactly what problem is preventing opening of the message, for example, a required cryptographic key is not available; (2) an indication of exactly what may be done to overcome the problem, for example, what utilities should be run on the device; and (3) exactly what data, if any, needs to be downloaded to the device, for example, what cryptographic keys should be downloaded.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: September 21, 2010
    Assignee: Research In Motion Limited
    Inventors: Neil P. Adams, Michael S. Brown, Herbert A. Little, Michael G. Kirkup, Michael K. Brown
  • Patent number: 7802140
    Abstract: A diagnostic program includes a first software module that diagnoses a diagnostic object test module; a plurality of second software modules respectively corresponding to the type of the non-diagnostic object test module, and controlling the non-diagnostic object test module to receive a signal for diagnosis output by the diagnostic object test module or to output a signal for diagnosis to the diagnostic object test module; a third software module specifying the second software module that corresponds to the type of the non-diagnostic object test module, in response to a call received from said first software module which instructs said third software module to receive the signal for diagnosis from or send the signal for diagnosis to the non-diagnostic object test module; and a fourth software module which calls the second software module specified by said third software module, and causes the signal for diagnosis to be input or output.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: September 21, 2010
    Assignee: Advantest Corporation
    Inventor: Satoshi Iwamoto
  • Patent number: 7802146
    Abstract: Provided are a method and system for loading test data into execution units in a graphics card to test the execution units. Test instructions are loaded into a cache in a graphics module comprising multiple execution units coupled to the cache on a bus during a design test mode. The cache instructions are concurrently transferred to an instruction queue of each execution unit to concurrently load the cache instructions into the instruction queues of the execution units. The execution units concurrently execute the cache instructions to fetch test instructions from the cache to load into memories of the execution units and execute during the design test mode.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: September 21, 2010
    Assignee: Intel Corporation
    Inventors: Allan Wong, Ke Yin, Naveen Matam, Anthony Babella, Wing Hang Wong
  • Patent number: 7797581
    Abstract: A testing device for testing a motherboard is provided to include a server, a client terminal computer, a debug card and a receiving device. The server is connected to the client terminal computer, for inquiring test results. The debug card is attached to the motherboard, for getting test data. The receiving device connecting with the debug card transmits the test data to the server via a network. A testing method for testing a motherboard is provided to include the following steps: a debug card getting the test data from the motherboard; sending the test data to a receiving device, the receiving device transmitting the test data to a server, the server collating and analyzing the test data; and a client terminal computer inquiring test results via the server.
    Type: Grant
    Filed: August 17, 2007
    Date of Patent: September 14, 2010
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Guang-Yu Zhu, Hoi Chan, Bo-Tao Wang, Li-Chuan Qiu, Da-Hua Xiao
  • Publication number: 20100229037
    Abstract: In a network including at least two transmission paths whose bands are respectively managed, an RTT test of DTCP-IP may fail due to a relay wait time generated by the band management regardless of retrials. An objective of the present invention is to assure success of the RTT test. A master unit device (100) managing bands of the transmission paths includes an RTT test detection section (140) for detecting a failure of the RTT test, and a band management section (150) for modifying a band management (TXOP allocation) schedule based on an RTT test failure detection. With this configuration, a time band during which no TXOP is allocated is provided between the transmission paths whose bands are respectively managed, thereby assuring success of the RTT test.
    Type: Application
    Filed: January 5, 2007
    Publication date: September 9, 2010
    Inventors: Shuichi Sato, Yasuo Hamamoto
  • Publication number: 20100229038
    Abstract: In an embodiment, a system is disclosed. The system has a bus interface port, a selection circuit coupled to the bus interface port, a first bus interface circuit coupled to the selection circuit and a second bus interface circuit coupled to the selection circuit. The selection circuit is configured to select between the first bus interface circuit and the second bus interface circuit. The system also has an initialization circuit configured to detect a first codeword written to the bus interface port, and activate the second bus interface circuit if the first codeword is detected.
    Type: Application
    Filed: March 4, 2009
    Publication date: September 9, 2010
    Inventors: Albrecht Mayer, Wolfram Carl
  • Publication number: 20100229039
    Abstract: A testing apparatus includes a vector memory unit storing original test vector data in which an input signal to be inputted to a circuit subjected to inspection is described, a vector generator generating generated test vector data from the original test vector data, an output part outputting test vector data to be inputted to the inspected circuit, a fault occurrence rate memory unit storing a fault occurrence rate of the input signal, a random number generator generating random number data, and a comparison part comparing the fault occurrence rate of the input signal with the random number data. The vector output part outputs the generated test vector data when the random number data is smaller than the fault occurrence rate of the input signal, and outputs the original test vector data when the random number data is larger than the fault occurrence rate of the input signal.
    Type: Application
    Filed: February 23, 2010
    Publication date: September 9, 2010
    Applicant: Sony Corporation
    Inventor: Shinichiro Chikada
  • Publication number: 20100229040
    Abstract: A method and a device for creating a pattern matching state machine are provided. The method includes: obtaining a predefined keyword set; generating a Goto function according to the keyword set; constructing a Failure function according to the generated Goto function, and setting that an acceptable input set of the Failure state of each state is not a subset of an acceptable input set of the state, where the acceptable input set of the state indicates that when any symbol within the symbol set is input in the state, the Goto function of the state does not fail; and generating an Output function according to the Goto function and the Failure function.
    Type: Application
    Filed: May 17, 2010
    Publication date: September 9, 2010
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jian CHEN, Qikun WEI, Guohai CHEN
  • Publication number: 20100223501
    Abstract: In order to provide a recording method for data which have been or are being generated at a data source in a time sequenced manner and are transmitted via a digital network to at least one recording device for storage, by means of which method the data can be reliably recorded, it is provided that the data are stored at the data source before the transmission on the digital network in such a way that, after a fault on the digital network, data which were intended for transmission during the period of the fault can be made available to the at least one recording device.
    Type: Application
    Filed: May 7, 2010
    Publication date: September 2, 2010
    Applicant: Robert Bosch GmbH
    Inventor: Michael Gilge
  • Publication number: 20100223496
    Abstract: The disk controller has a plurality of channel control units, a plurality of cache memories, a plurality of disk control units, and a plurality of internal switch units. Each channel control unit or disk control unit sends to one of the cache memory units a request packet requesting execution of processing. The cache memory unit sends a response packet in response to the received request packet. Each internal switch unit monitors the request packet sent from the channel control unit or disk control unit, and judges whether or not the response packet to the request packet has passed through the internal switch unit within a first given time period since the passage of the request packet. In the case where the response packet has not passed through the internal switch unit within the first given time period, the internal switch unit sends a failure notification.
    Type: Application
    Filed: May 12, 2010
    Publication date: September 2, 2010
    Applicant: Hitachi, Ltd.
    Inventors: Shuji Nakamura, Akira Fujibayashi, Mutsumi Hosoya
  • Publication number: 20100223492
    Abstract: The present invention relates to a failure detection method and system operating at the session control layer, preferably within an IMS/SIP architecture, which monitors the status of an adjacent node with the aid of a timer mechanism that sets a heartbeat rate associated with that adjacent node. Monitoring of a communication session takes place by monitoring the liveliness of the nodes handling the session. According to some embodiments, SIP traffic within an on-going communication session is used to determine whether an adjacent node is alive. Failure to receive a SIP message from an adjacent node within a given heartbeat rate starts a polling process to decide whether the adjacent node is in a faulty status. In the affirmative, i.e. upon decision that the adjacent node is in a faulty status, the polling node closes the communication session so that any further billing is prevented.
    Type: Application
    Filed: January 20, 2010
    Publication date: September 2, 2010
    Inventors: Maria Farrugia, Marco Stura, Maurizio Monti
  • Patent number: 7788534
    Abstract: A stale of a managed client device in a distributed autonomic computing environment is attached to an event occurring on the managed client device. The event is sent, with the attached state of the managed client device, to a server. The state of the managed client device is saved at the server. The event is analyzed for identifying a problem at the client device. An action for solving the problem is generated based on a state of the managed client device at the time the event is analyzed. An execution condition is dynamically generated based on the saved state of the managed client device. The execution condition is added to the action to be executed and sent to the managed client device. At the managed client device, a determination is made whether to execute the action based on the execution condition and a current state of the managed client device.
    Type: Grant
    Filed: December 11, 2007
    Date of Patent: August 31, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kazuhito Akiyama, Yasutaka Nishimura, Yasuhiro Suzuki, Tadashi Tsumura
  • Patent number: 7770124
    Abstract: Functionality and corresponding procedures are described for building a management system. The management system provides description language content (such as markup language content) which describes different aspects of the management system in a declarative manner. The management system also includes generic resource content for performing various general purpose tasks that can be applied to different applications of the management system. The management system provides a specific management-related service by combining the description language content with the generic resource content. In other words, the description language content effectively tailors the generic code content to provide the management-related service. One aspect of the description language content governs a manner of populating management information to be presented by the management system. Another aspect of the description language content governs a manner of displaying the retrieved management information to a user.
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: August 3, 2010
    Assignee: Microsoft Corporation
    Inventors: Kenneth A. Argo, Jeffry B. Phillips, Jie Liu
  • Patent number: 7764695
    Abstract: A multi-chassis system includes at least a first chassis and a second chassis that each includes one or more blades. The one or more blades in turn include one or more ports. The two or more chassis are connected through use of an interconnector. The multi-chassis system may also include access to one or more microprocessors that may execute thereon software that controls the propagation of the arm condition. The arm condition is generated at a first port of a first chassis or network analyzer blade coupled to the first chassis. The arm condition is then transmitted to one or more additional ports of the first chassis while not being transmitted to any ports of the second chassis. Finally, the reception of a precondition for triggering defined by the arm condition is limited to those ports that have received the arm condition.
    Type: Grant
    Filed: September 25, 2006
    Date of Patent: July 27, 2010
    Inventors: Randy I. Oyadomari, George A. Bullis, Minh Q. Vu
  • Patent number: 7761744
    Abstract: The invention provides a debugging method applicable for an embedded system. The system includes a processor, a main memory and a debugging interface. A debugging program is first provided in the main memory. A debugging interruption is subsequently triggered to cause the processor to read the debugging program from the main memory and execute the debugging program. After execution, an execution result of the debugging program is stored into the main memory. The execution result is read and output via the debugging interface for further analysis. Because the architecture does not require a scan chain of ITR 104, the circuit requirement is reduced while performance is increased.
    Type: Grant
    Filed: May 14, 2007
    Date of Patent: July 20, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Chao-Hung Chang, Po-Chou Chen, Ming-Lun Liu
  • Patent number: 7761757
    Abstract: An apparatus for setting a test mode in a semiconductor integrated circuit includes a test mode control block that generates a coding control signal according to whether or not a control fuse is cut, and a test mode coding block that sets default values of a multi-bit test code in response to the coding control signal.
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: July 20, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Won-Joo Yun, Hyun-Woo Lee, Dong-Suk Shin
  • Patent number: 7757122
    Abstract: When a fault is detected by a surveillance agent mounted in a user device, fault information is reported to a maintenance center device by an electronic mail through an internet. The user device is provided with a connect confirmation unit to prepare and transmit connect confirmation mails of a plurality of patterns different in mail content, and the maintenance center device is provided with a diagnosis unit, which diagnose a mail transmission environment of the user device from the reception result of one or a plurality of connect confirmation mails received within a fixed period of time and transmits a diagnosis result to the user device by the electronic mail.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: July 13, 2010
    Assignee: Fujitsu Limited
    Inventors: Tomohiro Hikita, Yoshihiro Kimura, Ikuko Tachibana, Toshiaki Hayashi, Takashi Tanifuji, Keisuke Horigami, Yasutaka Tanikawa
  • Patent number: 7757123
    Abstract: Faults are managed. A problem is detected in a data storage system. Possible field replaceable units (FRUs) of the data storage system are identified that may be at fault for the problem. If only one FRU may be at fault, a definitive alert is issued identifying the FRU. If multiple FRUs may be at fault, fault isolation is executed. If fault isolation isolates the problem to only one FRU, a definitive alert is issued naming the FRU. If fault isolation does not isolate the problem to only one FRU, an ambiguous alert is issued identifying multiple FRUs. The user is directed to execute a troubleshooting tree, which execution includes a manual FRU replacement by the user.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: July 13, 2010
    Assignee: EMC Corporation
    Inventors: Morrie Gasser, Mark W. Kulacz
  • Publication number: 20100162046
    Abstract: An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.
    Type: Application
    Filed: March 4, 2010
    Publication date: June 24, 2010
    Applicant: OC APPLICATIONS RESEARCH LLC
    Inventors: Bulent Dervisoglu, Laurence H. Cooke, Vacit Arat
  • Patent number: 7743278
    Abstract: The present invention is directed to facilitate debugging in a semiconductor integrated circuit device including a plurality of microprocessors. A semiconductor integrated circuit device includes: a plurality of processors; a plurality of debug interfaces enabling debugging of the corresponding processors; a plurality of common terminals shared by the plurality of debug interfaces; a selection circuit capable of selectively connecting the plurality of debug interfaces to the common terminals; and a controller capable of controlling selecting operation in the selection circuit in accordance with a predetermined instruction. A first selector capable of selectively connecting the plurality of debug interfaces to a TRST terminal in the terminal group conformed with the JTAG specifications, and a second selector capable of selectively connecting the plurality of debug interfaces to terminals other than the TRST terminal are provided.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: June 22, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Yuri Ikeda, Yoshikazu Aoto, Jun Matsushima, Hiroyuki Sasaki, Tomoyoshi Ujii, Makoto Saen
  • Publication number: 20100146337
    Abstract: The object of the invention is in particular a method and a device for detecting non-regression of an input/output system from a remote station comprising a test tool adapted for executing a test command of the said input/output system. The said input/output system and remote station are each connected to a communication network. The method comprises transmitting (305), to the said remote station, an instruction to run the said test tool and an instruction to execute the said test command (320), as well as transmitting (315), to a recording device connected to the said communication network, an instruction to record data corresponding to the result of execution of the said command, circulating on the said communication network. After reception, the recorded datum may be analyzed (335) according to a reference datum corresponding to the expected result of execution of the said command.
    Type: Application
    Filed: December 10, 2009
    Publication date: June 10, 2010
    Applicant: Airbus Operations SAS
    Inventors: Frank DESSERTENNE, Jean Francois Copin
  • Patent number: 7734957
    Abstract: The disk controller has a plurality of channel control units, a plurality of cache memories, a plurality of disk control units, and a plurality of internal switch units. Each channel control unit or disk control unit sends to one of the cache memory units a request packet requesting execution of processing. The cache memory unit sends a response packet in response to the received request packet. Each internal switch unit monitors the request packet sent from the channel control unit or disk control unit, and judges whether or not the response packet to the request packet has passed through the internal switch unit within a first given time period since the passage of the request packet. In the case where the response packet has not passed through the internal switch unit within the first given time period, the internal switch unit sends a failure notification.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: June 8, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Shuji Nakamura, Akira Fujibayashi, Mutsumi Hosoya
  • Patent number: 7730360
    Abstract: There is provided a method of communicating diagnostic information between a Universal Serial Bus (USB) host and a USB device, the USB host including a host USB controller, a main driver and a host main application. The method comprises establishing a data pipe in a data class interface between the USB host and the USB device for data communication; establishing a diagnostic information pipe in the data class interface between the USB host and the USB device for diagnostic information communication; monitoring the data class interface between the host USB controller and the main driver using a filter driver; intercepting the diagnostic information in the diagnostic information pipe of the data class interface using the filter driver; directing the diagnostic information intercepted by the filter driver to a host diagnostics application; and directing the data in the data pipe of the data class interface to the main driver.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: June 1, 2010
    Assignee: Conexant Systems, Inc.
    Inventor: Eddie Wai
  • Patent number: 7730352
    Abstract: Techniques and technologies are provided for testing network applications without communicating over a network layer communication link. For example, in one implementation, a system for testing network applications within a process is provided which includes at least one client user instance (CUI) module configured to execute in the process, a performance testing engine module (PTEM) configured to execute in the process, and a network application module configured to execute in the process. The CUI module has state information associated therewith. The PTEM includes a Request Driver Module (RDM) which generates information requests based on the state information received from the CUI. The network application module generates responses to the information requests.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: June 1, 2010
    Assignee: Microsoft Corporation
    Inventors: Thomas L. Marquardt, Andres M. Sanabria, Dmitry Robsman
  • Patent number: 7725770
    Abstract: An apparatus for collecting failure data includes a failure data collector that initializes one or more test devices by establishing a secondary interface therewith in response to receiving a test device initialization command from a device tester, communicates one or more failure data collection requests to each test device corresponding to a failure data collection command received from the test device, and receives failure data from the test devices via the secondary interface in response to communicating the failure data collection request. In certain embodiments, the present invention includes a failure data storage repository for storing the collected failure data.
    Type: Grant
    Filed: April 1, 2007
    Date of Patent: May 25, 2010
    Assignee: International Business Machines Corporation
    Inventors: William W. Owen, Joshua M. Rhoades, Marina M. Ruíz
  • Patent number: 7721159
    Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to generating processing debug information, processing link identification information, injecting errors across communications links and performing error detection.
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: May 18, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Gregg Bernard Lesartre, John W. Bockhaus
  • Patent number: 7716527
    Abstract: A repair system is disclosed comprising: a server having a repair manager; a client device having a repair agent; and a network, wherein the server and the client device are connected to the network. The repair agent, in response to a repair signal, is operable to restrict communication of the client device on the network to the repair manager, and the repair manager is operable to provide a repair application. The repair system is enabled to correct actual or potential problems including software viruses and trojans, and spam messages. Diagnosis and repairs can be carried out in response to a deleterious detection system or through user input to the device. The repair agent requires only limited system resources and therefore it particularly applicable to mobile devices where system resources are at a premium.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: May 11, 2010
    Assignee: International Business Machines Corporation
    Inventors: Francois-Xavier Drouet, Vincent Outters
  • Publication number: 20100115336
    Abstract: A test system includes a host, a module to communicate with the host, and a test device to test the module while the module is connected to the host. The host includes a pulse width modulator circuit to supply a power to the module, and the test device varies a feedback resistance value provided to the pulse width modulator circuit.
    Type: Application
    Filed: October 30, 2009
    Publication date: May 6, 2010
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dong-Eun SHIN, Jungkuk LEE, Junjung PARK, Deogjong HWANG, Jae Chun YOU
  • Patent number: 7711993
    Abstract: A JTAG bus cross point switching device that is commanded by the same bus which it configures. In a preferred embodiment a JTAG chain includes a cross point switching device that is capable of adding, omitting, or rearranging devices on a JTAG bus. The switching device itself is controlled by commands on the JTAG bus which it configures.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: May 4, 2010
    Assignee: International Business Machines Corporation
    Inventors: Mike Conrad Duron, Robert Allan Faust, Forrest Clifton Gray, Ajay Kumar Mahajan, Glenn Rueban Miles
  • Patent number: 7702956
    Abstract: A system on chip processor, that is, a semiconductor integrated circuit in which a processor, a cache memory and the like are integrated into one chip, includes a test controller, and a trace memory. The test controller generates test control signals in response to test flag signals generated from a processor. The trace memory stores a transmission data signal between the processor and a cache memory, a device under test, in response to the test control signals. Since the trace memory is provided within the integrated circuit, an operation of the device under test, which is configured in the integrated circuit, can be tested without disassembling the integrated circuit even after the integrated circuit is completely manufactured.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: April 20, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jung-Yul Pyo
  • Patent number: 7697443
    Abstract: Locating hardware faults in a parallel computer, including defining within a tree network of the parallel computer two or more sets of non-overlapping test levels of compute nodes of the network that together include all the data communications links of the network, each non-overlapping test level comprising two or more adjacent tiers of the tree; defining test cells within each non-overlapping test level, each test cell comprising a subtree of the tree including a subtree root compute node and all descendant compute nodes of the subtree root compute node within a non-overlapping test level; performing, separately on each set of non-overlapping test levels, an uplink test on all test cells in a set of non-overlapping test levels; and performing, separately from the uplink tests and separately on each set of non-overlapping test levels, a downlink test on all test cells in a set of non-overlapping test levels.
    Type: Grant
    Filed: April 13, 2006
    Date of Patent: April 13, 2010
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Archer, Mark G. Megerian, Joseph D. Ratterman, Brian E. Smith
  • Publication number: 20100083045
    Abstract: Methods and apparatus to perform quality testing in Internet Protocol (IP) Multimedia subsystem (IMS) based communication systems are disclosed. An example IMS-based system comprises a web portal to allow a user to configure quality testing for a user endpoint and to present results of the quality testing, a test server to exchange packets with the user endpoint to perform the testing, an IMS application server to implement a state machine to establish a test session between the test server and a test module of the user endpoint, the packets to be exchanged between the test server and the test module via the session, and a data analyzer to determine one or more parameters representative of performance of the session based on the exchanged packets, and to provide the same to the web portal, the web portal to present information representative of the one or more parameters to the user.
    Type: Application
    Filed: September 29, 2008
    Publication date: April 1, 2010
    Inventors: Chaoxin Qiu, Alexander Lisheng Huang, Michael Taylor
  • Patent number: 7689857
    Abstract: A method and apparatus for managing data, voice, application, and video services allows anticipation of poor quality of service from a remote management station, in order to allow correction of the cause before the end user perceives service quality degradation. Specific system phenomena are identified that coincide with user-perceived service degradation in a particular network. The network is then monitored for the occurrence of those phenomena. Incipient or existing user-perceived quality of service degradation is inferred from the occurrence of one or more of those phenomena and action is taken to avoid and/or correct the degraded service quality condition. In a preferred embodiment, as many of the steps as possible are performed automatically by a network management system. In one embodiment, a close correlation is assumed between application data buffer over-extension and poor quality of service from a user's point of view.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: March 30, 2010
    Assignee: Computer Associates Think, Inc.
    Inventor: Lundy M. Lewis
  • Patent number: 7681080
    Abstract: A diagnostic system and method for repairing computing devices comprises a diagnostic application running on a same computing system having a failed operating system (O/S). The diagnostic application is provided with access to the file system of the failed O/S image. The diagnostic software application collects relevant configuration information from the file system of the failed O/S image, and transports this information to a proxy system running the same operating system as the computing device being diagnosed. The proxy system utilizes the collected data to diagnose the subject failed O/S system. Once the proxy makes a determination it synthesizes repair information comprising new or modified files and instructions to be transported back to the diagnostic software system to apply. A network connection is provided between the computer running the diagnostic application and the proxy system that enables data to be easily transported between the two systems without human intervention.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: March 16, 2010
    Assignee: International Business Machines Corporation
    Inventors: Bulent Abali, Robert A. Saccone, Jr.
  • Patent number: 7676696
    Abstract: A functional unit for carrying out logical test cases on a test system interconnected to a unit that is to be tested, the functional unit being suitable for being interconnected between the logical test cases and the test system in such a way that the logical test cases are decoupled from the test system, and, in this context, for supporting an execution of the logical test cases on the test system as mediator.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: March 9, 2010
    Assignee: Robert Bosch GmbH
    Inventors: Gerald Holzapfel, Gerhard Filp, Hakan Oezaslan, Frank Traenkle, Juergen Meyer, Tilo Allmendinger, Uwe Gross, Alexander Bayerl, Sven Goebel, Bernd Kretschmer, Klaus Lebert, Ulrich Wolters
  • Patent number: 7676035
    Abstract: The solution described herein provides an innovative use of remote services technology integrated with service personnel onsite at the point of service, such as a consumer repair outlet, to provide a pool of technical support resources to service a widely distributed resource need, such as support and repair resource needs of a chain of consumer outlets or an aggregated group of single proprietor consumer outlets. With this solution, qualified technical resources are provided from a central location to service a widely distributed retail environment. This is on-demand online remote support service is called or referred to as “support from a spigot.” The distribution method enables the delivery of higher quality, more reliable and overall lower cost services. Instead of requiring dedicated technical resources at each location, lower skilled labor may be deployed at the location to enable the remote technical support services process.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: March 9, 2010
    Assignee: PlumChoice, Inc.
    Inventors: Theodore Werth, Richard T. Surace, II
  • Publication number: 20100042874
    Abstract: The same testing equipment can be used to test devices operating under different protocols. Where the testing protocol is slower than the native serial protocol of the high-speed serial link connecting the device processor to the component to be tested, the link may be adapted to carry the lower speed testing protocol. This may be accomplished by adding low-speed buffers to the circuits of the serial link, or the serial link may have a native low-speed protocol in addition to its high-speed protocol connections may be made to the pathways for the native low-speed protocol, or the testing protocol may be impressed on top of native low-speed protocol. Where the driver of the device being tested has limited number of pins, the test mode can be controlled by applying power to different power supply input pins.
    Type: Application
    Filed: September 29, 2008
    Publication date: February 18, 2010
    Applicant: APPLE INC.
    Inventor: Yongman Lee
  • Patent number: 7664986
    Abstract: A system and method for determining fault isolation in an enterprise computing system is disclosed. A method includes automatically troubleshooting errors in an enterprise computing system that receives at an analyzer engine a status notification from a first component. In response to receiving the status notification, the method automatically selects a first analyzer policy file from a set of analyzer policy files based on the status notification received at the analyzer engine, wherein the analyzer policy file contains troubleshooting logic for determining root causes for errors. The method automatically attempts to communicate with a second component based on the troubleshooting logic within the first analyzer policy file. The method automatically determines a root cause for the status notification based on the troubleshooting logic in the selected analyzer policy file and based on information obtained in connection with the attempt to communicate with the second component.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: February 16, 2010
    Assignee: Dell Products L.P.
    Inventors: Karthikeyan Angamuthu, Robert V. Cox, Stephanos S. Heracleous
  • Patent number: 7661030
    Abstract: A system is disclosed for obtaining debug information in a network that supports Web services. The system includes a first service host to send a first message, where the first message contains data corresponding to a request for debug information. The system also includes a second service host to receive the first message and to send a second message to a third service host in response to the first message, where the second message contains data corresponding to a request for debug information. The second service host receives a reply to the second message from the third service host, where the reply to the second message includes third debug information associated with the third service host, and the second service host generates a reply to the first message. The reply to the first message includes the third debug information and second debug information associated with the second service host.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: February 9, 2010
    Assignee: SAP AG
    Inventors: Erol Bozak, Alexander Gebhart
  • Patent number: 7657789
    Abstract: An integrated test framework is disclosed that allows software testers to easily generate and execute tests of software involving multiple interacting computer systems. A copy of the integrated test framework resides on each computer system in the test. The integrated test framework on each computer system supports the independent testing of software on that system and also the synchronization between the computer systems. A test manager is provided to coordinate the synchronization. All the information necessary to direct the test framework on each of the computer systems is included within a single test script that is propagated to and executed on each computer system. The test script dictates the role of each computer system within the test and includes role specific actions and identifies points at which the computer systems must synchronize together for the passing of data, messages or other communications.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: February 2, 2010
    Assignee: Microsoft Corporation
    Inventors: Peter Gerber, Jing Tan, Michael Robinson
  • Patent number: 7657790
    Abstract: Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: February 2, 2010
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 7652444
    Abstract: An actuator (10) includes sensors (12) which are used to detect variables representing the operating state of the actuator (10) and are connected to an evaluation unit (16) associated with the actuator (10). The evaluation unit (16) is connected to sensors (12) and/or control actuating elements (13) by means of a first data bus (15). The sensors (12) are used to detect measurable variables representing the operating state of the actuator (10), and to transmit the same to the evaluation unit (16).
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: January 26, 2010
    Assignee: Siemens Aktiengesellschaft
    Inventors: Winfried Kessler, Alexander Wagenpfeil