Abstract: Embodiments of apparatus, computer-implemented methods, systems, devices, and computer-readable media are described herein for a computing device with a platform entity such as an interrupt handier configured to notify an operating system or virtual machine monitor executing on the computing device of an input/output error-containment event. In various embodiments, the interrupt handler may be configured to facilitate recovery of a link to an input/output device that caused the input/output error-containment event, responsive to a directive from the operating system or virtual machine monitor.

Abstract: A method and an apparatus for processing an asynchronous audio stream are provided. A corrupted PES packet is detected from an asynchronous audio PES stream, and the ADTS frames of the corrupted PES packet are detected and replaced with predetermined substitute ADTS frames. Thus, an AAC stream is restored from the PES stream.

Abstract: Method or apparatus for passive process monitoring is described. One aspect of the invention relates to monitoring a process executing on a computer system. An operating system is instructed to report at least one event related to process termination. Termination of the process is detected in response to a reported instance of the at least one event by the operating system. A notification is provided to an agent in the computer system that the process has terminated.

Abstract: A portable electronic device includes a storage unit in which information indicating correct process contents is stored. A reception unit of the portable electronic device receives a command for requesting a process from an external device, and the portable electronic device determines whether or not process contents to be executed according to the received command are matched with process contents stored in the storage unit. When it is determined that process contents according to the received command are matched with process contents stored in the storage unit, the portable electronic device executes a process according to the command received by the reception unit.

Abstract: An information processing apparatus connected to an inputting/outputting apparatus includes a storage apparatus configured to store data, a calculation processing apparatus configured to issue an order, and a data forwarding apparatus configured to generate, upon receiving a data forwarding order issued by the calculation processing apparatus, based on data stored by the storage apparatus, first error inspection data to detect an error of the data, forward the data and the first error inspection data to the inputting/outputting apparatus, generate, upon receiving an data inspection order issued by the calculating processing apparatus, based on data stored by the storage apparatus, second error inspection data to detect an error of the data, and report occurrence of an error to the calculation processing apparatus, when a result of comparison of the first error inspection data generated by another data forwarding apparatus and the second error inspection detail is a mismatch.

Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to read or write performance of a phase change memory.

Abstract: Control over servers and partitions within a computer network may be automated to improve response to disaster events within the computer network. For example, a monitoring server may be configured to automatically monitor servers through remote communications sessions. A disaster event may be detected based on information received from the partitions and servers within the network. When a disaster event or events leading to a disaster event are detected, a trouble ticket may be generated. The trouble ticket may also generate an alert displayed to an administrator through a customized hierarchical graphical display. When the administrator is not logged in, messages may be generated to alert the administrator to the problem. The administrator may then log in remotely and respond to the alert.

Abstract: A method and system for detecting abnormal interleavings in a multi-threaded program includes generating an execution log in response to execution of the multi-threaded program. Based on the execution log, a list of allowable immediate interleavings is generated if the execution of the multi-threaded program resulted in no concurrency errors and a list of suspicious immediate interleavings is generated if the execution of the multi-threaded program resulted in one or more concurrency errors. The first and second lists are compared to generate a list of error-causing immediate interleavings. A replayable core is then generated and executed based on the list of error-causing immediate interleavings.

Abstract: Embodiments of an electronic circuit comprise a module, such as a security module, configured to perform cryptographic processing for a predetermined security protocol that includes random number checking. The security module is controlled by a descriptor that includes instructions that cause the security module to access a generated random number, compare the generated random number to a random number stored during a previous execution of the descriptor, and generate an error signal when the generated random number and the previous execution random number are equal.

Abstract: Systems and methods for maximizing a number of available states for a version number used for memory corruption detection. A physical memory may be a DRAM comprising a plurality of regions. Version numbers associated with data structures allocated in the physical memory may be generated so that version numbers of adjacent data structures in a virtual address space are different. A reserved set and an available set of version numbers are associated with each one of the plurality of regions. A version number in a reserved set of a given region may be in an available set of another region. The processor detects no memory corruption error in response to at least determining a version number stored in a memory location in a first region identified by a memory access operation is also in a reserved set associated with the first region.

Abstract: Files related to shipping transactions are received from participants. Each of the files are processed in a first stage of a multi-stage process that includes attempting to translate the files to generate a translated file and storing an error status for each file in which the translation experienced an error. For those files that are successfully translated, they are processed in subsequent stage(s) including applying application rule(s) to those files and storing an error status for those translated files resulting in an error. A participant may view a summary of those translated files that are associated with an error status. The participant may further view details of an error to be displayed and retrieve the underlying file. The participant may edit the file to correct the issue and republish the modified file to be reprocessed in the stage of the multi-stage process that identified the error.

Abstract: A network device for building up a network connection via a high-definition multimedia interface, includes a scrambler, a descrambler, a comparator and a control unit. The scrambler is utilized for generating a transmission signal according to a first seed. The descrambler is for decoding a receiving signal to generate a second seed. The comparator is for generating a comparing result according to the first seed and the second seed. The control unit is for controlling the network connection according to the comparing result.

Abstract: Provided is a communication system which includes a plurality of game apparatuses. Each game apparatus performs short-range wireless communication with another game apparatus among the plurality of game apparatuses. Through the short-range wireless communication, the game apparatus receives identification information of the other game apparatus (other-apparatus identification information) from the other game apparatus. The game apparatus detects the communication status of the short-range wireless communication with the other game apparatus. Based on the detection result, the game apparatus determines whether or not to register the other game apparatus which is associated with the received other-apparatus identification information. When determining to register the other game apparatus, the information processing apparatus registers the other game apparatus and performs communication with the registered other game apparatus.

Abstract: A memory device includes: volatile memory; an interface for connecting to a backup power source; non-volatile memory; a first configuration data bus for accessing parameters describing substantially permanent characteristics of the volatile memory; a second configuration data bus for accessing at least one of state of health information of the backup power source and status information of the memory device, wherein the first configuration data bus and the second configuration data bus implement a same bus protocol; a controller programmed to detect a loss of power of a primary power source and move data from the volatile memory to the non-volatile memory, wherein configuration information of the controller is at least one of readable and writable through the first configuration data bus; and wherein at least one of the state-of-health information and the status information is at least one of readable and writable through the second configuration data bus.

Abstract: An error correction apparatus comprises an input for receiving data. The received data includes error-check data. The apparatus also includes a processing resource arranged to calculate parity check data. A data store is coupled to the processing resource for storing look-up data for identifying, when in use, a location of an error in the received data. The look-up data is a compressed form of indexed error location data.

Abstract: In a method in a portable data carrier for securing the data carrier against external attacks on the data carrier, there is employed at least one counter in the data carrier. A specified command is secured here such that it is executed by the data carrier only when the at least one counter lies in a specified, permissible values range, in particular does not undershoot a specified minimum value. The at least one counter is actuated, normally decremented, according to the invention when it is recognized on the basis of a rollback buffer of the data carrier that a preceding execution of a command has been disturbed.

Abstract: The Advanced Logic System (ALS) is a complete control system architecture, based on a hardware platform rather than a software-based microprocessor system. It is significantly different from other PLC-type control system architectures, by implementing a FPGA in the central control unit. Standard FPGA logic circuits are used rather than a software-based microprocessor which eliminate problems with software based microprocessor systems, such as software common-mode failures. It provides a highly reliable system suitable for safety critical control systems, including nuclear plant protection systems. The system samples process inputs, provides for digital bus communications, applies a control logic function, and provides for controlled outputs. The architecture incorporates advanced features such as diagnostics, testability, and redundancy on multiple levels. It additionally provides significant improvements in failure detection, isolation, and mitigation for the highest level of integrity and reliability.

Abstract: In an error response circuit an analysis circuit unit analyzes a command transmitted from a first circuit section to a second circuit section, and detects a status of data transfer between the first circuit section and the second circuit section. A response circuit unit generates an error signal in accordance with the detected status of the data transfer in response to the second circuit section changing from a first power consumption state to a second power consumption state in which power consumption is lower than power consumption in the first power consumption state. A switching circuit unit transmits the error signal to the first circuit section in place of a response signal that is responsive to the command and transmitted from the second circuit section to the first circuit section.

Abstract: Native applications inherit transaction contexts when invoked by primary applications running in separate hosting environments, by: receiving, by an interface of a native application server in a first hosting environment, a unique transaction context identifier for an invocation of the native application at the native application server by the primary application at a primary application server in a second hosting environment; receiving a SQL statement from the native application by the interface of the native application server; sending the SQL statement and the unique transaction context identifier to the primary application server for execution by the interface of the native application server; receiving a result of the execution of the SQL statement and the unique transaction context identifier from the primary application server by the interface of the native application server; and sending the result to the native application by the interface of the native application server.

Abstract: A method includes receiving an error signal from a client device receiving a video stream. A portion of the video stream associated with the error signal is detected. An error selection listing based on the portion of the video stream is transmitted. The client device receives a selection based on the error selection listing. The selection is stored as an error listing.

Abstract: Storage system arrangement wherein: when a transmission destination determines that a source-side serial number included in a received packet is the same as a current destination-side serial number in the transmission destination, the transmission destination processes a content of the received packet in accordance with a command included in the received packet; and when the transmission destination determines that the source-side serial number is not the same as the current destination-side serial number, the transmission destination does not process a content of the received packet.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes: a data detector circuit, a low latency detection circuit, and an error calculation circuit. The data detector circuit is operable to perform a data detection process on a first signal derived from a data input to yield a detected output, and to provide a loop error as a difference between the detected output and the first signal. The low latency detection circuit operable to process a second signal derived from the data input to yield a fast detector output, and to provide a generated error as a difference between the fast detector output and the second signal. The error calculation circuit is operable to calculate an error value based at least in part on the generated error and the loop error.

Abstract: Embodiments relate to systems and methods for error containment in a system comprising detecting an error by processing an input signal by multiple processing units, and delaying at least one output signal of a processing unit to enable, in case an error has been detected, modifying at least one output signal of the processing unit that would cause propagation of the error through the system.

Abstract: Apparatus and methods for reducing infrastructure failure rates. The apparatus and methods may involve reduction of data complexity. The reduction may be based on the use of nonlinear analysis to derive representative variables, which may be multi-valued. Multi-valued variables may be consolidated. A model may be developed based on the values and relationships of the derived variables. The model may be applied to assess the risk involved in a prospective infrastructure change.

Abstract: A system includes one or more memory modules provided with a plurality of operation blocks having a plurality of memory elements which may be simultaneously operated. The system performs write access concurrently by writing data to two or more selected operation blocks. When a fault is detected in one of the two or more operation blocks, access is performed including the write access to two or more operation blocks excluding the operation block in which the fault is detected.

Abstract: A system and method for financial account reconciliation of a portfolio account system includes, for investments that are not reported as trades once an order to purchase has been placed, using a computer to electrically match investments that are not reported as trades to unmatched transactions of the portfolio account system. In this manner investments that are not reported as trades once an order to purchase has been placed do not create breaks of the portfolio account system.

Abstract: A pipelined processing device includes: a processor configured to receive a request to perform an operation; a plurality of processing controllers configured to receive at least one instruction associated with the operation, each of the plurality of processing controllers including a memory to store at least one instruction therein; a pipeline processor configured to receive and process the at least one instruction, the pipeline processor including shared error detection logic configured to detect a parity error in the at least one instruction as the at least one instruction is processed in a pipeline and generate an error signal; and a pipeline bus connected to each of the plurality of processing controllers and configured to communicate the error signal from the error detection logic.

Abstract: An information processing device, for executing content reproduction processing from an information recording medium, includes a security information processing unit for determining output messages based on security check information in a content reproduction sequence, and outputting a message output command accompanied by selection information of the output message to a user interface processing unit, and a user information processing unit for obtaining message information based on the selection information input from said security information processing unit and outputting to a display unit.

Abstract: A processor is provided that is capable of concurrently processing a sequence of instructions for a plurality of threads achieving the retry success rate equivalent to the success rate in processors that process a sequence of instructions for a single thread. An arithmetic device 200 is provided with an instruction execution circuit 201 for executing a plurality of threads, or an execution control circuit 202 for controlling the execution state or rerunning of the threads.

Abstract: A system and method for signature-based redundancy comparison provides for receiving, by a master part, an input signal and generating, by the master part, a binary output signal, generating a delayed input signal based on the input signal, generating a first output signature based on the binary output signal, and generating a delayed first output signature based on the first output signature. The system and method further comprise generating a delayed binary output signal based on the delayed input signal, generating, by a checker part, a delayed second output signature based on the delayed binary output signal, comparing the delayed first output signature with the delayed second output signature, and generating an error signal, where the state of the error signal is based upon the comparison.

Abstract: A method for writing and reading data in memory cells, comprising, when writing a data in a block of a first memory zone, a step consisting of writing in a second memory zone a temporary information structure metadata comprising a start flag, an identifier of the temporary information structure, an information about the location of the block in the first memory zone, and a final flag, and, after a power on of the first memory zone, searching for an anomaly in temporary information structures present in the second memory zone.

Abstract: One or more techniques and/or systems are disclosed for detecting anomalies in a message log. A log message is parsed from an unstructured text string to a structured form, comprising messages signature and parameter values. Structured log messages that contain a same parameter value of a same program variable are grouped together. One or more invariants for are identified from respective types of log message groups. Invariants are applied to log sequences of respective log types.

Abstract: A circuit arrangement and method utilize existing redundant execution pipelines in a processing unit to execute multiple instances of stability critical instructions in parallel so that the results of the multiple instances of the instructions can be compared for the purpose of detecting errors. For other types of instructions for which fault tolerant or stability critical execution is not required or desired, the redundant execution pipelines are utilized in a more conventional manner, enabling multiple non-stability critical instructions to be concurrently issued to and executed by the redundant execution pipelines. As such, for non-stability critical program code, the performance benefits of having multiple redundant execution units are preserved, yet in the instances where fault tolerant or stability critical execution is desired for certain program code, the redundant execution units may be repurposed to provide greater assurances as to the fault-free execution of such instructions.

Abstract: A system comprising a plurality of storage systems, which uses storage devices of multiple levels of reliability. The reliability as a whole system is increased by keeping the error code for the relatively low reliability storage disks in the relatively high reliability storage system. The error code is calculated using hash functions and the value is used to compare with the hash value of the data read from the relatively low reliability storage disks.

Abstract: A method of checking the integrity of a dynamic link library (DLL) file called by an application being executed on a handheld medical device is described. The method includes loading a DLL from a read only memory (ROM) to a random access memory (RAM) beginning at a fixed location in the RAM. The DLL includes a first routine for performing a safety critical function of the handheld medical device and a second routine for performing a cyclical redundancy check (CRC) once the DLL is loaded to the RAM. The method includes selectively executing the first routine from the RAM. The method includes selectively executing the second routine from the RAM including: calculating a check value based on the DLL; comparing the check value with a predetermined check value; and indicating that an error is present when the check value is different than the predetermined check value.

Abstract: An apparatus and a method for Automatic Repeat reQuest (ARQ) feedback in a wireless communication system are provided. A method for the ARQ feedback at a receiving end includes when receiving an ARQ block from the transmitting end, checking for error in the ARQ block, when the ARQ block has no error, initializing and driving a timer used for determining whether to perform the ARQ feedback according to reception of a next ARQ block, when receiving the next ARQ block without error before the timer expires, initializing and driving the timer, and when the timer expires, performing the ARQ feedback in relation to at least one ARQ block received without error.

Abstract: Mechanisms for preventing a distribution of a failure caused by a sequence of instructions in a distributed client server environment are provided. These mechanisms comprise executing the sequence of instructions on a first client, the instructions being provided by a management control server and being indicative of maintenance actions. These mechanisms may further comprise determining by the first client a failure caused by the sequence of instructions, and generating a warning message by the first client based on the determined failure. The warning message may comprise an indicator for the sequence of instructions. In addition, these mechanisms may comprise sending the warning message for informing a second client about the sequence of instructions causing the failure in order to prevent a distribution of the failure.

Abstract: Various exemplary embodiments relate to a method and related network node including one or more of the following: receiving, at a policy and charging rules node (PCRN), a request from a requesting node for an establishment of a first service data flow (SDF); generating a first rule set for implementing the first SDF in response to the request; transmitting a first rule of the rule set to a first node for installation of the first rule; waiting for a period of time for a response from the first node; determining from the response whether installation of the first rule at the first node failed or succeeded; and if installation of the first rule succeeded, transmitting a second rule of the first rule set to a second node for installation of the second rule.

Abstract: A versioned workload partition (WPAR) can be migrated from a source machine to a destination machine. Each thread associated with a process executing within the versioned WPAR is frozen. For each thread associated with the process, an error number associated with the thread is received in response to freezing execution of the thread and at least a current state of the thread is determined as checkpoint information associated with the thread based, at least in part, on the error number associated with the thread. The checkpoint information associated with the one or more threads is provided to the destination machine. The checkpoint information is used at the destination machine to reconstruct the process within a destination versioned WPAR on the destination machine.

Abstract: Provided are methods and systems of selectively decoding optical data read from an optical storage medium based on a checksum algorithm technique. In one embodiment, optical data is converted into a data stream and buffered, and the checksum algorithm is applied to the data stream. If the calculated checksum matches an encoded checksum of the data stream, the data stream may be output without requiring further decoding. If the calculated checksum does not match the encoded checksum, the buffered data stream may be decoded to produce a corrected data stream, and the checksum algorithm may be applied to the corrected data stream. In some embodiments, the optical data may be re-read if the corrected data stream does not pass the checksum test, and the data stream obtained from the re-reading may be combined with the buffered data stream for further decoding.

Abstract: A processor includes an accumulator, a storage that outputs data to the accumulator, an error detector that outputs a first error detection signal upon detecting an error in the data, an error identifier that outputs an error identification signal indicating that an error occurs in the storage, an error identification signal holder that outputs the error identification signal as a second error detection signal, an error detection signal holder that holds the first error detection signal and outputs a cancellation signal to stop the accumulation processing of the accumulator, a first calculator that starts making a first calculation based on the second error detection signal and the cancellation signal, and outputs a correction start signal after a lapse of a calculation period, and an error corrector that corrects the error of the data upon receiving the correction start signal.

Abstract: The data transfer control device of the present invention is capable of improving data transfer efficiency while discarding error data, a DMA parameter storing control unit (1112) temporarily stores parameters to a store resource; a data processing unit (1201) performs error detection processing for data that is transferred; a DMA parameter return control unit (1122) causes parameters used at transfer time of data for which the processing result in the error detection processing was an error to be returned as parameters for subsequent data transfer use from the store resource; and a completion notification delay control unit (1121), with regard to the parameters, causes the completion notification to a host system that indicates that data transfer has completed normally for each of the parameters to wait for normal completion of data transfer that uses parameters that had been set earlier than each of the first-mentioned parameters.

Abstract: An information handling system (IHS) troubleshooting system includes a customer IHS including a plurality of components. A customer management system in the customer IHS detects a failure in a managed system and, in response, immediately triggers a device snapshot of the customer IHS. At least one managed system in the customer IHS includes a device snapshot engine that, in response to the customer management system triggering the device snapshot of the customer IHS, immediately create the device snapshot of the customer IHS. A device snapshot storage in the customer IHS stores the device snapshot of the customer IHS. A snapshot communication engine in the customer IHS sends the device snapshot of the customer IHS over the network to a support IHS. The support IHS may load the device snapshot into a virtual IHS and manage the virtual IHS to replicate the failure detected in the managed system for troubleshooting.

Abstract: According to one embodiment, a method for detecting a periodic error, the method detecting a periodic processing error of a module controlled by a processor, the processor controlling a periodic processing by booting a peripheral module, the peripheral module outputting periodic triggers with a predetermined interval includes storing a first count value acquired from a counter, a second count value when the processing is started, and a third count value when the processing is completed, calculating a processing time on a basis of the three count values, and comparing the processing time with the predetermined interval to determine whether the periodic processing error occurs.

Abstract: A method is provided for managing changes to a computer system. The method includes generating a database configured with fields identifying one or more component changes and potential problems associated with each one or more component changes; populating the fields of the database with information as a change is made to a computer system; monitoring the computer system for issuance of error alerts; comparing issued error alerts against entries of potential problems in the database; and identifying a set of at least one of the component changes as a potential cause of the issued error alert based on the result of the comparing step. The method executes a corrective process in response to the identification of the potential cause of the issued error and updates the database entry of the set of at least one of the component changes to reflect the issued error as a confirmed error thereof.

Abstract: A high availability system has an application server communicatively coupled to one or more client machines through a network utilizing stateless communication sessions. The application server manages concurrent execution of tasks on multiple client machines. A task may be dependent on the execution of another task and the dependencies are managed through stages. The application server utilizes a fault tolerance methodology to determine a failure to any one of the components within the system and to perform remedial measures to preserve the integrity of the system.

Abstract: An embodiment relates generally to an apparatus for debugging. The apparatus includes a memory configured to store data and an arithmetic logic unit configured to perform logical and arithmetic operations. The apparatus also includes a control unit configured to interface with the memory and arithmetic logic unit and to decode instructions. The control unit is configured to write a data state designated to be overwritten by a currently executing instruction to a buffer allocated in the memory in response to a trace debug flag being set.

Abstract: The testing of services techniques include a method, a system, and a non-transitory computer-readable storage medium. In some embodiments of these techniques, the method includes receiving a first payload generated by a first service. The first service transmits the first payload to a system. The method further includes receiving a second payload from a second service. The second payload is generated based on data received from the first service. The method further includes receiving a schema associated with the second payload. The schema is configured to define the structure of the second payload. The method further includes determining one or more discrepancies between the second payload and the first payload using the schema associated with the second payload. The method further includes determining a testing result based on the one or more discrepancies. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules.

Abstract: The invention relates to a device (D) for checking frames of groups of bits, received by an electronic device (O1) connected to a communication network (RC) and using at least one so-called non-secure-type local function. The device (D) includes checking means (MC) which, should an error occur in at least one group of bits in a frame received from the network (RC), are configured to force the electronic device (O1) to use as is at least each bit group of the received frame which is representative of a parameter of a non-secure-type local function used by said electronic device (O1).

Abstract: Embodiments of the invention relate to scalable input/output (I/O) function level error detection, isolation, and reporting. An aspect of the invention includes detecting an error in a communication initiated between the function and a system memory, the communication including an I/O request from an application. Future communication is prevented between the one function and the system memory in response to the detecting. The application is notified that the error in communication occurred in response to the detecting.