Abstract: A purpose is to speed up a write process with a parity update. An information processing system includes storage devices constituting a RAID group, coupled to one bus and communicating with each other. Each of the storage devices includes a device controller and a storage medium for storing data. The storage devices include a first storage device storing old data and a second storage device storing old parity associated with the old data. A first device controller of the first storage device creates intermediate parity based on the old data and new data for updating the old data and transmit the intermediate parity to the second storage device specifying the second storage device storing the old parity associated with the old data, and a second device controller of the second storage device creates new parity based on the intermediate parity and the old parity.

Abstract: A wireless communication apparatus for a wireless communication system is described in one example comprising a receiver to receive communication signals, one or more processor to determine, based on the communication signals, that at least two SIM cards are located in one and the same wireless communication device of the wireless communication system, and the one or more processor further to coordinate requests for the at least two SIM cards that are located in the wireless communication device. Other embodiments may be described and/or claimed.

Abstract: A dual-port memory including a first memory array and at least one address decoder. The first memory array includes memory cells and two ports for each of the memory cells. The at least one address decoder generates word line signals for concurrent access to two ports of one or more cells of the memory cells in a same row of the first memory array. Each of the word line signals is generated to perform a read operation. Pulse widths of the word line signals for the read operations are proportional to a ratio of (i) a reference amount of cell current of a cell of a reference memory array to (ii) an amount of cell current of the one or more cells of the plurality of memory cells in a same row of the first memory array.

Abstract: A security system notifies of an alarm situation. The security system has two separate communications paths. When the alarm situation is determined, the security system may select one of the two separate communications paths based on performance, cost, urgency, and other factors.

Abstract: Methods and systems for efficient file replication are provided. In some embodiments, one or more coarse signatures for blocks in a base file are compared with those coarse signatures for blocks of a revised file, until a match is found. A fine signature is then generated for the matching block, of the revised file and compared to a fine signature of the base file. Thus, fine signatures are not computed unless a coarse signature match has been found, thereby minimizing unneeded time-consuming fine signature calculations. Methods are also provided for determining whether to initiate a delta file generation algorithm, or whether to utilize a more efficient replication method, based upon system and/or file parameters. In accordance with additional embodiments, the lengths of valid data on physical blocks are obtained from physical block mappings for the files, and these lengths and mappings are utilized for delta file generation, to minimize unnecessary signature computations.

Abstract: A virtual computer system includes an external event acquisition controller, an external event storing unit, and a snap shot creating unit. The external event acquisition controller performs control for acquiring an event regarding an external device provided outside a virtual computer which mounts a guest operating system in which an application program is installed. The external event storing unit stores the external event acquired by the external event acquisition controller. The snap shot creating unit creates a snap shot of the guest operating system including the application program after the external event is stored in the external event storing unit.

Abstract: Testing systems and methods, as well as memory devices using such testing systems and methods, may facilitate testing of memory devices using a read-modify-write test procedure. One such testing system receives a signal indicative of at least some of a plurality of bits of data read from an address differing from each other, and then masks subsequent write operations at the same address. Therefore, any address at which the bits of read data do not all have the same value may be considered to be faulty. Failure data from the test can therefore be stored in the same array of memory cells that is being tested.

Abstract: Novel tools and techniques are described for providing remote control of consumer electronics devices, and, more particularly, to tools and techniques for providing virtual remote control of consumer electronics devices that do not have dedicated remote controllers.

Abstract: Embodiments relate to an isolated program execution environment. An aspect includes receiving, by the isolated program execution environment on a computer comprising a processor and a memory, a request to run a program. Another aspect includes wrapping program code corresponding to the program as a function. Another aspect includes cloning a real global object of the isolated program execution environment to create a fake global object. Another aspect includes passing the fake global object to the function. Another aspect includes executing the function, such that the function executes the program.

Abstract: Systems and methods are disclosed for ingesting data, such as point of interest data. According to certain embodiments, a raw data load transmitted over a network is received from a first data source. The raw data load may comprise a plurality of raw data records, which may be stored in a first database. A first plurality of standard data records previously received from the first data source may be accessed and compared to each of the plurality of raw data records to identify at least one added record. The at least one added record may be compared to a second plurality of standard data records received from a second data source to identify a matching record received from the second data source. The at least one added record may be assigned a key from the matching record. Moreover, the updated information may be sent to an update queue, such that applications may be notified of and receive the updates.

Abstract: A code protection scheme for controlling access to a memory region in an integrated circuit includes a processor with an instruction pipeline that includes multiple processing stages. A first processing stage receives one or more instructions. A second processing stage receives address information identifying a protected memory region of the memory from the first processing stage and protection information for an identified protected memory region. The protection information indicates a protection state assigned to each protected memory region. Based on the instruction type of the received instruction and the protection information associated with a particular protected memory region, the second processing stage determines whether to enable or disable access to the particular protected memory region by the processor or other external host.

Abstract: A computing system can provide user interfaces and back-end operations to facilitate review and invalidation of executed jobs. The system can provide an interface that allows the operator to review quality-control information about a completed job. Once the operator identifies a job as invalid, the operator can be presented with further options, such as whether to invalidate only the reviewed job or the job and all its descendants. The operator can also review antecedent jobs to an invalid job (e.g., in order to trace the root of the problem) and can selectively invalidate antecedent jobs.

Abstract: An example device includes a first error corrector to perform platform error correction based on a stride length. A memory includes a second error corrector that is to perform on-memory error correction that is to be disabled for platform error correction.

Abstract: For a user terminal connected to one of cache devices distributed in a network and receiving contents, terminal access information including terminal address information about the user terminal and identification information of the cache device is stored and managed. If a content retransmission request message of the user terminal is detected at other cache device, this is regarded as a handover of the user terminal. This allows a simple detection of handover that occurs during content transmission.

Abstract: In an illustrative embodiment of a process for software version recommendation, a computer receives information representative of a software instance at a target machine, analyzes the received information using a set of predefined rules and a set of available updates metadata associated with a particular updates agent and target machine to identify information pertinent to a combination of a respective target machine associated with the particular updates agent. The computer, responsive to a determination to send the identified information as a recommendation to the respective target machine, sends the recommendation to the combination of the respective target machine associated with the particular updates agent.

Abstract: In an illustrative embodiment of a process for software version recommendation, a computer receives information representative of a software instance at a target machine, analyzes the received information using a set of predefined rules and a set of available updates metadata associated with a particular updates agent and target machine to identify information pertinent to a combination of a respective target machine associated with the particular updates agent. The computer, responsive to a determination to send the identified information as a recommendation to the respective target machine, sends the recommendation to the combination of the respective target machine associated with the particular updates agent.

Abstract: A system and method for securing processing devices includes a police bridge disposed in one or more data busses between a central processing and input/output peripherals, components or components. The police bridge is suitably disposed between northbridge logic and southbridge logic. Alternatively, or in addition to such placement, a police bridge is suitably place between southbridge logic and super I/O logic. A police bridge is suitably a system-on-chip or fixed or programmable hardware. The police bridge monitors or controls its associated bus to determine whether acceptable data, with an associated certificate in other embodiments, is being communicated and signaling is generated accordingly.

Abstract: Managing interrupts in a computing environment includes executing an instruction, deriving an interrupt mask value based at least in part on the instruction being executed, performing a masking operation involving the interrupt mask value and at least one pending interrupt to determine whether a pending interrupt is allowable, and in the event that the pending interrupt is allowable, performing the interrupt.

Abstract: A system employs a white list of authorized transactions to control access to system registers. In an embodiment, the white list is loaded into filter registers during system boot. Routing logic monitors a logical interconnect fabric of the system for register access requests. The routing logic parses source, destination information from a request to index the white list. If the white list includes an entry corresponding to the processing entity indicated in the source information and the register indicated in the destination information, the routing logic will permit the requested access.

Abstract: In some embodiments, a method includes receiving, at a data collection module implemented in at least one of a memory or a processing device, from a processing system, an observation value for a variable. The observation value of the variable is associated with operation of the processing system at a time. The method further includes computing a deviation value of the variable from a baseline value at the time based on the observation value. The method further includes computing a stableness value of the variable at the time based on the baseline value and a variance of the variable during a time period including the time. The method further includes transmitting an indication of the processing system as operating with a fault in response to the deviation value meeting a first criterion and the stableness value meeting a second criterion.

Abstract: The disclosure provides a download method and system based on a Management Data Input/Output (MDIO) interface, wherein the download method based on the MDIO interface comprises: a master device informing a slave device of using the MDIO interface to start downloading data packets in batches; the master device transmitting data packets in batches to the slave device by using an MDIO frame, wherein the MDIO frame comprises: a data packet address field and/or a data packet serial number field, wherein the data packet address field is used to indicate a relative address of one data packet in the slave device, and the data packet serial number field is used to indicate a location of said one data packet in multiple data packets; the slave device judging that a received data packet is a last data packet of a current batch transmission from the master device, and finishing a current batch download.

Abstract: This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die.

Abstract: A device management system includes an accommodation apparatus, a network device, and a device management apparatus. The accommodation apparatus includes a plurality of storage spaces. Each of the plurality of storage spaces is capable of storing an electronic device. The network device is connected to an electronic device accommodated in the accommodation apparatus. The device management apparatus includes a processor. The processor obtains connection information when a first electronic device is newly placed in the accommodation apparatus. The connection information indicates an expected connection point in the network device. The first electronic device is to be connected to the network device at the expected connection point with a cable. The processor identifies an actual connection point at which the network device has been connected to the first electronic device with the cable. The processor determines, based on the connection information, whether the actual connection point is appropriate.

Abstract: A decoder 5 applies decode processing to N input data in parallel to generate K decode data. An S/P converter 6 outputs N input data applied in series to decoder 5 through first lines L1-L64 dividedly over several times. A P/S converter 7 receives through second lines R1-R60 the K decode data from decoder 5 dividedly over several times to output in series the K decoded data to an external source.

Abstract: A malware detection rule is evaluated for effectiveness and accuracy. The detection rule defines criteria for distinguishing files having a characteristic of interest from other files lacking that characteristic, for instance, malicious files vs. benign files. The detection rule is applied to a set of unknown files. This produces a result set that contains files detected from among the set of unknown files as having the at least one characteristic of interest. Each file from the result set is compared to at least one file from a set of known files having the characteristic to produce a first measure of similarity, and to at least one file from a set of known files lacking the characteristic to produce a second measure of similarity. In response to the first measure of similarity exceeding a first similarity threshold, the detection rule is deemed effective. In response to the second measure of similarity exceeding a second similarity threshold, the detection rule is deemed inaccurate.

Abstract: In accordance with one aspect of the present description, an indication that a communication failure reported in a predetermined time interval is more likely the result of a software failure than a hardware failure may be made if the number of communication links reporting a communication failure in the predetermined time interval exceeds a communication link failure threshold, and the number of communication link devices such as nodes or communication paths which have been implicated as causing a communication failure, exceeds an implicated device threshold. Other features and aspects may be realized, depending upon the particular application.

Abstract: A method begins by tracking age related failure levels of memory devices within the storage unit. The method continues by maintaining a data location table that maps a range of DSN addresses allocated to the storage unit to the memory devices and further records storing of encoded data slices having specific DSN addresses within the memory devices. The method continues, when the age related failure level for a memory device compares unfavorably to a first failure level threshold, by determining to reassign a portion of DSN addresses assigned to the memory device. The method continues by identifying a second memory device having a corresponding age related soft failure level comparing favorable to the first failure level threshold. The method continues by reassigning the portion of the DSN addresses from the memory device to the second memory device and updating the data location table.

Abstract: A system and method for signature-based redundancy comparison provides for receiving, by a master part, an input signal and generating, by the master part, a binary output signal, generating a delayed input signal based on the input signal, generating a first output signature based on the binary output signal, and generating a delayed first output signature based on the first output signature. The system and method further comprise generating a delayed binary output signal based on the delayed input signal, generating, by a checker part, a delayed second output signature based on the delayed binary output signal, comparing the delayed first output signature with the delayed second output signature, and generating an error signal, where the state of the error signal is based upon the comparison.

Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

Abstract: A system and method for optimizing redundant output verification, are provided. A hardware-based store fingerprint buffer receives multiple instances of output from multiple instances of computation. The store fingerprint buffer generates a signature from the content included in the multiple instances of output. When a barrier is reached, the store fingerprint buffer uses the signature to verify the content is error-free.

Abstract: A recoverable and fault-tolerant CPU core and a control method thereof are provided. The recoverable and fault-tolerant CPU core includes first, second, and third arithmetic logic circuits configured to perform a calculation requested by the same instruction, a first selector configured to compare calculation values output from the first, second, and third arithmetic logic circuits by the same instruction, determine as a normal state when two or more of the calculation values are the same, and if not, determine as a fault state, and a register file configured to record the calculation value having the same value, when determining as the normal state in the first selector.

Abstract: Architectures and techniques for uploading virtual machine (VM) images to a network-accessible computing platform from a client device while simultaneously performing error detection of the VM images at the client device. One technique can include transmitting a request from the client device to upload VM images. The technique can further include receiving an application from the computing platform and using the application to reconstitute the VM images from a first stream at the client device while performing error detection. The technique also includes using the application to upload the VM images from a second stream at the client device to the computing platform while performing the error detection.

Abstract: In a data processing system, a selection is made, based at least on addresses of previously detected errors in a memory subsystem, between at least a first timing and a second timing of data transmission with respect to completion of error detection processing on a target memory block of the memory access request. In response to receipt of the memory access request and selection of the first timing, data from the target memory block is transmitted to a requestor prior to completion of error detection processing on the target memory block. In response to receipt of the memory access request and selection of the second timing, data from the target memory block is transmitted to the requestor after and in response to completion of error detection processing on the target memory block.

Abstract: In a data processing system, a selection is made, based at least on addresses of previously detected errors in a memory subsystem, between at least a first timing and a second timing of data transmission with respect to completion of error detection processing on a target memory block of the memory access request. In response to receipt of the memory access request and selection of the first timing, data from the target memory block is transmitted to a requestor prior to completion of error detection processing on the target memory block. In response to receipt of the memory access request and selection of the second timing, data from the target memory block is transmitted to the requestor after and in response to completion of error detection processing on the target memory block.

Abstract: Versioned memories using a multi-level cell (MLC) are disclosed. An example method includes comparing a global memory version to a block memory version, the global memory version corresponding to a plurality of memory blocks, the block memory version corresponding to one of the plurality of memory blocks. The example method includes determining, based on the comparison, which level in a multi-level cell of the one of the plurality of memory blocks stores checkpoint data.

Abstract: In one embodiment, the present invention includes a method for handling a request received in an agent designed in accordance with a peripheral component interconnect (PCI) specification using PCI Express™ semantics. More specifically, responsive to determining that the agent does not support the request, an unsupported request detection register of the agent can be updated, and a response sent from the agent to indicate that the agent does not support the request. Other embodiments are described and claimed.

Abstract: An apparatus and a method for Automatic Repeat reQuest (ARQ) feedback in a wireless communication system are provided. A method for the ARQ feedback at a receiving end includes when receiving an ARQ block from the transmitting end, checking for error in the ARQ block, when the ARQ block has no error, initializing and driving a timer used for determining whether to perform the ARQ feedback according to reception of a next ARQ block, when receiving the next ARQ block without error before the timer expires, initializing and driving the timer, and when the timer expires, performing the ARQ feedback in relation to at least one ARQ block received without error.

Abstract: Memory devices and/or methods of managing memory data errors are provided. A memory device detects and corrects an error bit of data read from a plurality of memory cells, and identifies a memory cell storing the detected error bit. The memory device assigns a verification voltage to each of the plurality of first memory cells, the assigned verification voltage corresponding to the corrected bit for the identified memory cell, the assigned verification voltage corresponding to the read data for the remaining memory cells. The memory device readjusts the data stored in the plurality of memory cells using the assigned verification voltage. Through this, it is possible to increase a retention period of the data of the memory device.

Abstract: A buffer integrated circuit device. The device comprising an output driver formed on the substrate member, the output driver having at least a command bus and an address bus. The device has a protocol and parity checking block (“Block”). The device has a table configured in the block. The table is programmable with a plurality of timing parameters. The device has a memory state block coupled to the table and a command history table coupled to the table to process protocol information for all commands that pass through the Block. The buffer integrated circuit device utilizes the protocol checking functionality to prevent failure propagation and enables data protection even in the case of host memory controller failure or system-level failure of any signal or signals on the command, control and address bus from the host memory controller to the buffer integrated device.

Abstract: Systems and methods for automated monitoring of automated server control components are provided. Embodiments may include transmitting a request for state information associated with a component of the automated server control system. At least one of a reception of the state information for the component and a threshold time period without reception of the state information for the component may be detected. Some embodiments may include determining if the received state information for the component comprises an error condition. In some instances, an alert may be output based on at least one of detecting the threshold time period without reception of the state information for the component and determining that the received state information comprises an error condition.

Abstract: A method for detecting errors in hardware including running a transaction on a plurality of cores, wherein each of the cores runs a respective copy of the transaction, synchronizing the transaction on the cores, comparing results of the transaction on the cores, and determining an error in one or more of the cores.

Abstract: An information processing method for supporting data setting include: extracting a first feature value for each of plural parameters from first data that is data after at least one parameter value, which is included in second data that includes, for each of plural setting targets, each parameter value for each of the plural parameters, was changed; and extracting a parameter that is a candidate of an erroneously changed parameter based on a difference between a second feature value that is extracted, for each of the plural parameters, from the second data and a corresponding first feature value.

Abstract: A technology for implementing a method for a machine check architecture environment. A method of the disclosure includes obtaining an occurrence of an error. The occurrence of the error causes a non-microcoded processing device to enter an error monitoring state. The method further processes the error using a dedicated memory portion for the error monitoring state while the non-microcoded processing device is in the error monitoring state. The error monitoring state is dedicated to error processing. The method further determines information associated with the error. The information associated with the error is in a predefined format.

Abstract: A server-based environment for reporting a status of a security, monitoring and automation controller is provided. Detecting cessation of an always-on persistent network connection between the SMA controller and the server is also provided. Reporting the cessation of the network connection to an end user and defined others is further provided. A further aspect provides for automatically reporting an alarm event to a central station, the end user, and others, in the event the cessation of the network connection occurs while the SMA controller is armed and after a zone fault event, and not receiving a disarm notification prior to expiration of a preset entry delay.

Abstract: File system errors are handled and computing systems are recovered by, responsive to receiving a page buffer request, initializing a sleep timer according to a detection interval value plus a hang resolution range value; responsive to the timer expiring, detecting that a process, thread, application program, daemon, or task is waiting on availability of the requested page buffer; and responsive to the detection, quarantining metadata associated with the requested page buffer, failing the page buffer request and releasing one or more locks on the requested page buffer. This process is then optionally repeated for additional processes, threads, application programs, daemons, tasks or combinations thereof which are waiting for availability of the requested page buffer, optionally randomizing the detection interval value in order to avoid an instantaneous recovery from the error.

Abstract: A system for simplifying message sequences is disclosed. The system includes a shrink component and a message simplification component. The shrink component is configured to receive a failure inducing message sequence and to provide a shrunk sequence based on the failure inducing message sequence. The shrunk sequence has less or equal number of messages than the failure inducing message sequence. The message simplification component is configured to receive the shrunk sequence and to simplify messages within the shrunk sequence to generate a simplified message sequence including debugging hints.

Abstract: An electronic device includes a CPU and an MCU intercommunicating with the CPU. The MCU sends an instruction to the CPU at a predetermined time interval. The MCU detects whether a response is received from the CPU within a predetermined time period after the instruction is sent, and determines that the CPU is nonfunctioning when no response is received from the CPU. The MCU restarts the CPU when the CPU is determined to be nonfunctioning. A method for releasing an electronic device from a nonfunctioning state is also provided.

Abstract: Embodiments of the present invention relate to a peripheral component interconnect express endpoint device accessing method, a computer system, and an apparatus. A state of an access request sent by a processor is monitored, and a simulation response message for the access request is sent to the processor when it is determined that the PCIe endpoint device sends no response message for the access request. Therefore, according to the simulation response message, the processor can confirm completion of the procedure corresponding to the previously sent access request, and shut down a timer for timing the access request and clear the buffered access request, thereby keeping normal processing in the processor and avoiding the MCE resetting problem that arises from accumulation of access requests in the processor.

Abstract: A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component receives a signature from the second component over a line of the interface concurrent with READ and WRITE operations over the interface. The latency associated with transmission of a signature from the second component to the first component is the time taken for the second component to compute a signature. The signature received is compared to a signature stored by the first component. Both signatures correspond to a particular READ or WRITE command. Based on the comparison, the first component determines whether the READ or WRITE operation was successful, and directs the second component as necessary.

Abstract: A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.