Memory Testing Patents (Class 714/718)
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Patent number: 8549362Abstract: A first module calculates a failure occurrence risk index of each data storage area address. A second module calculates a power saving index of each data storage area address. A third module calculates an access speed index per unit data volume necessary to access each data storage area address. A fourth module generates a distribution table that represents the failure occurrence risk index, the power saving index, and the access speed index for each candidate address, with respect to data to be distributed. A fifth module selects a candidate address in the distribution table such that the power saving index and the access speed index meet restricting conditions and the failure occurrence risk index is minimized, and distributes the data to the candidate address.Type: GrantFiled: September 14, 2012Date of Patent: October 1, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kenji Hirohata, Minoru Yonezawa, Chie Morita, Takeichiro Nishikawa, Minoru Nakatsugawa, Minoru Mukai
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Patent number: 8549371Abstract: A semiconductor memory device includes a test mode signal generation circuit configured to generate test mode signals which are selectively enabled, in response to a test enable signal which is enabled upon entry into a test mode; and a test mode signal output circuit configured to store the test mode signals in response to an input control signal and output the test mode signals in response to an output control signal, wherein the input control signal is enabled when a test write signal is generated according to a combination of commands, and the output control signal is a signal which is generated by delaying a test read signal a preset amount of time, where the test read signal is generated according to a combination of the commands.Type: GrantFiled: September 13, 2012Date of Patent: October 1, 2013Assignee: SK Hynix Inc.Inventor: Eun Ryeong Lee
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Patent number: 8549367Abstract: A method and system for randomizing memory in a functional verification test of a user design is disclosed. A random number is generated during the functional verification test. The data stored in the memory of the user design is stored. Encryption keys unique for each memory address of the memory are generated. Each encryption key for each memory address is a function of the random number and the memory address. Data in each memory address of the memory is encrypted with the encryption keys unique for each memory address. After exiting a low-power or power-off state, data in each memory address is read and decrypted using the same encryption keys. Data before and after the low-power or power-off state are compared to test memory loss.Type: GrantFiled: December 29, 2010Date of Patent: October 1, 2013Assignee: Cadence Design Systems, Inc.Inventor: Mark A. Sherred
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Patent number: 8543874Abstract: Methods and apparatus for executing internal operations of memory devices utilizing instructions stored in the memory array of the memory device. Decode blocks adapted to interpret instructions and data stored in the memory device. Methods can be used to perform internal self-test operations of the memory device by executing test procedures stored in the memory array of the memory device performing a self-test operation.Type: GrantFiled: October 15, 2012Date of Patent: September 24, 2013Assignee: Micron Technology, Inc.Inventors: Frankie F. Roohparvar, Benjamin Louie
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Patent number: 8543801Abstract: A method for booting a computer system is disclosed. The computer system has a main memory. The method includes the steps of providing a backup memory, replacing the main memory by the backup memory when the computer system is booted and the main memory fails to operate normally, and decompressing the program codes of the BIOS to the backup memory to perform the backup booting procedure.Type: GrantFiled: February 3, 2010Date of Patent: September 24, 2013Assignee: ASUSTeK Computer Inc.Inventors: Shao-Kang Chu, Hsu-Hung Cheng
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Patent number: 8543863Abstract: Dynamically replicated memory is usable to allocate new memory space from failed memory pages by pairing compatible failed memory pages to reuse otherwise unusable failed memory pages. Dynamically replicating memory involves detecting and recording memory faults, reclaiming failed memory pages for later use, recovering from detected memory faults, and scheduling access to replicated memory pages.Type: GrantFiled: November 18, 2009Date of Patent: September 24, 2013Assignee: Microsoft CorporationInventors: Engin Ipek, Thomas Moscibroda, Douglas C. Burger, Edmund B. Nightingale, Jeremy P. Condit
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Patent number: 8543873Abstract: A method and apparatus for multi-site testing of computer memory devices. An embodiment of a method of testing computer memory devices includes coupling multiple memory devices, each memory device having a serializer output and a deserializer input, wherein the serializer output of a first memory device is coupled with a deserializer input of one or more of the memory devices of the plurality of memory devices. The method further includes producing test signal patterns using a test generator of each memory device, serializing the test signal pattern at each memory device, and transmitting the serialized test pattern for testing of the memory devices, wherein testing of the memory devices includes a first test mode and a second test mode.Type: GrantFiled: January 6, 2010Date of Patent: September 24, 2013Assignee: Silicon Image, Inc.Inventor: Chinsong Sul
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Publication number: 20130246867Abstract: This technology relates to smoothly performing a test on a memory circuit having a high memory capacity while reducing the size of a test circuit. A test circuit according to the present invention includes a test execution unit configured to perform a test on a target test memory circuit, an internal storage unit configured to store data for the test execution unit, and a conversion setting unit configured to set a part of or the entire storage space of the target test memory circuit as an external storage unit for storing the data for the test execution unit.Type: ApplicationFiled: September 5, 2012Publication date: September 19, 2013Inventors: Hyung-Gyun YANG, Hyung-Dong LEE, Yong-Kee KWON, Young-Suk MOON, Hong-Sik KIM
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Patent number: 8539289Abstract: In a memory testing method for testing a memory module of a computing device, an operating voltage of the memory module is adjusted to a first voltage or a second voltage. A predetermined data set is written into the memory module after the operating voltage of the memory module is adjusted, and the written data set is read out from the memory module, to accomplish a data writing and reading process of the memory module. A register value that presents how many memory errors have occurred during the data writing and reading process is acquired from an ECC register of the memory module, to determine whether the memory module is stable during the adjusting of the operating voltage according to the register value.Type: GrantFiled: December 7, 2011Date of Patent: September 17, 2013Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.Inventors: Jie-Jun Tan, Yu-Long Lin, Hua Dong
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Patent number: 8539290Abstract: An integrated circuit is described that has a substrate with a memory array with dedicated support hardware formed on the substrate. An access wrapper circuit is coupled to address and data lines of the memory array and to control lines of the dedicated support hardware. The wrapper circuit is configured to provide an access port to the memory array. A test controller is formed on the substrate and coupled in parallel with the access wrapper circuit to the address and data lines of the memory array and to the control lines of the dedicated support hardware, wherein the test controller is operable to perform a test of the memory array by manipulating control signals to the support hardware in addition to those required to write data patterns into the memory array and to read the contents of the memory array.Type: GrantFiled: February 5, 2013Date of Patent: September 17, 2013Assignee: Texas Instruments IncorporatedInventors: Daniel Robert Burggraf, III, Hari Pendurty
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Patent number: 8538720Abstract: A cold boot test system and method can control an electronic device to perform a cold boot process to test whether the electronic device is operable. The method sets time parameters for a test period of the cold boot process, drives a data communication interface of a computer to generate a period control signal according to the time parameters, and sends the period control signal to a controller via the data communication interface. The method further transfers the period control signal to the electronic device by controlling a power switch to switch on and switch off, controls the electronic device to execute the cold boot process to generate test information correspondingly. In addition, the method obtains the test information from the electronic device, and displays the test information on a display screen of the computer upon the condition that the cold boot process is abnormal.Type: GrantFiled: November 30, 2010Date of Patent: September 17, 2013Assignee: Hon Hai Precision Industry Co., Ltd.Inventor: Ming-Yuan Hsu
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Publication number: 20130238947Abstract: A RAM 200 to be diagnosed is divided into n (n being an integer of 3 or greater) pieces of base regions. In an idle time of periodic processing performed in a system in which the RAM 200 is incorporated, two base regions are selected from the divided base regions, and the selected two base regions are diagnosed using a diagnostic method capable of detecting a coupling fault. Thereafter, in an idle time of the periodic processing, operations to select an unselected pair of base regions and diagnose the selected pair are repeated, so as to diagnose all combinations of pairs.Type: ApplicationFiled: February 18, 2011Publication date: September 12, 2013Applicant: Mitsubishi Electric CorporationInventor: Ryoya Ichioka
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Patent number: 8531322Abstract: Embodiments of a time-to-digital converter are provided, comprising a delay stage matrix and a measurement circuit. The delay stage matrix comprises a first and a second delay lines coupled thereto, and is arranged to propagate a transition signal from a starting delay stage in the first and a second delay lines, wherein each of the first and second delay lines comprises a same number of delay stages coupled in series, each delay stage in one of the first and second delay lines is coupled to a corresponding delay stage in the other delay line and operative to generate a delayed signal. The measurement circuit is arranged to determine a time of the transition signal propagating along the delay stages by sampling the delayed signals using a measurement signal to generate and hold a digital representation of the time.Type: GrantFiled: April 18, 2012Date of Patent: September 10, 2013Assignee: Mediatek Singapore Pte. Ltd.Inventors: Changhua Cao, Xiaochuan Guo, Yen-Horng Chen, Caiyi Wang
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Patent number: 8527820Abstract: A semiconductor device includes a first management area storing a plurality of inspection results, the plurality of inspection results being obtained by executing inspections for each of a plurality of storage areas which store a plurality of data; and a second management area storing the plurality of inspection results. The first and second management areas are independent from each other.Type: GrantFiled: February 7, 2011Date of Patent: September 3, 2013Assignee: Elpida Memory, Inc.Inventor: Shin Ito
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Patent number: 8522089Abstract: A method of testing a semiconductor device that includes first and second mutually asynchronous modules, a buffer for storing transaction data for read/write operations from the first module and transferring it to the second module synchronously with the data rate of the second module, and an inhibit input. The second module receives the transaction data from the buffer and transfers the data to a data output when the inhibit signal is de-asserted and not when the inhibit signal is asserted. The method of testing includes repeatedly: asserting the inhibit signal; providing test transaction data to the first module and storing the data in the buffer while the inhibit signal is asserted; de-asserting the inhibit signal so that the second module transfers test transaction data received from the buffer to the data output synchronously with the data rate of the second module; and capturing deterministically test transaction data from the output of the second module.Type: GrantFiled: January 21, 2011Date of Patent: August 27, 2013Assignee: Freescale Semiconductor, Inc.Inventor: Deepak Jindal
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Patent number: 8522090Abstract: A method of testing a double data rate (DDR) memory interface within a System-on-chip (SoC). The method comprises generating a data stream within the SoC and writing the data stream to an internal memory within the SoC via the DDR memory interface. The method further comprises reading the data stream from the internal memory within the SoC and comparing the data stream generated within the SoC with the data stream read from the internal memory within the SoC.Type: GrantFiled: May 24, 2011Date of Patent: August 27, 2013Assignee: Marvell International Ltd.Inventors: Jitendra Kumar Swarnkar, Vincent Wong, Yun-Ho Wu, Rakeshkumar K. Patel
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Patent number: 8522188Abstract: In a method of designing a system-on-chip including a tapless standard cell to which body biasing is applied, a slow corner timing parameter is adjusted to increase a slow corner of an operating speed distribution for the system-on-chip by reflecting forward body biasing, and a fast corner timing parameter is adjusted to decrease a fast corner of the operating speed distribution for the system-on-chip by reflecting reverse body biasing. The system-on-chip including the tapless standard cell is implemented based on the adjusted slow corner timing parameter corresponding to the increased slow corner and the adjusted fast corner timing parameter corresponding to the decreased fast corner. The slow corner timing parameter corresponds to a lowest value of an operating speed design window of the system-on-chip, and, the fast corner timing parameter corresponds to a highest value of the operating speed design window of the system-on-chip.Type: GrantFiled: September 25, 2012Date of Patent: August 27, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Hyung-Ock Kim, Jae-Han Jeon, Jung-Yun Choi, Kee-Sup Kim, Hyo-Sig Won
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Patent number: 8522099Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: May 7, 2012Date of Patent: August 27, 2013Assignee: Micron Technology, Inc.Inventor: Joe M. Jeddeloh
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Publication number: 20130219235Abstract: According to one embodiment, two memory systems each including a memory and a controller are connected via a communication line. The controller includes a testing unit that performs a self-test process on the memory, a communication unit that communicates with the counterpart controller, and a status output unit. The communication unit performs a startup synchronization process which is performed before the self-test process and a termination synchronization process which is performed after the self-test process. The testing unit obtains a comprehensive test result from the test results of the two memory systems, and the status output unit of one memory system outputs the comprehensive test result.Type: ApplicationFiled: February 15, 2013Publication date: August 22, 2013Applicant: Kabushiki Kaisha ToshibaInventor: Kabushiki Kaisha Toshiba
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Patent number: 8516298Abstract: A data protection method for damaged memory cells is provided. A power-on self-test (POST) is executed, and an initial backup memory is reserved in a memory. An operating system (OS) is executed, and data is loaded from a kernel region of the OS in the memory into a mirror region, so that when a processor accesses the data in the kernel region, it also accesses the data in the mirror region. An uncorrectable error (UE) is detected to determine a damaged page, and a backup page is selected from the initial backup memory or dynamically obtained from the OS to back up data in the damaged page. A mapping address of the damaged page and backup page are recorded into a page mapping table in a memory controller. Accordingly, when the OS accesses the damaged page, the memory controller accesses the backup page instead according to the page mapping table.Type: GrantFiled: June 10, 2011Date of Patent: August 20, 2013Assignee: Inventec CorporationInventors: Ying-Chih Lu, Yu-Hui Wang
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Patent number: 8516315Abstract: A method for identifying non stuck-at faults in a read-only memory (ROM) includes generating a golden value of a victim cell, providing a fault-specific pattern through an aggressor cell, generating a test reading of the victim cell in response to the provided fault-specific pattern, and determining whether the ROM has at least one non stuck-at fault. The determination is based on a comparison of the golden value and the test reading of the victim cell.Type: GrantFiled: October 18, 2010Date of Patent: August 20, 2013Assignee: STMicroelectronics International N.V.Inventor: Suraj Prakash
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Publication number: 20130212444Abstract: Correlated failure distribution for memory arrays having different groupings of memory cells is estimated by constructing memory unit models for the groupings based on multiple parameters, establishing failure conditions of the memory unit model using fast statistical analysis, calculating a fail boundary of the parameters for each memory unit model based on its corresponding failure conditions, and constructing memory array models characterized by the fail boundaries. Operation of a memory array model is repeatedly simulated with random values of the parameters assigned to the memory cells and peripheral logic elements to identify memory unit failures for each simulated operation. A mean and a variance is calculated for each memory array model, and an optimal architecture can thereafter be identified by selecting the grouping exhibiting the best mean and variance, subject to any other circuit requirements such as power or area.Type: ApplicationFiled: February 9, 2012Publication date: August 15, 2013Applicant: International Business Machines CorporationInventors: Rajiv V. Joshi, Rouwaida N. Kanj, Sani R. Nassif
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Patent number: 8510612Abstract: Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.Type: GrantFiled: September 7, 2012Date of Patent: August 13, 2013Assignee: Intel CorporationInventors: Pete D. Vogt, Dennis W. Brzezinski, Warren R. Morrow
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Patent number: 8510613Abstract: A method includes temporarily storing write-data to be written into non-volatile memory cells, respectively, the memory cells being divided into cell groups, performing a first operation including write-phases performed in series and on an associated cell group and including applying a write-voltage to the memory cells belonging to the associated cell group in response to an associated write-data to be written into the memory cells belonging to the cell groups, and performing a second operation after the first operation is completed, which includes read-phases performed in series and on an associated cell group and including applying a first read-voltage to the memory cell or cells belonging to the associated one of the cell groups to produce first read-data therefrom, and comparing the first read-data with the write-data to be written into the memory cells belonging to the associated cell groups to produce comparison data.Type: GrantFiled: February 25, 2011Date of Patent: August 13, 2013Assignee: Elpida Memory, Inc.Inventor: Akiyoshi Seko
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Patent number: 8510611Abstract: A computer apparatus includes a main memory, a first memory diagnosis unit that determines a faulty area in the main memory by executing a first memory diagnostic program, and a storage unit that stores a relocatable second memory diagnostic program. Moreover, the computer apparatus includes a second memory diagnosis unit, that loads the second memory diagnostic program into areas of the main memory other than the faulty area determined by the first memory diagnosis unit.Type: GrantFiled: July 28, 2009Date of Patent: August 13, 2013Assignee: Fujitsu LimitedInventors: Takeo Hishinuma, Yoshinori Mesaki, Osamu Ishibashi
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Publication number: 20130205177Abstract: A system and method for verifying memory cards. A memory card is received in a card reader in communication with a computing device. The memory card is scanned utilizing a computing device. A visual indicator is displayed on the computing device indicating whether the card is functioning correctly and whether the memory card passed or failed the scanning. An identifier associated with the memory card is stored in response to determining the memory card passed the scanning. A first volume name of the memory card is rewritten to the second volume name in response to storing the identifier.Type: ApplicationFiled: February 6, 2012Publication date: August 8, 2013Inventor: Jimmie Paul Partee
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Publication number: 20130205179Abstract: Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays. In another aspect of the invention, the MBST circuitry is used set the memory elements of the arrays to a first state and then to an inverse state during a burn-in operation to maintain each of the two opposing states for a desired time in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond an infancy stage.Type: ApplicationFiled: March 15, 2013Publication date: August 8, 2013Applicant: Advanced Micro Devices, Inc.Inventor: Advanced Micro Devices, Inc.
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Publication number: 20130205178Abstract: A system and method for auditing memory cards. A memory card is received in a card reader in communication with a computing device. The memory card is scanned utilizing a computing device. A determination is made whether content in the memory card is acceptable or unacceptable. A first volume name of the memory card is rewritten to the second volume name in response to determining the content in the memory card is acceptable.Type: ApplicationFiled: October 31, 2012Publication date: August 8, 2013Applicant: ATC & Logistics & Electronics, Inc.Inventor: ATC & Logistics & Electronics, Inc.
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Patent number: 8503259Abstract: A memory test is performed by sequentially generating a number of n-bit addresses, whose first to k-th bits (1?k?n) are all set to one of two values, 0 or 1, and whose (k+1)th to n-th bits are all set to the other one of the two values, for all k's which range from 1 to n; writing first test data to each of the generated addresses in the memory; reading second test data from each of the addresses in the memory; and comparing the first test data with the second test data.Type: GrantFiled: March 17, 2009Date of Patent: August 6, 2013Assignee: Fujitsu LimitedInventors: Shogo Shibazaki, Shinkichi Gama, Hideyuki Negi, Takeshi Nagase, Chikahiro Deguchi, Yutaka Sekino
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Patent number: 8499217Abstract: Memory devices and/or error control codes (ECC) decoding methods may be provided. A memory device may include a memory cell array, and a decoder to perform hard decision decoding of first data read from the memory cell array by a first read scheme, and to generate output data and error information of the output data. The memory device may also include and a control unit to determine an error rate of the output data based on the error information, and to determine whether to transmit an additional read command for soft decision decoding to the memory cell array based on the error rate. An ECC decoding time may be reduced through such a memory device.Type: GrantFiled: May 14, 2008Date of Patent: July 30, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Hwan Song, Jun Jin Kong, Jae Hong Kim, Kyoung Lae Cho, Sung Chung Park
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Patent number: 8495441Abstract: A method for adjusting a memory signal phase is applied to data access between a memory controller and a dynamic random access memory (DRAM) of an electronic apparatus. The method includes writing a test data into the DRAM by the memory controller in response to a predetermined status of the electronic apparatus; generating a first data strobe signal; offsetting a phase of the first data strobe signal to access and verify the test data to generate a verification result; generating a target offset value in response to the verification result; and offsetting the phase of the first data strobe signal by the target offset value for subsequent operations.Type: GrantFiled: November 25, 2010Date of Patent: July 23, 2013Assignee: MStar Semiconductor, Inc.Inventor: Yung Chih Chiang
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Patent number: 8495432Abstract: Described are embodiments of an invention for blocking write access to memory modules of a solid state drive. The solid state drive includes a controller access module or a memory access module that controls write access to the solid state drive and the memory modules of the solid state drive. Upon determining that a memory module has failed, the failed memory module or the entire solid state memory device is configured to be read only to prevent an errant write of data over critical data. Further, a failed memory module, or solid state device memory having a failed memory module, may be replaced upon failure.Type: GrantFiled: May 31, 2012Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Louie Arthur Dickens, Timothy A. Johnson, Craig Anthony Klein, Gregg Steven Lucas, Daniel James Winarski
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Patent number: 8495436Abstract: An electronic circuit includes first and second circuits that include corresponding built-in-self-test (BIST) engines to perform memory testing operations on corresponding first and second memory block and generate first and second memory repair data. A multiplexer receives the first and second memory repair data and selectively transmits the first memory repair data during a first test cycle and the second memory repair data during a second test cycle. A shadow register buffers the first memory repair data during the first test cycle and a fuse processor sequentially receives and stores the first and second memory repair data during the second test cycle.Type: GrantFiled: June 17, 2012Date of Patent: July 23, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Deepak Agrawal, Rachna Lalwani
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Patent number: 8495464Abstract: Methods and apparatuses for error correction. A N-bit block data to be stored in a memory device is received. The memory device does not perform any error correction code (ECC) algorithm nor provide designated error correction code storage for the N-bit block of data. Data compression is applied to the N-bit data to compress the block of data to generate a M-bit compressed block of data. A K-bit ECC is computed for the M-bit compressed data, wherein M+K is less than or equal to N. The M-bit compressed data and the K-bit ECC are stored together in the memory device.Type: GrantFiled: June 28, 2010Date of Patent: July 23, 2013Assignee: Intel CorporationInventors: Henry Stracovsky, Michael Espig, Victor W. Lee, Daehyun Kim
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Patent number: 8495437Abstract: A semiconductor memory device including a data bus inversion (DBI) determination unit, a first inverter, a cyclic redundancy check (CRC) calculation unit, a second inverter, and a DQ pin. The DBI determination unit is configured to determine whether to perform DBI based on first data on a main data line and configured to generate DBI data. The first inverter is configured to invert or non-invert the first data according to the DBI data to generate second data. The CRC calculation unit is configured to generate CRC data based on the second data and the DBI data. The second inverter is configured to invert or non-invert the first data according to the DBI data to generate third data. The DQ pin is configured to output the third data externally.Type: GrantFiled: September 4, 2012Date of Patent: July 23, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Kyo-min Sohn, Byung-sik Moon
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Patent number: 8495442Abstract: A system including a first plurality of memory cells to store data, and a memory controller to read the first plurality of memory cells and to identify one or more of the first plurality of memory cells in response to the one or more of the first plurality of memory cells being defective. A second plurality of memory cells stores information regarding locations of the one or more of the first plurality of memory cells. The second plurality of memory cells stores the information at a lower density than the first plurality of memory cells. The information read from the second plurality of memory cells has a lower probability of error than the data read from the first plurality of memory cells.Type: GrantFiled: September 10, 2012Date of Patent: July 23, 2013Assignee: Marvell International Ltd.Inventors: Pantas Sutardja, Zining Wu
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Patent number: 8489944Abstract: Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.Type: GrantFiled: December 3, 2012Date of Patent: July 16, 2013Assignee: Intel CorporationInventors: Warren Morrow, Pete Vogt, Dennis W. Brzezinski
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Patent number: 8489943Abstract: A system for generating test signals to test characteristics of input-output (IO) cells includes a memory and a processor coupled together through an integrated circuit (IC) chip. The IC chip includes a controller configured to exchange signals between the memory and the processor through IO cells of the IC chip. The IC chip further includes a protocol sequence generator for generating test signals for testing characteristics of the IO cells.Type: GrantFiled: March 31, 2010Date of Patent: July 16, 2013Assignee: STMicroelectronics International N.V.Inventors: Anil K. Dwivedi, Akhilesh Chandra, Ajay Arun Kulkarni
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Patent number: 8484519Abstract: The subject disclosure describes a method for reducing a sector error rate in a flash memory device, the method comprising, identifying a first program verify level having a first value, selecting an adjustment value for the first program verify level and programming the adjustment value to the first program verify level to replace the first value and to shift a first programming distribution associated with the first program verify level, wherein the shift in the first programming distribution is associated with a decrease in a sector error rate, wherein the shift in the first programming distribution is associated with an increase in a bit error rate. A flash storage device and computer-readable media are also provided.Type: GrantFiled: July 19, 2012Date of Patent: July 9, 2013Assignee: STEC, Inc.Inventors: Anthony D. Weathers, Richard D. Barndt, Xinde Hu
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Patent number: 8484529Abstract: Error correction and detection in a redundant memory system that includes a memory controller; a plurality of memory channels in communication with the memory controller, the memory channels including a plurality of memory devices; a cyclical redundancy code (CRC) mechanism for detecting that one of the memory channels has failed, and for marking the memory channel as a failing memory channel; and an error correction code (ECC) mechanism. The ECC is configured for ignoring the marked memory channel and for detecting and correcting additional memory device failures on memory devices located on one or more of the other memory channels, thereby allowing the memory system to continue to run unimpaired in the presence of the memory channel failure.Type: GrantFiled: June 24, 2010Date of Patent: July 9, 2013Assignee: International Business Machines CorporationInventors: Luiz C. Alves, Luis A. Lastras-Montano, Patrick J. Meaney, Eldee Stephens, Lisa C. Gower
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Patent number: 8484543Abstract: Error correction is selectively applied to data, such as repair data to be stored in a fusebay for BIST/BISR on an ASIC or other semiconductor device. Duplicate bit correction and error correction code state machines may be included, and selectors, such as multiplexers, may be used to enable one or both types of correction. Each state machine may include an indicator, such as a “sticky bit,” that may be activated when its type of correction is encountered. The indicator(s) may be used to develop quality and yield control criteria during manufacturing test of parts including embodiments of the invention.Type: GrantFiled: August 8, 2011Date of Patent: July 9, 2013Assignee: International Business Machines CorporationInventors: Darren L. Anand, Kevin W. Gorman, Michael R. Ouellette, Michael A. Ziegerhofer
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Patent number: 8484522Abstract: An apparatus, system, and method are disclosed for bad block remapping. A bad block identifier module identifies one or more data blocks on a solid-state storage element as bad blocks. A log update module writes at least a location of each bad block identified by the bad block identifier module into each of two or more redundant bad block logs. A bad block mapping module accesses at least one bad block log during a start-up operation to create in memory a bad block map. The bad block map includes a mapping between the bad block locations in the bad block log and a corresponding location of a replacement block for each bad block location. Data is stored in each replacement block instead of the corresponding bad block. The bad block mapping module creates the bad block map using one of a replacement block location and a bad block mapping algorithm.Type: GrantFiled: August 2, 2012Date of Patent: July 9, 2013Assignee: Fusion-io, Inc.Inventors: David Flynn, John Strasser, Jonathan Thatcher, David Atkisson, Michael Zappe, Joshua Aune, Kevin Vigor
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Publication number: 20130173973Abstract: A device includes memory banks, each having a plurality of memory cells with respective error data output circuits. Each of the error data output circuits outputs first to M-th (M is an integer of 2 or more) error data according to first to M-th data retrieved from first to M-th memory cell groups selected from its corresponding memory bank. A test control circuit has first error data synthesis circuits and second to (M+1)-th error data synthesis circuits, each of which synthesizes the first to M-th error data from a corresponding error data output circuit and outputs the synthesized data as first test data. Each of the error data synthesis circuits synthesizes m-th (m is an integer of from 1 to M) error data from the error data output circuits and outputs the synthesized data as (m+1)-th test data.Type: ApplicationFiled: December 19, 2012Publication date: July 4, 2013Applicant: Elpida Memory, Inc.Inventor: Elpida Memory, Inc.
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Publication number: 20130173970Abstract: A memory device with background built-in self-testing (BBIST) includes a plurality of memory blocks; a memory buffer to offload data from one of the plurality of memory blocks temporarily; and a memory block stress controller to control a stress test applied to the one of the memory blocks when the data is temporarily offloaded on the memory buffer. The stress test tests for errors in the one of the plurality of the memory blocks.Type: ApplicationFiled: January 2, 2013Publication date: July 4, 2013Applicant: MOSYS, INC.Inventors: Bendik Kleveland, Dipak K. Sikdar, Rajesh Chopra, Jay Patel
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Publication number: 20130173971Abstract: A boundary scan chain for stacked memory. An embodiment of a memory device includes a system element and a memory stack including one or more memory die layers, each memory die layer including input-output (I/O) cells and a boundary scan chain for the I/O cells. A boundary scan chain of a memory die layer includes a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including a first scan logic multiplexer a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and a decoder to provide command signals to the boundary scan chain.Type: ApplicationFiled: December 29, 2011Publication date: July 4, 2013Inventor: David J. Zimmerman
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Publication number: 20130173972Abstract: A system and method for early detection and reporting of an impending NAND Flash device plane failure. Each time that a data unit is retrieved from a NAND Flash array the number of bits in error and the memory location associated with the errors is observed. if the number of bits in error or the error rate for a memory location exceeds a threshold of the number of bits in error per data, retrieval, or number of bits in error per data unit per unit time, a NAND Flash plane failure Patrol Read operation is performed at the memory location, regardless of where in the cycle the Patrol Read function is in a scrub of the overall NAND Flash device. The NAND Flash plane failure Patrol Read is repeated for a number of cycles on the NAND Flash plane in question.Type: ApplicationFiled: February 14, 2012Publication date: July 4, 2013Inventor: Robert Kubo
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Publication number: 20130166973Abstract: A storage-medium diagnosis includes a storage unit that stores therein respective diagnosis results of subregions of a storage region of a storage medium; a higher-access executing unit that accesses a region corresponding to access request from a higher-level device, and stores a result of the access as a diagnosis result in the storage unit; a diagnosis-region identifying unit that identifies a diagnosis region to be diagnosed next on the basis of the respective diagnosis results of the subregions stored in the storage unit; and a diagnosis executing unit that accesses and diagnoses the diagnosis region identified by the diagnosis-region identifying unit, and stores a result of the diagnosis in the storage unit. The storage-medium diagnosis can reduce the time used for diagnosis of the storage medium and suppress degradation in performance even during operation.Type: ApplicationFiled: February 19, 2013Publication date: June 27, 2013Applicant: FUJITSU LIMITEDInventor: FUJITSU LIMITED
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Patent number: 8473809Abstract: Non-volatile storage devices and techniques for operating non-volatile storage are described herein. One embodiment includes accessing “n” pages of data to be programmed into a group of non-volatile storage elements. The “n” pages are mapped to a data state for each of the non-volatile storage elements based on a coding scheme that evenly distributes read errors across the “n” pages of data. Each of the non-volatile storage elements in the group are programmed to a threshold voltage range based on the data states to which the plurality of pages have been mapped. The programming may include programming the “n” pages simultaneously. In one embodiment, mapping the plurality of pages is based on a coding scheme that distributes a significant failure mode (for example, program disturb errors) to a first of the pages and a significant failure mode (for example, data retention errors) to a second of the pages.Type: GrantFiled: July 19, 2010Date of Patent: June 25, 2013Assignee: SanDisk Technologies Inc.Inventors: Jun Wan, Alex Mak, Tien-Chien Kuo, Yan Li, Jian Chen
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Publication number: 20130159797Abstract: Disclosed are apparatus and techniques for indicating health of a memory system having a controller and nonvolatile memory array. In one embodiment, the invention pertains to a method for indicating health of a removable memory system that is removably coupled with a host device. After the memory system is coupled with a host device, a first health status is output via an external electrical or mechanical interface of the memory system. One or more health metrics of the memory system are monitored. After a first predefined limit is reached with respect to the one or more health metrics, a second health status is output via the external electrical or mechanical interface of the memory system. The first health status differs from the second health status.Type: ApplicationFiled: December 20, 2011Publication date: June 20, 2013Applicant: SANDISK TECHNOLOGIES INC.Inventors: Yong Peng, Ka Ian Yung, Xiangyang Miao, Arjun Hary
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Patent number: 8468399Abstract: A cache logic verification apparatus includes an acquisition unit that acquires an ongoing process in each stage of a stepped operation to judge whether data to be read in a cache memory holding a copy of contents of a part of a memory is held or not, and a comparator that compares the ongoing process in each stage acquired by the acquisition unit with a scheduled ongoing process predetermined in each stage of the stepped operation.Type: GrantFiled: August 31, 2009Date of Patent: June 18, 2013Assignee: Fujitsu LimitedInventor: Eiji Furukawa