Abstract: A data processor having a plurality of data processing cores configured to disable cores found defective by a self-test.

Abstract: A test mode signal generation circuit includes a pre-decoder block configured to output first and second control signals and test address signals in response to first and second address signals, and a signal generation block configured to decode the test address signals in response to the first control signal and generate first and second test mode group signals each including a plurality of test mode signals.

Abstract: Testing methods in a pre-programmed memory device after it has been assembled into a final customer platform include issuing a self-test command to the memory device, the memory device reporting results of a self-test of pre-programmed data executed responsive to receiving the self-test command, and issuing a self-repair command responsive to the results indicating repair of the pre-programmed data is needed.

Abstract: An apparatus for detecting hard errors in a circuit includes a storage device and a processing circuit. The storage has stored therein test data and normal data. The processing circuit includes combinational logic in series with at least one set of input latches and at least one set of output latches. The apparatus includes a test control module configured to control the processing circuit to halt a flow of normal data through the processing circuit and run the test data through the processing circuit while subjecting the processing circuit to a stress condition.

Abstract: A chip with a built-in self-test (BIST) component capable of testing the linearity of an ADC is described herein. The BIST component uses hardware registers to facilitate a sliding histogram technique to save space on the chip. A subset of detected digital codes are analyzed, and DNL and INL calculations are performed by a controller to determine whether any of the digital codes in the subset exceed maximum or minimum DNL and INL thresholds. New digital codes being detected by the ADC are added to the subset as lower-value digital codes are pushed out of the subset, maintaining the same number of digital codes being analyzed as the subset moves from lower codes detected during lower voltages to higher codes detected at higher voltages. A synchronizer and pointer ensure that the subset moves through the digital codes at the same rate as the analog input ramp source.

Abstract: A transmitting device includes a parallel data generation unit and a transmitting unit. The parallel data generation unit generates first serial data and second serial data from a data packet, converts the first serial data and second serial data respectively into first parallel data and second parallel data, transmits the first parallel data and second parallel data respectively through first and second parallel transmission paths, and performs the transmission of the first parallel data and the transmission of the second parallel data in parallel. The transmitting unit receives the first parallel data and second parallel data respectively through the first and second parallel transmission paths, re-converts the first parallel data and second parallel data respectively into the first serial data and second serial data, and transmits the first serial data and second serial data to a receiving device respectively through first and second serial transmission paths.

Abstract: Embodiments of systems and methods for detecting errors that occur in association with an access to a memory and providing an associated error status are presented herein. According to one embodiment, an access to a memory may be received, where the access comprises a request tag. A request parity is determined based on the request tag and a stored tag and a stored parity associated with the request tag are also determined. An error correction status is determined based on the stored tag and the stored parity associated with the request tag. Additionally, a parity hotness is determined by comparing the request parity and the stored parity and a tag hotness is determined by comparing the request tag and the stored tag. An error status associated with the access is determined based on the parity hotness, the tag hotness and the error correction status.

Abstract: Systems and methods for testing non-volatile storage devices are disclosed that provide functionality to control when testing of the non-volatile storage device is performed. In one embodiment, information stored in persistent memory indicates whether testing is enabled or disabled. For example, the testing information may indicate that testing is to be performed upon a first initialization of a non-volatile storage device, but not in connection with subsequent power-up events. Furthermore, functionality is disclosed for re-running and/or bypassing testing of the non-volatile storage device.

Abstract: In one embodiment, the method includes performing a read operation on a memory, and determining, by a memory controller, whether to perform a reliability verification read operation based on a count value and a reference value. The count value is based on a number of read commands issued by the memory controller to the memory, and the reliability verification read operation is for reading data from at least one memory cell associated with at least one unselected word line in the memory. An unselected word line is a word line not selected during the read operation. The method further includes performing the reliability verification read operation for the at least one unselected word line based on the determining.

Abstract: A method is provided for operating a volatile memory device. The method includes performing a first initialization operation for the volatile memory device based on a boot code received from an external memory controller, storing the boot code in an internal register, reading the boot code stored in the internal register based on a first signal received from the external memory controller when the first initialization operation is not normally performed, and performing a second initialization operation for the volatile memory device based on the boot code read from the internal register.

Abstract: A controller of a storage control apparatus creates a fixed value, which is one or higher values conforming to a prescribed data pattern, with respect to first data, which is smaller than the size of a storage area of a storage device, creates a guarantee code related to a data area comprising the first data and the fixed value, and writes the data group comprising the data area and the guarantee code to the storage area. The controller reads a data group from the storage area, and determines whether or not more errors than the number of errors correctable by the guarantee code are included in this data group. In a case where the result of this determination is affirmative, the controller determines whether or not an error exists in the fixed value inside the data group.

Abstract: Methods of performing an internal diagnostic for a NAND configured memory device include storing data in a data cache coupled to an array of memory cells arranged in a NAND configuration, wherein the data stored in the data cache corresponds to at least one diagnostic function; performing a decode operation on the data stored in the data cache, wherein the decode operation generates a diagnostic function command for testing internal functions of the NAND configured memory device; and providing the decoded diagnostic function command to a state machine of the NAND configured memory device adapted to perform the decoded diagnostic function command.

Abstract: Correlated failure distribution for memory arrays having different groupings of memory cells is estimated by constructing memory unit models for the groupings based on multiple parameters, establishing failure conditions of the memory unit model using fast statistical analysis, calculating a fail boundary of the parameters for each memory unit model based on its corresponding failure conditions, and constructing memory array models characterized by the fail boundaries. Operation of a memory array model is repeatedly simulated with random values of the parameters assigned to the memory cells and peripheral logic elements to identify memory unit failures for each simulated operation. A mean and a variance is calculated for each memory array model, and an optimal architecture can thereafter be identified by selecting the grouping exhibiting the best mean and variance, subject to any other circuit requirements such as power or area.

Abstract: A method of controlling a nonvolatile semiconductor memory includes checking, at a first interval period, an error count of data stored in a first group, the first group including a plurality of blocks/units, and when a first block/unit in the first group satisfies a first condition, assigning the first block/unit to a second group. The method includes checking, at a second interval period, an error count of data stored in the second group, the second interval period being shorter than the first interval period, and when a second block/unit in the second group satisfies a second condition, moving data stored in the second block/unit to an erased block/unit in which stored data is erased among the plurality of blocks/units.

Abstract: The application discloses systems that can include a monitoring module that is operative to provide an event indicator of an event occurring on a hard-disk drive. The systems can include a recording module that is operative to create an event record based on a logging instruction to log the event indicator. The systems can include an event linkage module that is operative to link the event record to a hard-disk drive activity indicator. The systems can include an error log formatting module that is operative to format the event record and a hard-disk drive activity indicator into a hard-disk drive error log. The systems can include a configuration module to set configuration flags and/or values. The error log can be stored on various areas of the hard-disk drive. The application also discloses related methods.

Abstract: Implementations include systems, methods and/or devices suitable for use in a memory system that may enhance the performance of error control codes used to improve the reliability with which data can be stored and read. Some implementations include systems, methods and/or devices enabled to generate and utilize soft information for decoding encoded data read from a storage medium. More specifically, some implementations utilize a collection of characterization vectors that include soft information values for bit-tuples that may be read from the storage medium for various combinations of the storage medium characterization parameter values. Some implementations are enabled to determine and utilize read comparison signal values associated with one or more storage medium characterization parameter values.

Abstract: A method for operating a memory includes storing data in a plurality of analog memory cells that are fabricated on a first semiconductor die by writing input storage values to a group of the analog memory cells. After storing the data, multiple output storage values are read from each of the analog memory cells in the group using respective, different threshold sets of read thresholds, thus providing multiple output sets of the output storage values corresponding respectively to the threshold sets. The multiple output sets of the output storage values are preprocessed by circuitry that is fabricated on the first semiconductor die, to produce preprocessed data. The preprocessed data is provided to a memory controller, which is fabricated on a second semiconductor die that is different from the first semiconductor die. so as to enable the memory controller to reconstruct the data responsively to the preprocessed data.

Abstract: A magnetic recording disk drive determines the locations of defective bits in a failed data sector, and allows for the error correction code (ECC) to correctly decode the data from the sector. After a sector has failed decoding, the digitized waveform and the read channel state from the failed sector are stored in memory. A nondata pattern is written to the failed sector and read back to determine the locations of the defective data bits in the failed sector, which are then used to update the read channel state. The data pattern from the failed sector, with the identified bit error locations, is attempted to be decoded. If the decoding is successful then the sector is marked as bad and the correctly decoded data pattern is written to a different region of the disk, for example physical sectors specifically intended for use as spare sectors.

Abstract: A memory device includes a command decoder for generating a test selection code and a test setup data by decoding an external command and an external address, a non-volatile memory for storing an internal setup data, a counter for generating an internal selection code by counting a clock, a first selector for selecting the test selection code during a test mode operation, selecting the internal selection code during a boot-up operation, and transferring the selected selection code through a selection code transfer bus, a second selector for selecting the test setup data during the test mode operation, selecting the internal setup data that is outputted from the non-volatile memory during the boot-up operation, and transferring the selected selection code through a setup data transfer bus; and setup circuits for performing a setup operation based on the information transferred through the selection code transfer bus and the setup data transfer bus.

Abstract: A test method for a memory having first and second cell arrays, first compressed data obtained by compressing output data of the first cell array and output data of the second cell array is outputted. When the first compressed data represents that a fail exists, output data of one of the first and second cell arrays is locked as normal data, and second compressed data obtained by compressing the normal data and output data of the other of the first and second cell arrays is outputted.

Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.

Abstract: Aspects of the invention provide for decreasing the power supply demand during built-in self test (BIST) initializations. In one embodiment, a BIST architecture for reducing the power supply demand during BIST initializations, includes: a chain of slow BIST I/O interfaces; a chain of fast BIST I/O interfaces, each fast BIST I/O interface connected to a slow BIST I/O interface; and a BIST engine including a burst staggering latch for controlling a multiplexor within each of the slow BIST I/O interfaces, wherein the burst staggering latch, for a first burst signal, staggers the first burst signal to each of the slow BIST I/O interfaces, such that, during a first clock cycle, only a first slow BIST I/O interface receives the first burst signal.

Abstract: A built-in self-test (BIST) circuit to test one or more memory blocks on an integrated circuit. The one or more memory blocks further includes a first memory block and a second memory block A built-in soft-repair controller (BISoR) is provided to soft repair the one or more memory blocks. The BIST circuit in conjunction with the BISoR is configured to test and soft repair the first memory block before performing test and soft repair of the second memory block.

Abstract: A method and a system that checks software and includes a hooking module that collects process control block (PCB) information corresponding to each process on a kernel by being executed at the time of booting a system. In addition, the system includes a safety service module that searches and defends the defects of the process by being inserted into a memory region of the process based on the collected PCB information.

Abstract: A memory card includes a memory cell, a connector, a controller, and firmware. The memory cell can switch between a plurality of states. The connector can be connected to an external device and exchange signals including commands and data with the external device. The controller exchanges signals with the connector, analyzes a received signal, and accesses the memory cell to record, retrieve or modify data based on the analysis result. The firmware is located within the controller, controls the operation of the controller, and can be set to a test mode or a user mode. When the firmware receives a test command from the external device and the firmware is set to the test mode, the firmware performs a defect test on the memory cell and transmits the result of the defect test to the external device through the connector.

Abstract: The present invention provides a memory architecture and associated serial direct access (SDA) circuit. The memory architecture includes a memory of a parallel interface and a serial direct access (SDA) circuit. The SDA circuit includes an enable pin, a serial pin and an auto-test module. The enable pin receives an enable bit, wherein the SDA circuit is selectively enabled and disabled in response to the enable bit. When the SDA circuit is enabled, the serial pin sequentially relaying a plurality of serial bits, such that each of the serial bits is associated with one of parallel pins of the parallel interface; in addition, the auto-test module can perform a built-in test of the memory associated with the serial bits.

Abstract: A system that includes a multiplicity of flash memory cells; a reading apparatus; a writing apparatus for writing logical data from temporary memory into individual flash memory cells from among said multiplicity of flash memory cells, thereby to generate a physical representation of the logical data including a plurality of physical levels at least some of which represent, to said reading apparatus, at least one bit-worth of said logical data; and a special cell marking apparatus operative to store an earmark in at least an individual one of said multiplicity of flash memory cells for subsequent special treatment.

Abstract: A system includes a first device, a first storage element, a comparator and a second device. The first device is configured to test memory cells in an array of memory cells to detect defective memory cells. The defective memory cells include a first memory cell and a second memory cell. The first storage element is configured to store a first address of the first memory cell. The comparator is configured to compare a second address of the second memory cell to the first address.

Abstract: A method for checking the functional ability of a memory element having a stack memory, wherein the stack memory occupies a defined region within the memory element. A stack memory pointer is defined, which displays, in the form of an address, a stack memory position, from which data are currently being removed or to which data are currently being written. In the memory element, a section of defined length arranged outside a memory region to be checked is delimited and used as an auxiliary memory; the current address of the stack memory pointer is stored before the start of a test program for checking the memory element and the stack memory pointer is then assigned an address associated with the auxiliary memory, so that during the test program the auxiliary memory is used as working memory; and after terminating the test program the stack memory pointer is reassigned the address of that position, which it displayed before the start of the test program.

Abstract: An embodiment is a technique to classify a flash device. Test data to a flash device are accessed in unscramble and scramble modes under a test mode. Error correcting code (ECC) results are recorded on the test data for the unscramble and scramble modes. A device quality figure is calculated based on the ECC results for the unscramble and scramble modes. The flash device is classified using the device quality figure.

Abstract: Disclosed are a flash memory device and flash memory programming method that equalizes a wear-level. The flash memory device includes a memory cell array, an inversion determining unit to generate a programming page through inverting or not inverting a data page based on a number of ‘1’s and ‘0’s in the data page, a programming unit to store the generated programming page in the memory cell array; and a data verifying unit to read the programming page stored in the memory cell array, to restore the data page from the programming page according to whether an error exists in the read programming page, and to output the restored data page, and thereby can equalize a wear-level of a memory cell.

Abstract: A method and apparatus for operation of a memory module for storage of a data word is provided. The apparatus includes a memory module having a set of paired memory devices including a first memory device to store a first section of a data word and a second memory device to store a second section of the data word when used in failure free operation. The apparatus may further include a first logic module to perform a write operation by writing the first and second sections of the data word to both the first memory device and the second memory device upon the determination of certain types of failure. The determination may include that a failure exists in the word section storage of either the first or second memory devices but that no failures exist in equivalent locations of word section storage in the two memory devices.

Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where a plurality of memories requiring different testing conditions are incorporated in an SOC. The pBIST Read Only Memory storing the test setup data is organized to eliminate multiple instances of test setup data for similar embedded memories.

Abstract: According to one embodiment of the present disclosure, an approach is provided in which an interface node selects a logical block address that corresponds to a contiguous memory location located on a storage device that is accessible by multiple interface nodes. The interface node retrieves a logical block address status indicator from a shared memory area and determines, based upon the logical block status indicator, whether the logical block address is utilized by a different interface node. If the logical block address is not utilized by a different interface node, the interface node tests the corresponding contiguous memory location.

Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module. Test data comparison is performed in a distributed data logging architecture to minimize the number of interconnections between the distributed data loggers and the pBIST.

Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories may be operating at a voltage domain different from the voltage domain of the pBIST. A plurality of buffer and synchronizing registers are used to avoid meta stable conditions caused by the time delays introduced by the voltage shifters required to bridge the various voltage domains.

Abstract: Techniques for a post-write read are presented. In an exemplary embodiment, a combined simultaneous sensing of multiple word lines is used in order to identify a problem in one or more of these word lines. That is, sensing voltages are concurrently applied to the control gates of more than one memory cell whose resultant conductance is measured on the same bit line. The combined sensing result is use for measuring certain statistics of the cell voltage distribution (CVD) of multiple word lines and comparing it to the expected value. In case the measured statistics are different than expected, this may indicate that one or more of the sensed word lines may exhibit a failure and more thorough examination of the group of word lines can be performed.

Abstract: A repair control circuit and a semiconductor integrated circuit using the same, which can reduce test time, are provided. The semiconductor integrated circuit includes a plurality of memory blocks in which a plurality of word lines are arranged, a plurality of word line drivers driving one or more of the plurality of word lines in response to a plurality of memory block selection signals, and a repair control circuit determining whether to perform a repair through comparison of repair addresses generated in response to surplus addresses and the plurality of memory block selection signals with external addresses.

Abstract: A smart memory system preferably includes a memory including one or more memory chips, and a processor including one or more memory processor chips. The system may include a smart memory controller capable of performing a bit error rate built-in self test. The smart memory control may include bit error rate controller logic configured to control the bit error rate built-in self test. A write error rate test pattern generator may generate a write error test pattern for the bit error rate built-in self test. A read error rate test pattern generator may generate a read error test pattern for the built-in self test. The smart memory controller may internally generate an error rate timing pattern, perform built-in self test, measure the resulting error rate, automatically adjust one or more test parameters based on the measured error rate, and repeat the built-in self test using the adjusted parameters.

Abstract: A method and circuit for testing a multi-chip package is provided. The multi-chip package includes at least a memory chip, and the memory chip includes a number of memory cells. The method includes performing a normal read operation on the memory cells to check if data read from the memory cells is the same with preset data in the memory cells; and performing a special read operation on the memory cells to check if data read from the memory cells is the same with an expected value, wherein the expected value is independent from data stored in the memory cells.

Abstract: A semiconductor device includes a first CPU, a second CPU having a configuration that is the same as or comparable to a configuration of the first CPU, and a comparator that compares an output of the first CPU with an output of the second CPU. The second CPU is made so as to have a lower operating margin than the first CPU. By supplying a same signal to the first CPU and the second CPU and then detecting a mismatch between the outputs of the first CPU and the second CPU as a result of comparison, the abnormality is predicted. The semiconductor device includes a reset control circuit that resets the device when the result of comparison by the comparator indicates an error.

Abstract: A resistive memory device and a system and method for testing the resistive memory device are provided. The resistive memory device includes a plurality of bit lines comprising at least one dummy bit line to which a plurality of resistive memory cells are connected, a conducting wire connected to the dummy bit line, a first switching element positioned between the dummy bit line and an external device outside the resistive memory device, and a second switching element positioned between the conducting wire and the external device. Accordingly, the operational reliability of the resistive memory device may be increased.

Abstract: A system including a memory controller configured to identify a first memory cell of a first plurality of memory cells as defective and to store information about the first memory cell in a second memory cell of a second plurality of memory cells. The second plurality of memory cells is configured to store data at a lower density than the first plurality of memory cells. In response to (i) reading data from the first plurality of memory cells and (ii) the first memory cell of the first plurality of memory cells having been identified as defective, the memory controller is configured to read the information about the first memory cell stored in the second memory cell and to determine a location of the first memory cell in the first plurality of memory cells.

Abstract: In a method of executing a BIST operation on IC memory arrays having a common BIST control unit, a first BIST sequence is initiated. Each address for the arrays is incremented. The BIST control unit receives a signal indicating a maximum valid address in the array is reached, receiving a plurality of maximum valid addresses, which are recorded. A single relatively highest maximum valid address is determined. A first mode, which prevents BIST testing, is engaged in each array having reached the maximum valid address. A second BIST sequence is initiated based on having received the signal indicating a maximum valid address is reached from all the arrays connected to the common BIST control unit. An address count is decremented from the single relatively highest maximum valid address. The first mode is disengaged for each array as the address count reaches each of the maximum valid addresses during the decrementing.

Abstract: A method for recording at least one information block in a first volatile memory external to a circuit, a first digital signature being calculated based on information and data internal to the circuit and a second digital signature being calculated based on first signatures of a group of information blocks and on a digital quantity internal to the circuit and assigned to said group. A method for checking the content of an information block recorded by this recording method.

Abstract: Systems and methods are provided for selectively retiring blocks based on refresh events of those blocks. In addition to refresh events, other criteria may be applied in making a decision whether to retire a block. By applying the criteria, the system is able to selectively retire blocks that may otherwise continue to be refreshed.

Abstract: A flash interface error injector for end-of-life testing of a flash-based array includes a plurality of error injection logic blocks that are implemented by one or more processors. Each of the plurality of error injection logic blocks corresponds with a respective flash channel. The flash injector also includes a bit flip probability logic that identifies one or more bits to be flipped.

Abstract: A flash interface error injector for end-of-life testing of a flash-based array includes a plurality of error injection logic blocks that are implemented by one or more processors. Each of the plurality of error injection logic blocks corresponds with a respective flash channel. The flash injector also includes a bit flip probability logic that identifies one or more bits to be flipped.

Abstract: A method and system for managing storage of one or more data blocks in a programmable data storage device is provided. A data storage controller partitions each of multiple data blocks into multiple sub data blocks comprising a number of bits based on one or more index value descriptors. The data storage controller generates transition vectors from each of the sub data blocks by applying one or more transition functions. The data storage controller encodes one of the transition vectors for each sub data block for obtaining a residual sub data block comprising a reduced number of bits, thereby resulting in increased bit space. The data storage controller generates a composite data block by merging each residual sub data block. The composite data block is configurable for writing to one or more regions in the programmable data storage device free from a disturbance caused by write operations to other regions.

Abstract: A data communication apparatus includes a data generation unit, a control register, a memory, a memory address generation unit, a failure setting unit, and a transmission unit. The data generation unit generates data. The control register outputs an enable signal and a test control signal. In the memory, pseudo failure data is written during the test. The pseudo failure data is used to modify generated data to data having a pseudo failure. The memory address generation unit generates a readout address of the memory during the test on the basis of the enable signal and the test control signal. The failure setting unit reads out pseudo failure data from the memory using a readout address generated by the memory address generation unit, and modifies the generated data to data having the pseudo failure. The transmission unit transmits the data having the pseudo failure modified by the failure setting unit.