Memory Testing Patents (Class 714/718)
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Patent number: 8914690Abstract: A multi-core processor having a cache, an interconnect system selectively connecting the cache to individual cores, and a interconnect control whereby selected cores are disabled.Type: GrantFiled: June 11, 2014Date of Patent: December 16, 2014Assignee: Pact XPP Technologies AGInventors: Martin Vorbach, Robert Munch
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Patent number: 8914687Abstract: A method is provided in which a first error test may be performed on a memory that includes an integrated error correcting code (ECC) portion. The functionality of the ECC portion may be bypassed in the first error test. A second error test may be performed on the memory, where the second error test includes testing the functionality of the ECC portion. Also provided is an apparatus including a memory device and an error correcting code (ECC) circuit. The apparatus also includes a first switching device adapted to select a first input signal or a second input signal and a second switching device adapted to select one of a signal from the memory device or a signal from a portion of the ECC circuit. Also provided are computer readable storage devices encoded with data for adapting a manufacturing facility to create the apparatus and for adapting a processor to perform the method above.Type: GrantFiled: April 15, 2011Date of Patent: December 16, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Spencer M. Gold, Arun B. Hegde
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Patent number: 8910021Abstract: A method for data storage in a memory including multiple memory cells arranged in blocks, includes storing first and second pages in respective first and second groups of the memory cells within a given block of the memory. A pattern of respective positions of one or more defective memory cells is identified in the first group. The second page is recovered by applying the pattern identified in the first group to the second group of the memory cells.Type: GrantFiled: October 22, 2013Date of Patent: December 9, 2014Assignee: Apple Inc.Inventors: Ofir Shalvi, Naftali Sommer, Oren Golov
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Patent number: 8910001Abstract: Method for testing a memory under test (1) including a plurality of memory cells and a Memory Built-In Self-Test Engine (2) connectable to a memory under test. The MBIST engine (2) is arranged to generate appropriate addressing and read and/or write operations to the memory under test (1). The MBIST engine (2) is connected to a March Element Stress register (MESR) (3), a generic march element register (GMER) (4), and a Command Memory (5). The GMER (4) specifies one of a set of Generic March Elements (GME), and the MESR (3) specifies the stress conditions to be applied. Only a few GMEs are required in order to specify most industrial algorithms. The architecture is orthogonal and modular, and all speed related information is contained in the GME. In addition, only little memory is required for the specification of the test, providing a low implementation cost, yet with a high flexibility.Type: GrantFiled: March 16, 2011Date of Patent: December 9, 2014Assignee: Technische Universiteit DelftInventors: Said Hamdioui, Zaid Al-Ars, Georgi Nedeltchev Gaydadjiev, Adrianus van de Goor
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Patent number: 8910000Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to read or write performance of a phase change memory.Type: GrantFiled: May 17, 2012Date of Patent: December 9, 2014Assignee: Micron Technology, Inc.Inventor: Ferdinando Bedeschi
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Publication number: 20140359383Abstract: Integrated circuits with memory built-in self-test (BIST) logic and methods of testing using the same are disclosed. The method includes setting an address window for locating defects in a memory array. The method further includes comparing output data of the memory array to expected data to determine that a defect exists at location “M” in the memory array within the address window. The method further includes storing, in registers, the address M and a resultant bit fail vector associated with the location “M” of the defect found in the memory array. The method further includes resetting the registers to a null value and resetting the address window with a new minimum and maximum address pair, to compare the output data of the memory array to the expected data within the reset address window which excludes address M.Type: ApplicationFiled: May 28, 2013Publication date: December 4, 2014Inventors: Geovanny Rodriguez, Brian J. Vincent, Timothy J. Vonreyn
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Patent number: 8904097Abstract: For each of a plurality of locations in flash memory, a number of pulses required to change a value stored in that location is obtained. From the plurality of locations, a location to write to is selected using the obtained number of pulses. The selected location is written to.Type: GrantFiled: January 31, 2014Date of Patent: December 2, 2014Assignee: SK hynix memory solutions inc.Inventors: Rajiv Agarwal, Marcus Marrow
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Patent number: 8904249Abstract: A programmable Built In Self Test (BIST) system used to test embedded memories where the memories may be operating at a clock frequency higher than the operating frequency of the BIST. A plurality of BIST memory ports are used to generate multiple memory test instructions in parallel, and the parallel instructions are then merged to generate a single memory test instruction stream at a speed that is a multiple of the BIST operating frequency.Type: GrantFiled: April 14, 2012Date of Patent: December 2, 2014Assignee: Texas Instruments IncorporatedInventors: Raguram Damodaran, Naveen Bhoria
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Patent number: 8904250Abstract: Testing methods in a pre-programmed memory device after it has been assembled into a final customer platform include issuing a self-test command to the memory device, the memory device reporting results of a self-test of pre-programmed data executed responsive to receiving the self-test command, and issuing a self-repair command responsive to the results indicating repair of the pre-programmed data is needed.Type: GrantFiled: February 14, 2013Date of Patent: December 2, 2014Assignee: Micron Technology, Inc.Inventors: Francesco Falanga, Victor Tsai
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Publication number: 20140351662Abstract: A read only memory (ROM) with redundancy and methods of use are provided. The ROM with redundancy includes a programmable array coupled to a repair circuit having one or more redundant repairs. The one or more redundant repairs include a word address match logic block, a data I/O address, and a tri-state buffer. The word address match logic block is provided to the tri-state buffer as a control input and the data I/O address is provided to the tri-state buffer as an input. An output of the tri-state buffer of each redundant repair is provided as a first input to one or more logic devices. One or more data outputs of a ROM bit cell array is provided as a second input to a respective one of the one or more logic devices.Type: ApplicationFiled: August 7, 2014Publication date: November 27, 2014Inventors: George M. BRACERAS, Albert M. CHU, Kevin W. GORMAN, Michael R. OUELLETTE, Ronald A. PIRO, Daryl M. SEITZER, Rohit SHETTY, Thomas W. WYCKOFF
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Publication number: 20140344635Abstract: An ActiveTest solution for memory is disclosed which can search for memory errors during the operation of a product containing digital memory. The ActiveTest system tests memory banks that are not being accessed by normal memory users in order to continually test the memory system in the background. When there is a conflict between the ActiveTest system and a memory user, the memory user is generally given priority.Type: ApplicationFiled: January 21, 2014Publication date: November 20, 2014Inventors: Sundar Iyer, Shadab Nazar, Sanjeev Joshi
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Methods and apparatus for soft data generation for memory devices using decoder performance feedback
Patent number: 8892966Abstract: Methods and apparatus for soft data generation for memory devices using decoder performance feedback. At least one soft data value is generated in a memory device, by obtaining performance feedback from a decoder; obtaining an error statistic based on the performance feedback; and generating the at least one soft data value based on the obtained error statistic. The performance feedback comprises one or more of decoded bits, a number of erroneous bits based on data decoded by the decoder and a number of unsatisfied parity checks.Type: GrantFiled: September 30, 2009Date of Patent: November 18, 2014Assignee: LSI CorporationInventors: Erich F. Haratsch, Milos Ivkovic, Victor Krachkovsky, Nenad Miladinovic, Andrei Vityaev, Clifton Williamson, Johnson Yen -
Patent number: 8887033Abstract: Monitors, architectures, systems and methods for determining one or more quality characteristics of a storage channel. The monitor generally includes an iterative decoder configured to decode data from the storage channel and generate information relating to a quality metric of the storage channel and/or the iterative decoder, a memory configured to store a threshold value for the quality metric, and a comparator configured to compare the threshold value with a measured value of the quality metric. The monitor enables accurate determination of storage channel quality without use of conventional Reed-Solomon metrics.Type: GrantFiled: August 23, 2013Date of Patent: November 11, 2014Assignee: Marvell International Ltd.Inventors: Nedeljko Varnica, Gregory Burd
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Patent number: 8880375Abstract: Provided is a test apparatus that tests a device under test having a plurality of output terminals. The test apparatus comprises an executing section that executes a test command sequence for testing the device under test; a storage section that stores a plurality of pieces of setting data designating one or more output terminals among the plurality of output terminals; a detecting section that detects whether a value of an output signal from an output terminal designated by one of the pieces of setting data matches an expected value; and a selecting section that selects different pieces of setting data in the storage section when at least two detection commands, which change execution sequencing of the test command sequence according to the detection results of the detecting section, are executed, and supplies the selected pieces of setting data to the detecting section.Type: GrantFiled: February 11, 2011Date of Patent: November 4, 2014Assignee: Advantest CorporationInventors: Kuniyuki Kaneko, Naoyoshi Watanabe
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Patent number: 8880964Abstract: A programming process evaluates NAND strings of a block to detect a defective NAND string, e.g., a NAND string with a defective storage element. Status bits can be stored which identify the defective NAND string. Original data which is to be written in the NAND string is modified so that programming of the defective NAND string does not occur. For example, a bit of write data which requires a storage element in the defective NAND string to be programmed to a higher data state is modified (e.g., flipped) so that no programming of the storage element is required. Subsequently, when a read operation is performed, the flipped bits are flipped back to their original value, such as by using error correction code decoding. In an erase process, a count of defective NAND strings is made and used to adjust a pass condition of a verify test.Type: GrantFiled: September 19, 2012Date of Patent: November 4, 2014Assignee: SanDisk Technologies Inc.Inventors: Jun Wan, Bo Lei, Feng Pan, Yongke Sun
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Patent number: 8880979Abstract: A method and system are disclosed in which a first non-volatile memory includes blocks that store data, and a second memory that stores overhead information related to the blocks storing the data. The amount of the second memory storing the overhead information related to the at least one block of the plurality of blocks is varied.Type: GrantFiled: May 31, 2013Date of Patent: November 4, 2014Assignee: Micron Technology, Inc.Inventors: Giovanni Campardo, Stefano Corno, Gian Pietro Vanalli, Manuela Scognamiglio, Danilo Caraccio, Federico Tiziani, Massimiliano Magni, Andrea Ghilardelli
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Patent number: 8880978Abstract: A method begins by a processing module encoding data based on a decode threshold parameter and a pillar width parameter to produce a set of encoded data slices and selecting a local area network (LAN) pillar width value of encoded data slices of the set of encoded data slices for storage in LAN available memories, wherein the LAN pillar width value is based on the decode threshold parameter, the pillar width parameter, and quantities of the LAN available memories. The method continues with the processing module selecting a wide area network (WAN) pillar width value of encoded data slices of the set of encode data slices for storage in a dispersed storage network (DSN) memory of a wide area network, wherein the WAN pillar width value is based on the decode threshold parameter and the pillar width parameter.Type: GrantFiled: March 6, 2012Date of Patent: November 4, 2014Assignee: Cleversafe, Inc.Inventors: Jason K. Resch, Gary W. Grube, Timothy W. Markison
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Patent number: 8873288Abstract: Techniques for a post-write read are presented. In an exemplary embodiment, a combined simultaneous sensing of multiple word lines is used in order to identify a problem in one or more of these word lines. That is, sensing voltages are concurrently applied to the control gates of more than one memory cell whose resultant conductance is measured on the same bit line. The combined sensing result is use for measuring certain statistics of the cell voltage distribution (CVD) of multiple word lines and comparing it to the expected value. In case the measured statistics are different than expected, this may indicate that one or more of the sensed word lines may exhibit a failure and more thorough examination of the group of word lines can be performed.Type: GrantFiled: April 21, 2014Date of Patent: October 28, 2014Assignee: SanDisk Technologies Inc.Inventors: Eran Sharon, Yan Li, Dana Lee, Idan Alrod
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Patent number: 8874997Abstract: A system comprising a memory, and a control module external to the memory. The memory includes a plurality of cells. The control module is configured to receive user data to be stored in the plurality of cells, select one of a plurality of sequences of pilot data, based on the selected one of the plurality of sequences of pilot data, generate pilot data having a known predetermined sequence, combine the pilot data with the user data, and output the combined pilot data and user data. A write module is configured to write the combined pilot data and user data to the plurality of cells of the memory.Type: GrantFiled: January 17, 2014Date of Patent: October 28, 2014Assignee: Marvell International Ltd.Inventors: Xueshi Yang, Zining Wu
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Patent number: 8874991Abstract: A method begins by a processing module receiving a request to store data in dispersed storage network (DSN) memory and determining whether the data is to be appended to existing data. When the data is to be appended, the method continues with the processing module encoding, using an append dispersed storage error coding function, the data to produce a set of encoded append data slices, generating a set of append commands, wherein an append command of the set of append commands includes an encoded append data slice of the set of encoded append data slices and identity of one of a set of dispersed storage (DS) units, and outputting at least a write threshold number of the set of append commands to at least a write threshold number of the set of DS units.Type: GrantFiled: March 6, 2012Date of Patent: October 28, 2014Assignee: Cleversafe, Inc.Inventor: Jason K. Resch
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Patent number: 8867287Abstract: A semiconductor memory apparatus including a test circuit configured for generating compressed data by comparing and compressing data stored in a plurality of memory cells inside a memory bank during a first test mode, and configured for outputting the compressed data as test data to an input/output pad through one selected global line during the first test mode, and the test circuit is configured for transmitting the compressed data to a plurality of global lines during a second test mode, combining the compressed data loaded in the respective global lines during the second test mode, and outputting the combination result as the test data to the input/output pad during the second test mode.Type: GrantFiled: August 15, 2012Date of Patent: October 21, 2014Assignee: SK Hynix Inc.Inventors: Jin Youp Cha, Jae Il Kim
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Patent number: 8868990Abstract: A semiconductor memory device is disclosed that includes an ODT circuit configured to be connected to a bus which transmits a data signal or a data strobe signal between a memory block and an input-output terminal; a first switch configured to be inserted into the bus between the memory block and the ODT circuit; a mode controller configured to switch off the first switch during a test of the memory block; and an oscillator configured to be connected to the ODT circuit, wherein a test signal is supplied to the ODT circuit from the oscillator during the test of the memory block.Type: GrantFiled: March 27, 2012Date of Patent: October 21, 2014Assignee: Fujitsu LimitedInventors: Rikizo Nakano, Osamu Ishibashi, Sadao Miyazaki
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Patent number: 8866650Abstract: A circuit for testing digital-to-analog (DAC) and analog-to-digital converters (ADC) is provided. The circuit applies a code pattern having a plurality of sequential values to the digital to analog converter. A plurality of built-in test switches (BTS) couple at least one tap voltage from the DAC to a test bus and to the ADC as a variable reference input voltage. In one form, the circuit uses incremental digital codes to test for defects in a resistor string, a switch array, and a decode logic that form part of the DAC. In another form, the circuit uses the tap voltages from the DAC to test the comparators that form part of the ADC. Instead of performing time-consuming analog to digital conversions, the functionality of the above mentioned circuitry is tested by varying the code pattern around a reference point and by selecting the appropriate combination of BTS switches.Type: GrantFiled: December 7, 2011Date of Patent: October 21, 2014Assignee: Intel CorporationInventors: Stephen J. Spinks, Andrew Talbot, Colin Mair
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Patent number: 8862953Abstract: A method includes directing an access of a memory location of a memory device to an error correction code (ECC) decoder in response to receiving a test activation request indicating the memory location. The method also includes writing a test pattern to the memory location and reading a value from the memory location. The method further includes determining whether a fault is detected at the memory location based on a comparison of the test pattern and the value.Type: GrantFiled: January 4, 2013Date of Patent: October 14, 2014Assignee: International Business Machines CorporationInventors: Marc A. Gollub, Girisankar Paulraj, Diyanesh B. Vidyapoornachary, Kenneth L. Wright
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Patent number: 8862965Abstract: Systems, methods, and other embodiments associated with decoding codewords are described. According to one embodiment, a read channel includes a set of memories and a decoding logic. The set of memories is configured to decode a plurality codewords. At least one memory is classified as an inactive memory for use when a failure occurs. The remaining memories of the set of memories are classified as active memory for decoding. The decoding logic is configured to decode the plurality of codewords using the active memory of the set of memories. When the decoding logic fails to decode a codeword, which is stored in a memory of the active memory, resulting in a failed codeword, the memory of the active memory is reclassified as a memory of the inactive memory.Type: GrantFiled: February 23, 2012Date of Patent: October 14, 2014Assignee: Marvell International Ltd.Inventors: Panu Chaichanavong, Gregory Burd
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Patent number: 8862952Abstract: A data storage system configured to perform prioritized memory scanning for memory errors is disclosed. In one embodiment, the data storage system prioritizes scanning for memory errors based on a quality attribute of pages or zones of a non-volatile memory array. Pages or zones having quality attributes that reflect a lower level of reliability or endurance than other pages or zones are scanned more frequently for memory errors. When memory errors are discovered, the quality attribute of pages or zones can be adjusted to reflect a lower level of reliability or endurance. In addition, stored data can be recovered before it may become permanently lost and before a host system reads the stored data. Improved performance of the data storage system is thereby attained.Type: GrantFiled: March 16, 2012Date of Patent: October 14, 2014Assignee: Western Digital Technologies, Inc.Inventors: Jing Booth, Andrew J. Tomlin
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Patent number: 8862967Abstract: A method may be performed at a data storage device that includes a memory and a controller. The method includes providing user data to a variable-bit error correction coding (ECC) encoder. The ECC encoder generates a first set of parity bits. A first number of parity bits in the first set of parity bits is determined based on stored counts of read errors. The method also includes storing the user data and the first set of parity bits to a memory of the data storage device.Type: GrantFiled: April 19, 2012Date of Patent: October 14, 2014Assignee: Sandisk Technologies Inc.Inventors: Deepak Pancholi, Manuel Antonio D'Abreu, Radhakrishnan Nair, Stephen Skala
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Patent number: 8856615Abstract: A data storage device is disclosed comprising a non-volatile memory (NVM). First data is written to a first area of the NVM, and a first estimated data sequence is read from the first area of the NVM. The first estimated data sequence is first decoded, and a log-likelihood ratio (LLR) is first updated based on the first decode. Second data is written to a second area of the NVM, and a second estimated data sequence is read from the second area of the non-volatile memory. The second estimated data sequence is second decoded in response to the first updated LLR, and the LLR is second updated based on the second decode.Type: GrantFiled: June 11, 2012Date of Patent: October 7, 2014Assignee: Western Digital Technologies, Inc.Inventors: Anantha Raman Krishnan, Shayan S. Garani, Kent D. Anderson, Shafa Dahandeh
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Patent number: 8854241Abstract: A method and system for monitoring an output of an electronic processing component which detects an out-of-range value in the output of the electronic processing component during one time period during which one channel of input channels of a time multiplexer provides an input signal to the electronic processing component. Corrective actions are performed based on the detected out-of-range value. The corrective actions including excluding further multiplexing of signals from the one channel of the input channels.Type: GrantFiled: May 20, 2013Date of Patent: October 7, 2014Assignee: Hamilton Sundstrand CorporationInventors: Gary Hess, Kirk Lillestolen
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Patent number: 8850281Abstract: Technologies are generally described for secure digital signatures that employ hardware public physically unclonable functions. Each unique digital signature generator can be implemented as hardware such that manufacturing variations provide measurable performance differences resulting in unique, unclonable devices or systems. For example, slight timing variations through a large number of logic gates may be used as a hardware public physically unclonable function of the digital signature unit. The hardware digital signature unit can be parameterized such that its physical characteristics may be publicly distributed to signature verifiers. The verifiers may then simulate randomly selected portions of the signature for verification.Type: GrantFiled: May 12, 2009Date of Patent: September 30, 2014Assignee: Empire Technology Development LLCInventor: Miodrag Potkonjak
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Publication number: 20140289574Abstract: A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.Type: ApplicationFiled: October 19, 2012Publication date: September 25, 2014Inventors: Ely Tsern, Frederick A. Ware, Suresh Rajan, Thomas Vogelsang
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Patent number: 8843778Abstract: A method for calibrating a DDR memory controller is described. The method provides an optimum delay for a core clock delay element to produce an optimum capture clock signal. The method issues a sequence of read commands so that a delayed version of a dqs signal toggles continuously. The method delays a core clock signal to sample the delayed dqs signal at different delay increments until a 1 to 0 transition is detected on the delayed dqs signal. This core clock delay is recorded as “A.” The method delays the core clock signal to sample the core clock signal at different delay increments until a 0 to 1 transition is detected on the core clock signal. This core clock delay is recorded as “B.” The optimum delay value is computed from the A and B delay values.Type: GrantFiled: September 11, 2013Date of Patent: September 23, 2014Assignee: Uniquify, IncorporatedInventors: Jung Lee, Mahesh Goplan
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Patent number: 8843803Abstract: A method begins by a processing module encoding data utilizing a dispersed storage error coding function to produce a set of encoded data slices, wherein the dispersed storage error coding function includes a decode threshold parameter and a pillar width parameter. The method continues with the processing module storing a number of encoded data slices of the set of encoded data slices in a local memory, wherein the number is based on the decode threshold parameter and is less than the pillar width parameter, and outputting remaining encoded data slices of the set of encoded data slices to dispersed storage network (DSN) memory.Type: GrantFiled: March 6, 2012Date of Patent: September 23, 2014Assignee: Cleversafe, Inc.Inventors: Jason K. Resch, Gary W. Grube, Timothy W. Markison
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Patent number: 8843804Abstract: A method begins by a processing module storing data files utilizing a dispersed storage error coding function that includes a pillar width parameter and a decode threshold parameter. The method continues with the processing module determining whether to adjust the pillar width parameter based one or more memory performance characteristics. When the pillar width parameter is to be decreased, the method continues with the processing module identifying one or more pillars within a memory to delete to produce one or more identified pillars, identifying encoded data slices of one or more of the data files stored in the one or more identified pillars to produce identified encoded data slices, and deleting the identified encoded data slices.Type: GrantFiled: March 6, 2012Date of Patent: September 23, 2014Assignee: Cleversafe, Inc.Inventors: Jason K. Resch, Gary W. Grube, Timothy W. Markison
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Publication number: 20140281764Abstract: A system comprises pipeline registers and an integrated circuit comprising a memory array. The integrated circuit is coupled to the pipeline registers, and a data path incorporating the memory array is used to test the integrated circuit.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Susumu Sugie, Seiji Yanagida
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Publication number: 20140281765Abstract: A memory card includes a memory cell, a connector, a controller, and firmware. The memory cell can switch between a plurality of states. The connector can be connected to an external device and exchange signals including commands and data with the external device. The controller exchanges signals with the connector, analyzes a received signal, and accesses the memory cell to record, retrieve or modify data based on the analysis result. The firmware is located within the controller, controls the operation of the controller, and can be set to a test mode or a user mode. When the firmware receives a test command from the external device and the firmware is set to the test mode, the firmware performs a defect test on the memory cell and transmits the result of the defect test to the external device through the connector.Type: ApplicationFiled: May 28, 2014Publication date: September 18, 2014Inventors: Yun-Bo Yang, Young-Jae Jung, Kui-Hyun Ro, Sung-Eun Yun
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Patent number: 8839057Abstract: An integrated circuit includes memory units and at least one memory test module, each module includes one associated memory unit, a set of test registers therefor, and a test engine configured to perform a test operation on that associated memory unit. A transaction interface of the memory test module receives a transaction specifying a register access operation and providing a first address portion having encodings allowing individual memory units as well as groups of memory units to be identified, and a second address portion identifying one of the test registers within the set to be an accessed register. Decode circuitry, within each memory test module and responsive to the transaction, is configured to selectively perform the register access operation if it is determined that the memory test module includes a set of test registers associated with a memory unit.Type: GrantFiled: February 3, 2011Date of Patent: September 16, 2014Assignee: ARM LimitedInventor: Paul Stanley Hughes
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Patent number: 8836360Abstract: A semiconductor device that can be manufactured with reduced costs and that includes a first connecting terminal, a second connecting terminal, a third connecting terminal, and a first circuit module configured to operate in response a first signal and a second signal. When a mode signal is in a first state, the first circuit module receives the first signal from the first connecting terminal and receives the second signal from the second connecting terminal. Otherwise, when the mode signal is in a second state, the first circuit module receives the first signal from the first connecting terminal and receives the second signal from the third connecting terminal. A memory module including at least one such memory device may also be provided.Type: GrantFiled: September 22, 2011Date of Patent: September 16, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Young-ju Oh
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Patent number: 8839073Abstract: An SSD controller maintains a zero count and a one count, and/or in some embodiments a zero/one disparity count, for each read unit read from an SLC NVM (or the lower pages of an MLC). In an event that the read unit is uncorrectable in part due to a shift in the threshold voltage distributions away from their nominal distributions, the maintained counts enable a determination of a direction and/or a magnitude to adjust a read threshold to track the threshold voltage shift and restore the read data zero/one balance. In various embodiments, the adjusted read threshold is determined in a variety of described ways (counts, percentages) that are based on a number of described factors (determined threshold voltage distributions, known stored values, past NVM operating events). Extensions of the forgoing techniques are described for MLC memories.Type: GrantFiled: May 4, 2012Date of Patent: September 16, 2014Assignee: LSI CorporationInventor: Earl T Cohen
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Patent number: 8839074Abstract: Methods and devices for recovering data stored in a non-volatile storage device are provided. Data may be recovered for memory cells associated with a word line that cannot be read using ECC that was calculated based on the data stored on that word line. This allows recovery for situations such as a word line shorting to the substrate or two adjacent word lines shorting together. When programming memory cells associated with a group of word lines, parity bits may be calculated and stored in memory cells associated with an additional word line in the memory device. When reading memory cells associated with one of the word lines in the group, an otherwise unrecoverable error may occur. By knowing which word line is defective, its data may be recovered using the parity bits and the data of all of the other word lines in the group.Type: GrantFiled: September 13, 2012Date of Patent: September 16, 2014Assignee: SanDisk Technologies Inc.Inventor: Eugene Tam
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Patent number: 8839058Abstract: A method and apparatus for multi-site testing of computer memory devices. An embodiment of a method of testing computer memory devices includes coupling multiple memory devices, each memory device having a serializer output and a deserializer input, wherein the serializer output of a first memory device is coupled with a deserializer input of one or more of the memory devices of the plurality of memory devices. The method further includes producing test signal patterns using a test generator of each memory device, serializing the test signal pattern at each memory device, and transmitting the serialized test pattern for testing of the memory devices, wherein testing of the memory devices includes a first test mode and a second test mode.Type: GrantFiled: September 24, 2013Date of Patent: September 16, 2014Assignee: Silicon Image, Inc.Inventor: Chinsong Sul
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Patent number: 8832508Abstract: Apparatus and methods are provided for concurrently selecting multiple arrays of memory cells when accessing a memory element. A memory element includes a first array of one or more memory cells coupled to a first bit line node, a second array of one or more memory cells coupled to a second bit line node, access circuitry for accessing a first memory cell in the first array, a first transistor coupled between the first bit line node and the access circuitry, and a second transistor coupled between the second bit line node and the access circuitry. A controller is coupled to the first transistor and the second transistor, and the controller is configured to concurrently activate the first transistor and the second transistor to access the first memory cell in the first array.Type: GrantFiled: November 18, 2010Date of Patent: September 9, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Carson Henrion, Michael Dreesen
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Patent number: 8832507Abstract: Systems and methods are disclosed for generating dynamic super blocks from one or more grown bad blocks of a non-volatile memory (“NVM”). In some embodiments, a dynamic super block can be formed by striping together a subset of memory locations of grown bad blocks from one or more dies of a NVM. The subset of memory locations may be selected based on at least one reliability measurement of the subset of memory locations. In some embodiments, in response to detecting one or more access failures in a portion of the dynamic super block, the NVM interface can retire at least a portion of the dynamic super block. In some embodiments, the NVM interface can reconstruct a new dynamic super block from the dynamic super block by progressively increasing the size of the new dynamic super block.Type: GrantFiled: August 23, 2010Date of Patent: September 9, 2014Assignee: Apple Inc.Inventors: Daniel J. Post, Hsiao Thio
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Patent number: 8832506Abstract: According to exemplary embodiments, a system, method, and computer program product are provided for BER-based wear leveling in a SSD. A block-level BER value for a block in the SSD is determined. An adjusted PE cycle count for the block is incremented or decremented based on the block-level BER value. Wear leveling is then performed in the SSD based on the adjusted PE cycle count.Type: GrantFiled: January 20, 2012Date of Patent: September 9, 2014Assignee: International Business Machines CorporationInventors: Thomas J. Griffin, Dustin J. Vanstee
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Patent number: 8832509Abstract: A semiconductor system includes a semiconductor memory configured to determine whether an error has occurred in a data pattern and generate an error signal, and a memory controller configured to provide the data pattern to the semiconductor memory and perform data training with respect to the semiconductor memory using the error signal.Type: GrantFiled: December 16, 2010Date of Patent: September 9, 2014Assignee: SK Hynix Inc.Inventor: Sang Sic Yoon
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Patent number: 8826087Abstract: An integrated circuit comprises scan test circuitry, additional circuitry subject to testing utilizing the scan test circuitry, and control circuitry associated with the scan test circuitry. The scan test circuitry comprises a scan chain having a plurality of scan cells, and the associated control circuitry is coupled to at least a given one of a primary input of the integrated circuit and a primary output of the integrated circuit. The scan test circuitry is configurable by the control circuitry so as to permit testing of both an input functional path associated with the given one of the primary input and the primary output and an output functional path associated with the given one of the primary input and the primary output.Type: GrantFiled: November 21, 2012Date of Patent: September 2, 2014Assignee: LSI CorporationInventors: Ramesh C. Tekumalla, Vijay Sharma
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Patent number: 8826086Abstract: A memory card and methods for testing memory cards are disclosed herein. The memory card has a test interface that allows testing large numbers of memory cards together. Each memory card may have a serial data I/O contact and a test select contact. The memory cards may only send data via the serial data I/O contact when selected, which may allow many memory cards to be connected to the same serial data line during test. Moreover, existing test socket boards may be used without adding additional external circuitry. Thus, cost effective testing of memory cards is provided. In some embodiments, the test interface allows for a serial built in self test (BIST).Type: GrantFiled: February 7, 2011Date of Patent: September 2, 2014Assignee: SanDisk Technologies Inc.Inventors: Charles Moana Hook, Loc Tu, Nyi Nyi Thein, James Floyd Cardosa, Ian Arthur Myers
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Publication number: 20140245087Abstract: According to an embodiment, a semiconductor integrated circuit includes a memory, a bypass circuit, a first selection unit, a compression unit, and a comparison unit. The bypass circuit bypasses the test signal to output a bypass signal. When the memory is tested using a BIST circuit, the first selection unit selects a memory signal output from the memory in response to the test signal. When the BIST circuit is tested, the first selection unit selects the bypass signal. If the memory is tested, the compression unit holds a signal output from the first selection unit and if the BIST circuit is tested, the compression unit compresses and holds the signal output from the first selection unit. The comparison unit compares the signal held in the compression unit with an expectation value signal of the memory signal which is generated in the BIST circuit.Type: ApplicationFiled: July 15, 2013Publication date: August 28, 2014Inventors: Chikako TOKUNAGA, Kenichi ANZOU
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Publication number: 20140245088Abstract: There is provided a semiconductor test device, including: a test information acquisition unit acquiring test information; a test information conversion unit converting the acquired test information into test vector information including a plurality of test vectors; and a test signal generation unit generating a test input signal based on the test vector information.Type: ApplicationFiled: February 27, 2014Publication date: August 28, 2014Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventor: OSCAR PEDRO BANAAG TORRECAMPO
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Patent number: 8819522Abstract: A disk array apparatus, if a rebuild error occurs, stores information indicating an error occurrence place in a sector holding unit, and then stops rebuild processing. A host computer, if a rebuild error occurs in the disk array apparatus, acquires the information indicating the error occurrence place from the disk array apparatus. The host computer determines whether the rebuild error does not obstruct continuation of the rebuild processing based on the acquired information indicating the error occurrence place. If it is determined that the rebuild error does not obstruct continuation of the rebuild processing, the host computer instructs the disk array apparatus to resume the rebuild processing while skipping the error occurrence place. In response to the instruction from the host computer, the disk array apparatus resumes the rebuild processing while skipping the error occurrence place.Type: GrantFiled: May 3, 2011Date of Patent: August 26, 2014Assignee: Canon Kabushiki KaishaInventor: Tatsuru Baba
