Abstract: A system is provided to encode data for recording onto media whereby modulation and linear constraints from a concatenated code or product code are imposed. A first array of unencoded user data is generated. Each row is modulation encoded to enforce a first modulation constraint; the array is transformed into a second array which is transformed into a third array having predetermined empty locations in each column interleaved with the modulated data. A C2-parity byte is computed for at least some of the empty locations of the third array and a fourth array is generated. C1-parity symbols in each row are computed, generating a fifth array. A second modulation constraint is enforced on each C1-parity symbol in each row of the fifth array, generating a sixth array. The rows of the sixth array are assembled with header and sync fields for recording onto a recording media.

Abstract: Method and computer program product are provided to encode data for recording onto media whereby modulation and linear constraints from a concatenated code or product code are imposed. A first array of unencoded user data is generated. Each row is modulation encoded to enforce a first modulation constraint; the array is transformed into a second array which is transformed into a third array having predetermined empty locations in each column interleaved with the modulated data. A C2-parity byte is computed for at least some of the empty locations of the third array and a fourth array is generated. C1-parity symbols in each row are computed, generating a fifth array. A second modulation constraint is enforced on each C1-parity symbol in each row of the fifth array, generating a sixth array. The rows of the sixth array are assembled with header and sync fields for recording onto a recording media.

Abstract: To eliminate the need for buffering in order to calculate data length information on data as an object of computation, a first exclusive-OR unit 53 executes computation of exclusive-OR of a cyclic code R(x) of the integral multiple bit bits block A(x) and a data string of M bits, containing the fraction bits block B(x). A first shifting unit 54 shifts the exclusive-OR of the cyclic code R(x) and the data string of M bits, containing the fraction bits block B(x), by {M?H(k)} bits toward a least significant side, where M is a parallel width and H(k) is a bit length of the fraction bits block B(x). An R?(x) generation unit 55 generates a cyclic code R?(x) that is a cyclic code of the data after shifting. To obtain R?(x), a second shifting unit 56 shifts the cyclic code R(x) by H(k) bits toward a most significant side. A second exclusive-OR unit 57 executes computation of exclusive-OR of the cyclic code R?(x) and data R?(x).

Abstract: A data converter includes: an input module to which a first data series is input, the first data series having a first data sequence and a first error detection code corresponding to a remainder of division of the first data sequence by a predetermined polynomial; a conversion module converting the first data sequence into a second data sequence by processing including one of insertion, exchange, and inversion of a bit or a bit sequence, and exclusive-OR with a predetermined bit or bit sequence; a processing bit sequence generation module generating a processing bit sequence corresponding to the processing; and a code generation module generating a second error detection code corresponding to the second data sequence based on an exclusive-OR of the generated processing bit sequence and the first error detection code.

Abstract: The invention provides a method for encoding and decoding an error correction code. First, raw data is received and then divided into a plurality of data segments. A plurality of short parities corresponding to the data segments is then generated according to a first generator polynomial. The short parities are then appended to the data segments to obtain a plurality of short codewords. The short codewords are then concatenated to obtain a code data. A long parity corresponding to the code data is then generated according to a second generator polynomial, wherein the first generator polynomial is a function of at least one minimum polynomial of the second generator polynomial. Finally, the long parity is then appended to the code data to obtain a long codeword as an error correction code corresponding to the raw data.

Abstract: An encoder and a decoder employ an encoding scheme corresponding to a parity check matrix which is derivable from a bipartite protograph formed of variable nodes and check nodes, with each variable node corresponding to a codeword symbol position. The protograph has a plurality of groups of nodes, each group of nodes comprising both variable nodes and check nodes. Each of the check nodes in a group is of degree 2 and has connections to two variable nodes in the same group. The protograph also has a plurality of check nodes of degree n, where n is the number of said plurality of groups, wherein each of the plurality of check nodes has a connection to a variable node in each group such that the symbol positions in a codeword are interleaved between the groups of nodes.

Abstract: A system apparatus and method generates a communications signal having an error detection mechanism. A circuit generates a data packet. An encoder multiplies and accumulates data words with values in a distance table containing non-repeated n-bit multipliers having “m” number of one bits that are set to obtain accumulated sum bits and appends the accumulated sum bits to the data packet as an error detection code to form a communications signal to be transmitted.

Abstract: Data error detection and correction in non-volatile memory devices are disclosed. Data error detection and correction can be performed with software, hardware or a combination of both. Generally an error corrector is referred to as an ECC (error correction code). One of the most relevant codes using in non-volatile memory devices is based on BCH (Bose, Ray-Chaudhuri, Hocquenghem) code. In order to correct reasonable number (e.g., up to 8-bit (eight-bit)) of random errors in a chunk of data (e.g., a codeword of 4200-bit with 4096-bit information data), a BCH(4200,4096,8) is used in GF(213). ECC comprises encoder and decoder. The decoder further comprises a plurality of error detectors and one error corrector. The plurality of error decoders is configured for calculating odd terms of syndrome polynomial for multiple channels in parallel, while the error corrector is configured for sequentially calculating even terms of syndrome polynomial, key solver and error location.

Abstract: Methods and systems for error detection and error correction in n-valued with n>2 data symbols are disclosed. N-valued check symbols are generated from data symbols in n-valued logic expressions using n-valued logic functions. N-valued Hamming codes are disclosed. Also disclosed is the generation of check symbols from data symbols in an n-valued expression wherein at least one check symbol is multiplied by a factor not equal to 0 or 1 in GF(n). Identifying n-valued symbols in error by check symbols and error correction by solving sets of independent n-valued equations are also disclosed. A method for introducing and removing annoyance errors is provided. Systems for error corrections in communication and data storage are also provided.

Abstract: Methods and apparatus reducing the number of multipliers in Galois Field arithmetic are disclosed. Methods and apparatus for implementing n-valued Linear Feedback Shift Register (LFSR) based applications with a reduced number of multipliers are also disclosed. N-valued LFSRs with reduced numbers of multipliers in Fibonacci and in Galois configuration are demonstrated. Multiplier reduction methods are extended to n-valued functions with more than 2 inputs. Methods to create multiplier reduced multi-input n-valued function truth tables are disclosed. Methods and apparatus to implement these truth tables with a limited number of n-valued inverters are also disclosed. Scrambler/descrambler combinations with adders and multipliers over GF(2p) are provided. Communication, data storage and digital rights management systems using multiplier reduction methods and apparatus or the disclosed scrambler/descrambler combination are also provided.

Abstract: Systems and methods to perform polynomial division are disclosed. In a particular embodiment, the method includes receiving a codeword and storing a portion of the received codeword at a register. The portion of the received codeword has a first number of terms. A divisor having a second number of terms is also received. During at least one stage of a multi-stage polynomial division operation using the portion of the codeword and the divisor, the portion of the received codeword to be divided by the divisor is adjusted based on a result of a comparison of the first number to the second number.

Abstract: A method for decoding an Error Correction Code (ECC) includes accepting coefficients, including at least first and second coefficients, of an Error Locator Polynomial (ELP) that is defined over a vector space and has at least one root that is indicative of a location of an error in a set of bits, which represent data that has been encoded with the ECC. The first coefficient is represented using a first basis of the vector space, and the second coefficient is represented using a second basis of the vector space, different from the first basis. Using processing circuitry, the root of the ELP is identified by applying algebraic operations to the coefficients, such that the algebraic operations are applied to the first coefficient using the first basis, and to the second coefficient using the second basis. The error is corrected responsively to the identified root of the ELP.

Abstract: A wireless communication device including a first CRC coder that generates a first block of CRC parity bits on a transport block and associates the first block of CRC parity bits with the transport block, a segmenting entity that segments the transport block into multiple code blocks after associating, and a second coder that generates a second block of CRC parity bits on each code block and associates a second block of CRC parity bits with each code block. The first and second blocks of CRC parity bits are based on first and second generator polynomials.

Abstract: Disclosed herein is a receiving apparatus including a reception device configured to receive a code sequence coded in LDPC (Low Density Parity Check) and punctured at least partially as a target to be decoded; and an LDPC decoding device configured to perform a punctured matrix transform process including a first and a second process on an original parity check matrix noted to have punctured bits or symbols and used in the LDPC coding. The LDPC decoding device further performs the first process to carry out Galois field addition operations on those rows of the original parity check matrix to set the non-zero elements to zero. The LDPC decoding device further performs the second process to delete the columns rid of the non-zero elements. The LDPC decoding device uses the matrix resulting from the process as the parity check matrix for performing an LDPC decoding process on the code sequence.

Abstract: Convolutional coders having an n-state with n?2 Linear Feedback Shift Registers (LFSR) in Galois configuration with k shift register elements with k>1 are provided. Corresponding decoders are also provided. A convolutional coder generates a sequence of coded n-state symbols. A content of a starting position of an LFSR in a decoder is determined when sufficient error free coded symbols are available. Up to k symbols in error are corrected. A systematic convolutional coder and decoder are also provided.

Abstract: A communication system comprises a transmitting device and a receiving device. The transmitting device includes means for connecting an addition bit string containing at least one bit 1 to information data, means for generating a CRC code corresponding to a remainder at a polynomial ring on a Galois field defined modulo 2 based on a predetermined generator polynomial of the information data connected with the addition bit string, means for transmitting the information data connected with the CRC code. The receiving device includes means for receiving the data, means for performing an addition of the data received and the addition bit string at a polynomial ring on a Galois field defined modulo 2, means for making a decision as to the presence or absence of a transmission error by determining the remainder at the polynomial ring on the Galois field defined modulo 2 based on the generator polynomial of data.

Abstract: Methods and apparatus are provided for more efficiently computing error checking codes such as cyclic redundancy checks (CRCs). Based on particular characteristics of CRCs, an input sequence is intelligently divided into a series of subsequences. Each subsequence gets selected bits from the input sequence. The error checking code is calculated on each subsequence. The results are bit-interleaved and an error checking code is calculated over this interleaved result to obtain the error checking code over the entire sequence.

Abstract: The present invention provides for applying a cyclic redundancy check (CRC) to a data signal. The present invention includes attaching a first CRC to a first data signal block having a first length, segmenting the first data signal block attached with the first CRC into a plurality of second data signal blocks having a length shorter than the first length, respectively generating a second CRC for each second data signal block, and attaching the generated second CRC to the respective second data signal block. Moreover, the first CRC and second CRC may be generated from respectively different CRC generating polynomial equations.

Abstract: An error locator polynomial is incrementally generated by flipping a bit pattern Yi at a symbol Xi an initial dataword to obtain a first test error pattern. A bit pattern Yj at a symbol Xj within the first test error pattern is flipped to obtain a second test error pattern, wherein i?j.

Abstract: A method of correcting errors in a message transmitted over a digital communication channel, where the message was encoded using a CRC for purposes of error detection. A parity-check matrix representation of the CRC is computed for any fixed-length message, and that parity-check matrix is combined with the parity-check matrix for any error correcting code that used in conjunction with the CRC. The combined parity-check matrix is extended using sparsification algorithms to allow it to work well under a message passing decoder (MPD). Received messages are decoded using the message passing decoder, making it possible to correct more errors than if the CRC were decoded in a conventional manner.

Abstract: A method is described for use in determining a residue of a message. The method includes loading at least a portion of each of a set of polynomials derived from a first polynomial, g(x), and determining the residue using a set of stages. Individual ones of the stages apply a respective one of the derived set of polynomials to data output by a preceding one of the set of stages.

Abstract: The present invention provides a method and a system for verifying a match between states of a first video processor and a second video processor, wherein one of said first and second video processors is a video encoder utilizing predictive video encoding and the other one of said first and second video processors is a video decoder capable of reproducing a decoded bit stream from an encoded bit stream generated by said video encoder.

Abstract: Apparatuses and methods for detecting error events in a codeword reproduced by perpendicular magnetic recording medium (PMR. The method includes: generating cyclic redundancy check (CRC) parity bits based on a generator polynomial for a source information sequence to be recorded on PMR medium and recording a codeword in which the generated CRC parity bits are added to the source information sequence; and reading the recorded codeword and an error event in the read codeword. It is possible to detect error events when a codeword recorded by PMR is read, using a small number of bits.

Abstract: An improvement to a key equation solver block for a BCH decoder, where the key equation solver block having a number of multiplier units specified by X, where: t*(7*t?1)/(codeword_len?3)?X<(t+1), where t is a number of transmission errors for the key equation solver block to correct, and codeword_len is a length of a transmitted codeword to be decoded by the BCH decoder.

Abstract: Methods and apparatus for generating parity symbols for a data block are disclosed. One of the proposed methods includes: determining a multiplicator polynomial for a first-direction symbol line of the data block, receiving a set of symbols on the first-direction symbol line, multiplying each of the set of symbols by the multiplicator polynomial to generate a set of product polynomials, repeating the determining, receiving, and multiplying steps for a plurality of first-direction symbol lines of the data block to generate a plurality of sets of product polynomials, and summing the plurality of sets of product polynomials to generate a set of parity polynomials. The coefficients of the set of parity polynomials constitute parity symbols of the data block.

Abstract: A decoder and method for implementing an iterative error correcting decoder are provided for decoding a codeword consisting of a N-bit messages. In one implementation, the decoder includes a first set of nodes, and a second set of nodes, each having N bits of resolution. Each node of the second set is coupled to at least one node of the first set, each node of the second set being coupled to a node of the first set by a corresponding set of M wires. Each of the first set of nodes is operable to transfer the bits of a given N-bit message of the codeword over the corresponding set of M wires to a coupled node of the second set during a single iteration cycle, each of the M wires carrying i bits, where N is an integer greater than M, and N=M*i.

Abstract: A method and an apparatus that has Chien search capabilities, the apparatus includes a first hardware circuit and a second hardware circuit. The first hardware circuit evaluates an error locator polynomial for a first element of a finite field over which the error locator polynomial is defined to provide a first set of intermediate results and a first Chien search result and provides the first set of intermediate results to the second hardware circuit; the second hardware circuit evaluates the error locator polynomial for a second element of the finite field to provide a second Chien search result in response to the first set of intermediate results.

Abstract: A method and a device for information block coding and synchronization detecting are provided. Information block coding and synchronization detecting are preformed according to a synchronization character sequence satisfying certain conditions. Thus, the probability of incorrect synchronization is effectively reduced without increasing the complexity. Optimal synchronization character sequences in different lengths are provided to further reduce the probability of incorrect synchronization.

Abstract: A non-linear post-processor for estimating at least one source of signal-dependent noise is disclosed. The post processor may receive a set of preliminary decisions from a sub-optimal detector along with the sampled data signal. The post-processor may then compute the transition jitter and white noise associated with each preliminary decision in the set and assign a cost metric to each decision based on the total signal noise. The post-processor may output the decision with the lowest cost metric as the final decision of the detector.

Abstract: Generating a polynomial is disclosed. A prior error locator polynomial, associated with locating errors in encoded data, is obtained. A new error locator polynomial, associated with a test error pattern, is incrementally generated based at least in part on the prior error locator polynomial.

Abstract: A system and method for reduced power consumption communications over a physical interconnect is described. In an embodiment, an input/output circuit includes a port to receive a transmission unit via an interconnect, a combining module coupled to the port to append at least one of a first and a second indicator to the transmission unit, a first adder module to generate the first indicator, indicating that the transmission unit is a starting transmission unit of a set of related transmission units, a second adder module to generate the second indicator, indicating that the starting transmission unit of the set of related transmission units has already been received, and logic to determine at least one of the start and end boundaries of the set of related transmission units.

Abstract: An apparatus, system and method can be arranged for coding and/or decoding with a phase invariant coding scheme that is useful for short burst signaling devices. 10-bit data is mapped into a 12-bit data with a non-coherent burst code mapper. A parity generator creates a 12-bit parity data to form a 24-bit extended binary Golay code from the 12-bit data. The values for selected bit fields in the 12-bit data and 12-bit parity data are swapped to generate I and Q data such that sensitivity to changes in rotational phase is removed. I and Q data can be used by a transmitter to transmit a rotationally-invariant signal. On receipt, I and Q signals can be recovered, reverse swapped to generate the parity and data signals, and remapped to recover the transmitted 10-bit data. The receiver can also be arranged to use a soft decoding method for improved signal integrity.

Abstract: A low-density parity check convolution code (LDPC-CC) is made, and a signal sequence is sent after subjected to an error-correcting encodement using the low-density parity check convolution code. In this case, a low-density parity check code of a time-variant period (3g) is created by linear operations of first to 3g-th (letter g designates a positive integer) parity check polynomials and input data.

Abstract: The present invention discloses a method for LDPC code erasure decoding, including: generating a first code word through setting a value as a value in Galois field having two elements GF(2) at each of erasure locations in a code word; generating a second code word through setting the value as an inverse value of the value in GF(2) at each of the erasure locations in the code word; conducting a MLD error correcting operation for the first code word and the second code word to get a first result of hard decoding and a second result of hard decoding respectively; determining a result of erasure decoding according to the first result of hard decoding and the second result of hard decoding. Thus the present invention allows LDPC code erasure decoding aimed at the BEC, and increases the error correcting capability for BED signal transmitted data.

Abstract: Techniques are provided for performing Galois field arithmetic to detect errors in digital data stored on disks. Two 12-bit numbers or two 10-bit numbers are multiplied together in Galois field using tower arithmetic. In the 12-bit embodiment, a base field GF(2) is first extended to GF(23), GF(23) is extended to a first quadratic extension GF(26), and GF(26) is extended to a second quadratic extension GF(212). In the 10-bit embodiment, the base field GF(2) is first extended to GF(25), and GF(25) is extended to a quadratic extension GF(210). Each of the extensions for the 10-bit and 12-bit embodiments is performed using an irreducible polynomial. All of the polynomials used to generate the first and the second quadratic extensions of the Galois field are in the form x2+x+K, where K is an element of the ground field whose absolute trace equals 1.

Abstract: Processing polynomials is disclosed. At least a portion of processing associated with an error evaluator polynomial and at least a portion of processing associated with an error locator polynomial are performed simultaneously. The error evaluator polynomial and the error locator polynomial are associated with Berlekamp-Massey processing. Data associated with the error evaluator polynomial is removed, including by shifting data in an array so that at least one element in the array is emptied in a shift.

Abstract: It is possible to provide and an LDPC-CC (Low-Density Parity-Check Convolution Codes) encoder and an LDPC-CC decoder which performs an error correction encoding and decoding while reducing the amount of a termination sequence required for encoding/decoding the LDPC-CC encoding/decoding and suppressing degradation of the transmission efficiency. The LDPC-CC encoder (400) includes a weight control unit (470) which stores a weight pattern (475) based on an LDPC-CC inspection matrix (100); and a weight pattern (476) based on a check matrix (300) obtained by deforming an LDPC-CC inspection matrix (100). The weight control unit (470) controls a weight to be multiplied onto the outputs of a plurality of shift registers (410-1 to 410-M, 430-1 to 430-M) by using the weight pattern (475) when the input bit is an information sequence, and using a weight pattern (476) which makes a weight value to be multiplied by an inspection bit v2,t to be 0 when the input bit is a termination sequence.

Abstract: An apparatus and method are provided including a point-to-point cluster link configured to receive a data packet and determines a cyclic redundancy code check for the data packet. The point-to-point cluster link is configured to add a cyclic redundancy code check bit to the data packet transmitted to the point-to-point inter-cluster link, to clear the cyclic redundancy code check bit when the data packet is received, and to sample a cyclic redundancy code window to identify a corrupted data packet.

Abstract: Embodiments of the invention provide a decoder arrangement (400), wherein a decoder (420) which is adapted to decode a bitstream which has been encoded with a non-recursive convolutional encoder is used to at least partially perform the decoding of a recursive convolutionally encoded bitstream, with pre- or post-processing (410) of the bitstream being performed to complete the decoding. More particularly, in one embodiment of the invention a recursively encoded bitstream is input into a. conventional decoder (420) which is adapted to decode a non-recursively encoded bitstream. The resulting intermediate output does not represent the correct decoded bitstream, but can then be subject to a post-processing step in the form of a non-recursive encoding operation (410), which effectively completes the decoding operation and provides as its output the correct decoded bitstream. Both hard decision or soft decision inputs can be used.

Abstract: A system and method for self-test of an integrated circuit are disclosed. As one example, an integrated circuit is disclosed. The integrated circuit includes a digital signal processing chain, a random sequence generator coupled to an input of the digital signal processing chain, and a checksum calculator coupled to an output of the digital signal processing chain.

Abstract: A linear feedback shift register (LFSR) based design is applied to cyclic redundancy check (CRC) modules, in which a CRC building block having a minimum width is implemented. The CRC building block accepts a generator polynomial as an input design parameter to build a CRC block module. The modularity of the design then allows a larger CRC block design to be constructed from multiple CRC block modules such that wider data width blocks may be accommodated. The LFSR based designs are extended to communication systems that may require scrambling and descrambling functionality.

Abstract: A system and method for correcting errors in an ECC block using soft-decision data. In an embodiment, a soft-decision ECC decoding method, uses “soft” data indicative of how reliable bits of data are when read out. Such a method may use an update module for receiving and manipulating the soft-decision data and iteratively change bits or groups of bits based upon an ordering of the reliability factors. Then a calculator module may determine the total number of errors still remaining after each iteration. Determining just the total number of errors instead of the actual locations is far less computationally intensive, and therefore, many combination of potential flip-bit combination may be analyzed quickly to determine if any combination might reduce the total number of errors enough to be handled by the conventional hard-decision ECC decoding method.

Abstract: Arrangements are provided for efficient erasure coding of files to be distributed and later retrieved from a peer-to-peer network, where such files are broken up into many fragments and stored at peer systems. The arrangements further provide a routine to determine the probability that the file can be reconstructed. The arrangements further provide a method of performing the erasure coding in an optimized fashion, allowing fewer occurrences of disk seeks.

Abstract: A system and method for correcting errors in an ECC block using erasure-identification data when generating an error-locator polynomial. In an embodiment, a ECC decoding method, uses “erasure” data indicative of bits of data that are unable to be deciphered by a decoder. Such a method may use an Berlekamp-Massey algorithm that receives two polynomials as inputs; a first polynomial indicative of erasure location in the stream of bits and a syndrome polynomial indicative of all bits as initially determined. The Berlekamp-Massey algorithm may use the erasure identification information to more easily decipher the overall codeword when faced with a error-filled codeword.

Abstract: A system for cyclic redundancy check (CRC) calculations with modulo-2 multiplication is disclosed for repetitive CRC computations that optimizes processing efficiency and maximizes capacity. The resulting system results in the use of relatively fewer logical gates and conserves on power. The system receives a message ({right arrow over (m)}) including a plurality of blocks ({right arrow over (b)}i) and a set of pre-computed coefficients ({right arrow over (?)}i). The system performs a modulo-2 multiply-accumulate operation on the message ({right arrow over (m)}) using the relationship given by: CRC ? ( m ? ) ? CRC ( ? i ? b ? i ? ? ? i ) .

Abstract: Method and apparatus for generating a set of generator polynomials for use as a tail biting convolutional code to operate on data transmitted over a channel comprises: (0) specifying a constraint and a low code rate for a tail biting convolutional code, where the low rate code is lower than 1/n (n being an integer greater than 4); (1) selecting valid combinations of generator polynomials to include in a pool of potential codes, each valid combination being a potential code of the low rate code; (2) determining first lines of a weight spectrum for each potential code in the pool and including potential codes of the pool having best first lines in a candidate set; (3) determining best codes of the candidate set based on the first L number of lines in the weight spectrum; (4) selecting an optimum code(s) from the best codes; and (5) configuring a circuit(s) of a data transceiver to implement the optimum code(s).

Abstract: A method of encoding a communication signal by selecting a cyclic code, establishing a generator polynomial, generating a polynomial using the generator polynomial, forming a matrix from the generated polynomial, receiving data to be encoded, appending zeros to the received data, calculating a syndrome of the matrix, calculating check values from the syndrome, appending the check values to the received data, and encoding the received data with appended check values using the generator polynomial.

Abstract: Error detection that detects an error in an input data sequence, the input data sequence created by regarding a data sequence having a specified bit length as a polynomial, dividing that polynomial by a generator polynomial for generating error detection code and adding the error detection code to the data sequence so the remainder becomes ‘0’. Including calculating remainder values by dividing polynomials that correspond to each respective bit position by the generator polynomial and saving those remainder values; inputting together with an input data sequence, bit position information that indicates proper bit position of each data of the input data sequence, finding remainder values that correspond to proper bit positions of data of the input data sequence that are not ‘0’, performing bit-corresponding addition of each of the found remainder values; and determining no error in the input data sequence when all bits of the addition result become ‘0’.

Abstract: An encoder includes an outer repetition encoder, an interleaver for permuting encoding from said outer repetition encoder; and an inner encoder for encoding information from the interleaver to provide a repeat zigzag-Hadamard code. In an exemplary embodiment, a common bit of a zigzag-Hadamard segment of encoding from said inner encoder is a repetition of a last parity bit of a previous zigzag-Hadamard segment of encoding from said inner encoder and said common bit is punctured.

Abstract: An error correcting apparatus includes a storing means for storing product code with n2 rows and n1 columns, an error correcting unit 5 that performs error correction for four code sequences simultaneously in parallel, and a bus control unit 2 for reading codes on four rows from the buffer memory 1 and transferring the codes to the error correcting unit 5. The bus control unit 2 reads and transfers four consecutive codes on each of four rows in order before shifting the reading position by four codes in the row direction.