Abstract: A low power Chien searching method employing Chien search circuitry comprising at least two hardware components that compute at least two corresponding bits comprising a Chien search output, the method comprising activating only a subset of the hardware components thereby to compute only a subset of the bits of the Chien search output; and activating hardware components other than those in the subset of hardware components, to compute additional bits of the Chien search output other than the bits in the subset of bits, only if a criterion on the subset of the bits of the Chien search output is satisfied.

Abstract: Methods and systems for designing LDPC codes are disclosed. A method in accordance with the present invention comprises configuring a plurality (M) of parallel accumulation engines, accumulating a first information bit at a first set of specific parity bit addresses using the accumulation engines, increasing a parity bit address for each of the parity bit addresses by a pre-determined offset for each new information bit, accumulating subsequent information bits at parity bit addresses offset from the parity bit addresses by a pre-determined offset until an M+1 information bit is reached, accumulating the next M information bits at a second set of specific parity bit addresses using the parallel accumulation engines, increasing a parity bit address for each member of the second set of parity bit addresses by the pre-determined offset for each new information bit; and repeating accumulating and increasing the addresses until the information bits are exhausted.

Abstract: A method and apparatus is provided to improve an error correction capability for transmitted information, thereby reducing bit error rate and block error rate, and improving the reliability. The method and apparatus can generate error correcting codes having a good minimum distance characteristic, and which can achieve soft decision decoding and reduce the quantity of calculations for the decoding by using an IFHT decoder. Also, the method and apparatus can perform decoding while improving the error correcting capability of particular bits.

Abstract: Efficient methods for encoding and decoding Half-Weight codes are disclosed and similar high density codes are disclosed. The efficient methods require at most 3·(k?1)+h/2+1 XORs of symbols to calculate h Half-Weight symbols from k source symbols, where h is of the order of log(k).

Abstract: A method of generating a codeword for a control signal in a wireless communication system is provided. The method includes preparing a control signal and generating a codeword by applying a Reed-Muller (RM) extension matrix to the control signal. The RM extension matrix is generated by extending a RM basic matrix. A control signal can reliably be transmitted by the codeword with low complexity.

Abstract: A method and apparatus for detecting errors and improving quality in real-time data transmissions is provided. In one embodiment, the packet header checksum field is turned off to allow uninterrupted transmission of data packet payloads. A checksum added to each independent data segment in the datagram payload permits each data packet to be examined separately, resulting in improved transmission quality.

Abstract: A technique to perform carry-less multiplication and bit reflection operations. More specifically, embodiments of the invention include a technique to perform cyclic redundancy code (CRC) generation.

Abstract: Method and apparatus for generating codewords with variable length and redundancy from a single Low-Density Parity-Check (LDPC) code with variable length input words. A mother code for encoding data words is generated based on a parity-check matrix, wherein the mother code is adjusted to reflect the size of the data word to be encoded. A generator matrix applies the mother code to data words to produce codewords for transmission. In one embodiment, a reduction criteria is determined and the size of the generator matrix reduced in response. The corresponding parity-check matrix is applied at the receiver for decoding the received codeword.

Abstract: The errors that may occur in transmitted numerical data on a channel affected by burst errors, are corrected via the operations of: ordering the numerical data in blocks each comprising a definite number of data packets; generating for each block a respective set of error-correction packets comprising a respective number of correction packets, the respective number identifying a level of redundancy for correcting the errors; and modifying dynamically the level of redundancy according to the characteristics of the bursts and of the correct-reception intervals between two bursts. Preferential application is on local networks, such as W-LANs for use in the domestic environments.

Abstract: A scrambling system includes a seed finder that selects a scrambling seed. A first scrambler generates a scrambled sequence in response to a user data sequence and the scrambling seed. A code finder generates at least one of a token and an offset of the token from the scrambling seed. An encoder increases a Hamming weight of the scrambled sequence in response to at least one of the token and the offset.

Abstract: A method of correcting a communication signal with BCH product codes is disclosed. The method comprising the steps of receiving a codeword vector, establishing a generator polynomial, establishing a check polynomial, calculating a binary-matrix, and calculating the binary syndrome S=Hrt. If an all zero vector results, no errors exist in the received vector. If errors exist, a tm x (N?k) binary matrix is created, the power basis expansion of (r(?1), r(?3), r(?5), . . . r(?2t?1)) is calculated, and the syndrome is solved. The speed of the method comes from using word-level XOR's to apply the check polynomial to the stream at all offsets. The utility of this approach is due in part to the fact that the conversion matrix involved can be created quickly using only items needed elsewhere in BCH decoders: a field table and the generator polynomial coefficients.

Abstract: Embodiments of the present invention relate to a data processing system comprising a first arithmetic unit comprising at least one finite field multiplier and at least one finite field adder for selectively performing at least two finite field arithmetic calculations; the data processing system comprising means to use a previous finite field arithmetic calculation result in a current finite field arithmetic calculation to determine at least part of a polynomial.

Abstract: An apparatus, system and method for detecting errors in a physical interface during the transmission and/or receipt of data communications between integrated circuits (“ICs”) are disclosed. In one embodiment, an apparatus is configured to operate as or within a receiving physical interface. The apparatus includes a decoder configured to decode a subset of encoded data bits to yield decoded data bits. It also includes a physical interface (“PI”) error detection bit extractor configured to extract a physical interface error detection bit from the decoded data bits. As such, the apparatus uses the physical interface error detection bit to determine whether the encoded data bits include at least one erroneous data bit as an error. In some embodiments, the apparatus includes an error detector configured to operate within a physical layer. In at least one embodiment, the apparatus efficiently transmits error detection codes within, for example, an NB/(N+1)B line coder.

Abstract: A safety control device for ensuring safety of an object to be controlled, including: communication unit which is used for communication with another safety control device and uses a frame including a test bit string T having correlation with a base bit string B; and detection unit which compares with the base bit string B the test bit string T included in a frame having been received from another safety control device, thereby determining the number of bit errors in the frame.

Abstract: A decoding apparatus and method is disclosed by which the decoder error occurrence probability is suppressed and a high decoding performance can be achieved. An ABP decoding apparatus diagonalizes a parity check matrix, updates LLR values, decodes the LLR values and then adds a decoded word obtained by the decoding to a decoded word list. The ABP decoding apparatus repeats the decoding procedure as inner repetitive decoding by a predetermined number of times. Further, as the ABP decoding apparatus successively changes initial values for priority ranks of the LLR values, it repeats the inner repetitive decoding as outer repetitive decoding by a predetermined number of times. Then, the ABP decoding apparatus selects an optimum one of the decoded words from within a decoded word list obtained by the repeated inner repetitive decoding. The invention is applied to an error correction system.

Abstract: An LDPC decoder has a determined number of processing units operating in parallel. Storage circuitry contains first words having a juxtaposition of a first type of message. The storage circuitry also contains second words having a juxtaposition of a second type of message. A message provision unit provides each processing unit with the messages. A message write unit may write words into the storage circuitry in a way that depends on the contents of the words. The message provision unit may provide data in a way that depends on the contents of the words.

Abstract: In this parity data generating circuit, a Galois field multiplying calculation is realized by performing data conversion by index table information generated from a Galois field multiplying table so that data for RAID6 are generated. A table check circuit inspects nonconformity of the index table information in advance by using results in which the Galois field multiplying table is indexed from different directions constructed by the longitudinal direction and the transversal direction. Data and parity for making the multiplying calculation are decomposed into plural data and parities by using this table check circuit, and index table information different from each other are allocated to these data and parities. Thus, a longitudinal index table making circuit and a transversal index table making circuit themselves are checked.

Abstract: In a data decoder for decoding data from received symbols received over a channel from an encoder, a method for decoding data wherein the received data includes erasures and includes source symbols and repair symbols organized into one or more source blocks. The decoder uses a generator matrix, any square submatrix of which is invertible, such that the decoder performs decoding operations concurrently with the arrival of the source symbols and repair symbols that are a part of a source block. Novel methods for interleaving and specifying encoding structure for a large class of FEC codes, scheduling the sending of packets and the like, are also applied in conjunction with the method for decoding data.

Abstract: Chien search apparatus operative to evaluate an error locator polynomial having a known rank and including a sequence of terms for each element in a finite field whose elements correspond respectively to bits in each of a stream of data blocks to be decoded, the apparatus comprising a sequence of functional units each operative to compute a corresponding term in the sequence of terms included in the error locator polynomial, each term having a degree; and a power saving unit operative to de-activate at least one individual functional unit from among the sequence of functional units, the individual functional unit being operative, when active, to compute a term whose degree exceeds the rank.

Abstract: A low density parity check (LDPC) code is used within a wireless apparatus to perform forward error correction (FEC) coding. In at least embodiment of the invention, a (2000, 1600) bit-length LDPC code is used.

Abstract: Tail-biting turbo coding to accommodate any information and/or interleaver block size. A means is presented by which the beginning and ending state of a turbo encoder can be made the same using a very small number of dummy bits. In some instances, any dummy bits that are added to an information block before undergoing interleaving are removed after interleaving and before transmission of a turbo coded signal via a communication channel thereby increasing throughput (e.g., those dummy bits are not actually transmitted via the communication channel). In other instances, dummy bits are added to both the information block that is encoded using a first constituent encoder as well as to an interleaved information block that is encoded using a second constituent encoder.

Abstract: A method to generate an erasure locator polynomial in an error-and-erasure decode. The method generally includes the steps of (A) storing current values in multiple registers at a current moment, (B) generating first values by multiplying each current value by a respective one of multiple constants, (C) generating second values by gating at least all but one of the first values with a current one of multiple erasure values of an erasure position vector, (D) generating next values by combining each one of the second values with a corresponding one of the first values, (E) loading the next values into the registers in place of the current values at a next moment and (F) generating an output signal carrying the current values at a last moment such that the current values form the coefficients of the erasure locator polynomial.

Abstract: A transmission apparatus includes: a CRC encoding processing unit configured to include a plurality of generating polynomials for an CRC encoding processing with each of a plurality of data of which the code lengths differ as a target, and employ the optimal generating polynomial out of the plurality of generating polynomials to perform the CRC encoding processing; and a transmission unit configured to transmit data obtained by the CRC encoding processing unit performing the CRC encoding processing.

Abstract: Aspects describe a transmit driver that processes data communication between a scheduler and a turbo encoder. Transmit driver receives a request for a super frame and ascertains whether it has enough information to start the super frame. If there is enough data, the super frame is written to an appropriate hardware register. Both Direct Memory Access (DMA) and non-DMA hardware can be supported with the one or more aspects. In an aspect, a method is provided for data transmission. The method includes obtaining data comprising one or more logical channels wherein each of the logical channels comprises one or more code blocks, and wherein each of the code blocks comprises one or more turbo groups, organizing the data based on the one or more code blocks to produce time-sequenced turbo groups, and outputting the time-sequenced turbo groups.

Abstract: A data transfer method for connecting a master unit on an upstream side and a plurality of slave units on an downstream side in series with serial bus by a daisy chain system and transferring data having an appended error check code or error correction code between a data transmitter and a data receiver, the data transfer method including: transferring the data flowing in the serial bus in the slave unit from the data transmitter to the data receiver without performing an error check or error correction; performing an error check of the data in a circuit provided in the slave unit aside from a circuit in which the data flow; and informing a result of the error check to the master unit individually by the slave unit, which has performed the error check of the data.

Abstract: An automatic CRC format detection and selection device observes FCS errors during an interval, incrementing counts thereof. When a determination is made that an error count threshold has been met, the CRC format may be automatically changed in order to enable CRC format detection and switching without requiring a user to have knowledge of the format or how to accomplish its change.

Abstract: Provided is a systematic encoder of cyclic codes for partially written codewords in flash memories wherein all bits of an erased but unwritten area have a default value such as one. In the case where the host writes data to one or a plurality of discontinuous fragments in an area reserved for storing the message section of a codeword in the flash memory, the encoder computes the parity of the codeword by using only the data written to the flash memory as input and by asserting that all bits in the gaps between the written fragments have the default erased value, such that after both the data and the parity are written to the flash memory, the area reserved for storing the codeword would contain a valid codeword. On read back, the host reads the entire codeword area from the flash memory without having to distinguish between the written and unwritten fragments.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for improving latency by offsetting cyclic redundancy check lanes from data. In some embodiments, a memory device includes a memory array to provide read data bits and a cyclic redundancy code (CRC) generator to generate CRC bits corresponding to the read data bits. In addition, the memory device may include a transmit framing unit to transmit the read data bits and the CRC bits to a host, wherein the transmit framing unit includes logic to offset the transmission of the CRC bits from the transmission of the read data bits based, at least in part, on an offset value. Other embodiments are described and claimed.

Abstract: Techniques for generating cyclic redundancy check (CRC) values are provided. Bit messages that are to be transmitted to recipients are aligned to desired byte boundaries for purposes of generating CRC values, which are to be sent with the bit messages. The CRC values are rewound or adjusted back to values associated with original lengths of the bit messages before the CRC values are transmitted or forwarded with the bit messages to recipients.

Abstract: The present invention concerns a method of coding information symbols according to a code defined on a Galois field Fq, where q is an integer greater than 2 and equal to a power of a prime number, and of length n=p(q?1), where p>1. This coding is designed so that there exists a corresponding decoding method, also disclosed by the invention, in which the correction of transmission errors essentially comes down to the correction of errors in p words of length (q?1) coded according to Reed-Solomon. The invention is particularly advantageous when, through a suitable choice of parameters, the code according to the invention is an algebraic geometric code: in this case, it is possible to correct the transmission errors by the method already mentioned and/or by a conventional method which is less economical but has a higher performance.

Abstract: Methods and apparatus are provided for more efficiently implementing error checking code circuitry on a programmable chip. In one example, Cyclic Redundancy Check (CRC) exclusive OR (XOR) circuitry is decomposed to allow efficient implementation on lookup tables (LUTs) of various sizes on a device. XOR cancellation factoring is used to break up wide CRC XORs into blocks that fit in various LUTs while maintaining focus on minimizing logic depth and logic area. Simulated annealing is used to further reduce logic area cost.

Abstract: Error detection and error location determination circuitry is provided for detecting and locating soft errors in random-access-memory arrays on programmable integrated circuits. The random-access-memory arrays contain rows and columns of random-access-memory cells. Some of the cells are loaded with configuration data and produce static output signals that are used to program associated regions of programmable logic. Cyclic redundancy check error correction check bits are computed for each column of each array. The error correction check bits are stored in corresponding columns of cells in the array. During normal operation of an integrated circuit in a system, the cells are subject to soft errors caused by background radiation strikes. The error detection and error location determination circuitry contains linear feedback shift register circuitry that processes columns of array data. The circuitry continuously processes the data to identify the row and column location of each error.

Abstract: In some embodiments, a chip includes a memory core, error detection circuitry, and a control unit. The error detection circuitry determines the validity of error detection signals associated with speculative and non-speculative commands received by the chip and to provide validity signals indicative of the determined validity. The control unit provides the speculative commands to the memory core to be acted on before the control unit receives the associated validity signals and to provide the non-speculative commands to the memory core to be acted on only after receiving associated validity signals that indicate the associated error detection signals are valid. Other embodiments are described and claimed.

Abstract: The resistance against recording defects of a write-once optical disk is enhanced allowing realtime recording and playback of data streams with a single speed disk drive. A data stream is recorded in data blocks on the optical disk. An error correction block for one or more data blocks is generated and written on the same optical disk during recording. A spare data area is kept blank on the storage medium and used for storing a defect data block reconstructed by using the error correction block.

Abstract: Methods and apparatus are provided for N+1 packet level mesh protection. An error correction encoding method is provided that assembles M-T data packets; appends a sequence number and a payload integrity check to each of the M-T data packets; and creates T protection packets having the sequence number and payload integrity check, wherein a payload for each of the T protection packets are formed from corresponding symbols in the M-T data packets. An error correction decoding method is also provided that receives a plurality of error-free packets and one or more packets having an error; and reconstructs the one or more packets having an error by applying block erasure decoding to said plurality of error-free packets, whereby one packet having an error can be reconstructed for each protection packet used to encode the received packets.

Abstract: A generator may include a monitoring unit, an engine unit and/or a register. The monitoring unit may selectively extract at least a portion of data to be transmitted to, or received from, an external communication device. The engine unit may generate an error check code using a polynomial expression or a checksum according to a transmission format associated with the extracted data. The register may store the generated error check code.

Abstract: A decoder for error correction an encoded message, such as one encoded by a turbo encoder, with reduced iterations due to an improved stopping criterion. The decoder includes an error correction loop that iteratively processes a message that is encoded prior to transmittal over a communication channel. The error correction loop generates, such as with a Reed-Solomon decoder, an error location polynomial in each iterative process. A stopping mechanism in the decoder allows an additional iteration of the message decoding based on the error location polynomial, such as by obtaining the degree of the error location polynomial and comparing it to a threshold. In one example, the threshold is the maximum number of symbol errors correctable by the Reed-Solomon code embodied in the decoder. The stopping mechanism allows additional iterations when the stopping criterion (or polynomial degree) is greater than the maximum number of symbol errors correctable by the Reed-Solomon code.

Abstract: A method for wireless data transmission between a base station and one or more, in particular passive, transponders is provided, in which electromagnetic carrier waves are emitted by the base station. Data comprising successive characters are transmitted from a respective transponder to the base station by modulation and backscattering of the electromagnetic carrier waves, and a respective one of the characters is coded and transmitted by a respective transponder within a predefined time interval. Within at least one of the predefined time intervals, a safeguard character formed from the data to be transmitted is transmitted in addition to the character to be transmitted.

Abstract: Apparatus for vector generation is described. A vector generator is associated with a discrete power series symmetric about at least one term and configured to provide vectors, such as QSvectors for a Turbo Code for example. The vectors are each provided in separate portions as a first portion and a second portion. The second portion of a vector of the vectors is generated from the first portion of the vector using symmetry about the at least one term.

Abstract: The present disclosure provides an apparatus and method for generating a Galois-field syndrome. One exemplary method may include loading a first data byte from a first storage device to a first register and loading a second data byte from a second storage device to a second register; ANDing the most significant bit (MSB) of the first data byte and a Galois-field polynomial to generate a first intermediate output; XORing each bit of the first intermediate output with the least significant bits (LSBs) of the first data byte to generate a second intermediate output; MUXing the second intermediate output with each bit of the first data byte to generate a third intermediate output; XORing each bit of the third intermediate output with each bit of the second data byte to generate at a fourth intermediate output; and generating a RAID Q syndrome based on, at least in part, the fourth intermediate output. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

Abstract: An HDLC accelerator includes a deframer and framer to respectively accelerate the deframing and framing processes for PPP packets. The deframer includes an input interface unit, a detection unit, a conversion unit, and an output interface unit. The input interface unit receives a packet of data to be deframed. The detection unit evaluates each data byte to detect for special bytes (e.g., flag, escape, and invalid bytes). The conversion unit deframes the received data by removing flag and escape bytes, “un-escaping” the data byte following each escape byte, providing a header word for each flag byte, and checking each deframed packet based on a frame check sequence (FCS) value associated with the packet. The output interface unit provides deframed data and may further perform byte alignment in providing the deframed data. A state control unit provides control signals indicative of specific tasks to be performed for deframing.

Abstract: A system and method, associated with a receiver, for increasing the range or bandwidth of a wireless digital communication network and a receiver incorporating the system or the method. In one embodiment, the system includes: (1) a service class detector configured to determine a service class of a PDU received by the receiver from the wireless digital communication network and (2) a frame check sequence checker coupled to the service class detector and configured to disregard error-checking information in the PDU when the service class indicates that the PDU is a streaming media PDU.

Abstract: A transmitting/receiving unit for asynchronous data transmission has a CRC unit and a transmission FIFO in a transmission path. A coding unit for SLIP-coding of data to be transmitted can optionally be connected in the transmission path. Furthermore, a CRC unit and a reception FIFO are arranged in the reception path of the module. A decoding unit for SLIP-decoding of received data can optionally be connected in the reception path. The unit is connected to a data bus, in which case a DMA unit can also be connected to the data bus.

Abstract: A system and method for preventing user-input text strings of illegal lengths from being submitted to a database where, for each character in the string, a character length is determined in quantities of digital units of storage according to an encoding schema, the character lengths are accumulated into a total string length, also measured in digital units of storage, and the total string length is compared to one or more database input field requirements such as non-null and maximum length specifications. If a limit is not met, the system and method are suitably disposed in a manner to block or prevent submission of the user-input string to the database. Overflow sub-strings are extracted and stored from input strings which exceed the input length limit, and are further processed to yield additional storage and resource allocation.

Abstract: Apparatus and method for coding a block low density parity check (LDPC) code. Upon receiving an information word vector, an encoder codes the information word vector into a block LDPC code according to a predetermined generation matrix. A modulator modulates the block LDPC code into a modulation symbol using a predetermined modulation scheme. A transmitter transmits the modulation symbol.

Abstract: A retransmission control method comprising: generating N parity check matrices; generating a generator matrix containing a check symbol generator matrix contained in the first parity check matrix; transmitting the codeword generated by using the generator matrix to another communications device; generating, when the communications device receives a NAK in response to the codeword, a first additional parity by using the second parity check matrix; and retransmitting the first additional parity to the another communications device.

Abstract: A method of encoding data using low density parity check (LDPC) code defined by a m×n parity check matrix is disclosed. More specifically, the method includes encoding input source data using the parity check matrix, wherein the parity check matrix comprises a plurality of z×z sub-matrices of which row weights and column weights are ‘0’ or ‘1’.

Abstract: An error correcting device for correcting erroneous data included in data read out from a nonvolatile memory includes a determining unit that determines whether the data read out from the nonvolatile memory include an error beyond an error correcting capability of the error correcting device. When the determining unit has determined that an error beyond the error correcting capability exists, the error correcting device does not perform the correction of the error.

Abstract: A channel interleaving method and apparatus in a communication system using a low density parity check (LDPC) code. Upon receipt of information data bits, an encoder encodes the information data bits into an LDPC codeword using a predetermined coding scheme. A channel interleaver interleaves the LDPC codeword according to a predetermined channel interleaving rule. A modulator modulates the channel-interleaved LDPC codeword into a modulation symbol using a predetermined modulation scheme.

Abstract: A method of encoding data using low density parity check (LDPC) code defined by a m×n parity check matrix is disclosed. More specifically, the method includes encoding input source data using the parity check matrix, wherein the parity check matrix comprises a plurality of z×z sub-matrices of which row weights and column weights are ‘0’ or ‘1’.