Abstract: A memory device includes an error detection and correction system with an error correcting code over GF(2n), wherein the system has an operation circuit configured to execute addition/subtraction with modulo 2n?1, and wherein the operation circuit has a first operation part for performing addition/subtraction with modulo M and a second operation part for performing addition/subtraction with modulo N (where, M and N are integers which are prime with each other as being obtained by factorizing 2n?1), and wherein the first and second operation parts perform addition/subtraction in parallel to output an operation result of the addition/subtraction with modulo 2n?1.

Abstract: A method of encoding data using low density parity check (LDPC) code defined by a m×n parity check matrix is disclosed. More specifically, the method includes encoding input source data using the parity check matrix, wherein the parity check matrix comprises a plurality of z×z sub-matrices of which row weights and column weights are ‘0’ or ‘1’.

Abstract: Systems and methods are provided for performing error correction decoding. The coefficients of the error locator polynomial are iteratively determined for each codeword using a modular implementation of a single recursion key-equation solver algorithm. According to this implementation, modules are used to calculate the current and previous coefficients of the error locator polynomial. One module is used for each correctable error. The modular single recursion implementation is programmable, because the number of modules can be easily changed to correct any number of correctable errors. Galois field tower arithmetic can be used to calculate the inverse of an error term. Galois field tower arithmetic greatly reduces the size of the inversion unit. The latency time can be reduced by placing the computations of the inverse error term outside the critical path of the error locator polynomial algorithm.

Abstract: A system and method for providing a cyclical redundancy code (CRC) for use in a high-speed serial link. The system includes a cascade interconnect memory system including a memory controller, a memory hub device and a downstream link. The downstream link is in communication with the memory controller and the memory hub device and includes at least thirteen signal lanes for transmitting a multiple transfer downstream frame from the memory controller to the memory hub device. A portion of the downstream frame includes downstream CRC bits to detect errors in the downstream frame. The downstream CRC bits capable of detecting any one of a lane failure, a transfer failure and up to five bit random errors.

Abstract: Input data (1A) having an integral multiple of 8 bits is divided into symbols in units of b bits (b is an integer of 5 to 7) in a register file 10, an error detecting code is added in an error detection calculation circuit 20, and then encoding (such as Reed Solomon (RS) encoding) having an error correction capability of two or more symbols is performed in a parity calculation circuit 30 to record the data in a storage 40. In the reproduction, error correction in units of symbols is performed to reproduced data from the storage 40 in an error correction circuit 70, error detection processing is performed in an error detection calculation circuit 80, and then data having the integral multiple of 8 bits is recovered in a register file 90 to output the same. By this means, it is possible to provide a storage system with high reliability to a soft error that occurs in a storage such as semiconductor memory.

Abstract: A method includes receiving a detected sequence representing a signal on a channel. The detected sequence includes data bits and one or more error detection code bits. One or more error indications are received for the detected sequence. Each of the one or more error indications identifies one of the data bits of the detected sequence that may have an erroneous value. Errors are detected in the detected sequence based on the error detection code bits in the detected sequence. When errors are detected in the detected sequence, a candidate sequence is generated based on the detected sequence and the one or more error indications.

Abstract: An EDC generating circuit includes a memory unit, an EDC generating module, a header generator and an EDC correcting circuit. The EDC generating module, which is coupled to the memory unit, is used for generating a first EDC according to at least one main data, and for storing the first EDC to the memory unit. The header generator, which is coupled to the memory unit, is used for generating a header according to header information. The EDC correcting circuit, which is coupled to the memory unit, is used for reading the first EDC from the memory unit and for correcting the first EDC according to the header to generate a second EDC.

Abstract: A method of encoding data using low density parity check (LDPC) code defined by a m×n parity check matrix is disclosed. More specifically, the method includes encoding input source data using the parity check matrix, wherein the parity check matrix comprises a plurality of z×z sub-matrices of which row weights and column weights are ‘0’ or ‘1’.

Abstract: A system to improve miscorrection rates in error control code may include an error control decoder with a safe decoding mode that processes at least two data packets. The system may also include a buffer to receive the processed at least two data packets from the error control decoder. The error control decoder may apply a logic OR operation to the uncorrectable error signal related to the processing of the at least two data packets to produce a global uncorrectable error signal. The system may further include a recipient to receive the at least two data packets and the global uncorrectable error signal.

Abstract: An LFSR module is configured according to a characteristic polynomial for generating an output stream according to an input stream. The LFSR module has several LFSRs coupled together and an output generator. Each LFSR respectively receives a sub-input stream and at least one feedback stream, and respectively generates a sub-output stream and a feedback stream according to the received sub-input stream and the received at least one feedback stream, wherein the sub-input stream is generated according to the input stream, and at least one of the received feedback streams is generated by another LFSR. The output generator generates the output stream according to a plurality of inputs, wherein some of the inputs are the sub-output streams of the LFSRs.

Abstract: The present invention discloses an apparatus and method for performing cyclic redundancy check (CRC) on partial protocol data units (PDUs). The disclosed apparatus is designed to off-load the CRC calculation for transmit or receive from a host computer. According to the disclosed method, when generating CRC for partial PDUs, for each such PDUs a decision is made to determine whether a CRC action is required, i.e., if CRC should be calculated, checked or placed in the outgoing byte stream. When partial CRC calculation is performed the intermediate value is saved into memory and later is used for calculating the CRC for a consecutive partial PDU. In accordance with a preferred embodiment of the invention, the need to re-calculate the CRC in a case of a re-transmit request is eliminated.

Abstract: Algebraic method to construct LDPC (Low Density Parity Check) codes with parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. A novel approach is presented by which identity sub-matrices undergo cyclic shifting, thereby generating CSI sub-matrices that are arranged forming a parity check matrix of an LDPC code. The parity check matrix of the LDPC code may correspond to a regular LDPC code, or the parity check matrix of the LDPC code may undergo further modification to transform it to that of an irregular LDPC code. The parity check matrix of the LDPC code may be partitioned into 2 sub-matrices such that one of these 2 sub-matrices is transformed to be a block dual diagonal matrix; the other of these 2 sub-matrices may be modified using a variety of means, including the density evolution approach, to ensure the desired bit and check degrees of the irregular LDPC code.

Abstract: A writing method of a memory module comprises temporarily storing a piece of 2m-byte data as p characters, wherein each character comprises q bits, and m, p and q are positive integers; rearranging the 2m-byte data to obtain K symbols, wherein each symbol has m bits and K is a positive integer smaller than 2m; encoding the K symbols into a codeword according to a Reed-Solomon (RS)-code algorithm, wherein the codeword comprises N symbols, the codeword has a parity code, the parity code comprises (2T=N?K) symbols, and N and T are positive integers; and writing the p characters and the parity code into a memory-cell array, wherein all the symbols belong to a finite field GF(2m).

Abstract: The present invention aims at providing an encoding device for error correction, encoding method for error correction and encoding program for error correction wherein countermeasures against eavesdropping are taken into account. To achieve this, in accordance with an aspect of the present invention there is provided an encoding device for error correction, the device comprises a generation means for generating randomly a vector u=(xk+1, . . . , xm) composed of m-k digit(s); a creation means for creating an x?=[xu]=(x1, . . . , xm) by concatenating the vector u=(xk+1, . . . , xm) composed of m-k digit(s) randomly created by the creation means to data x=(x1, . . . , xk) to send; and an output means for outputting a vector of length n by carrying out [n, m] encoding of the x? created by the creation means.

Abstract: Error protection based on a nonlinear code set may be used in a multiple input multiple output (MIMO) radio communications system. A decoder decodes received MIMO data streams and generates an automatic repeat request (ARQ) message for data units received for the MIMO data streams for each transmission time interval. An encoder codes the ARQ message using a code word from a nonlinear code set. At the data transmitter, which transmits one or more data units in transmission time intervals from two or more MIMO data streams, the ARQ message associated with the transmitted data units is decoded using a code word from the nonlinear code set.

Abstract: A coding circuit that includes a buffer manager and a coding block is provided for generating product codes for parity checks as error correction code and adding the product codes to digital data to be recorded in a record medium.

Abstract: Method and system for data-rate control by randomized bit-puncturing in communication systems. An encoder encodes at least one information bit thereby generating a group of encoded bits or an encoded frame. The encoder may be any type of encoder including a turbo encoder, an LDPC (Low Density Parity Check) encoder, a RS (Reed-Solomon) encoder, or other type of encoder. Any sub-portion of an encoded frame generated by such an encoder can be viewed as being a group of encoded bits. If the encoded frame is sub-divided into multiple groups of bits, each group can under processing in accordance with the means presented herein to effectuate rate matching. Based on a number of bits to be punctured from the group or frame generated by the encoder, a set of pointers and random-generated displacements is used to generate addresses for bits in the group or frame to be transmitted or punctured.

Abstract: A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC bit and transmitting the coded PMI and EC bit.

Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to store a block of data values arranged in a first order. The first circuit may be further configured to present a plurality of the data values in parallel in response to a plurality of address signals, where the data values are presented in a second order. The second circuit may be configured to generate the plurality of address signals in response to a first signal, a second signal and a third signal. The second circuit generally includes an even number of address generators configured to generate the plurality of address signals in parallel.

Abstract: A Redundant Array of Inexpensive Disks (RAID) controller comprises a RAID error correction code (ECC) encoder module that receives data for storage and that generates code words for data drives and one or more parity drives, which have physical locations. The code words are generated based on the data and a cyclic code generator polynomial. Logical locations correspond to index positions in the cyclic code generator polynomial. A mapping module maps the physical locations of the data and parity drives to the logical locations. The mapping module adds a new data drive to an unused one of the logical locations. A difference generating module generates a difference code word based on the new data drive. The RAID ECC encoder module encodes the difference code word and adds the encoded difference code word to an original code word generated before the new data drive is added.

Abstract: A system corrects errors in a codeword. The system includes a channel that sorts reliability numbers of symbols in the codeword to create an ordered list of candidate erasure locations. The system also includes a generalized minimum distance decoder that iteratively processes the ordered list of candidate erasure locations and at least two syndromes of the codeword using a single-shot key equation solver to generate an error locator polynomial and an error evaluator polynomial. The generalized minimum distance decoder processes the least reliable candidate erasure locations first within the ordered list of candidate erasure locations.

Abstract: A cyclic redundancy check generator includes a plurality of shift registers, each shift register corresponding to a coefficient of a general polynomial key word. A plurality of programmable registers are programmed based on a specific polynomial key word. The specific key word programmed to the plurality of programmable registers is compared to the general polynomial key word to determine which shift registers corresponding to coefficients of the general polynomial key word are to take a predetermined value in order to convert the general polynomial key word into the specific polynomial key word.

Abstract: A cyclic redundancy check (“CRC”) generator and method therefor are described. Checksum bits and checksum enable bits are bitwise ANDed to provide interim checksum outputs. The interim checksum outputs are XORed to provide resultant checksum outputs. Data bits and data enable bits are bitwise ANDed to provide interim data outputs. The interim data outputs are XORed to provide resultant data outputs. The resultant checksum outputs and the resultant data outputs are bitwise XORed to provide parity outputs.

Abstract: Integrated interleaved encoding is performed by obtaining a first piece of input data and a second piece of input data. The first piece of input data is systematically encoded using a first generator polynomial to obtain a first codeword. A second codeword is generated based at least in part on the second piece of input data and the first codeword. This includes by systematically encoding information based at least in part on the second piece of input data and the first codeword using a second generator polynomial. The first codeword and the second codeword are output.

Abstract: A video decoder capable of generating a check data in response to a data selection code for debugging is disclosed. The video decoder includes a plurality of functional blocks, wherein each said plurality of functional blocks has a output signal to be used as an input signal for a next stage functional block; a multiplexer (209) that receives a plurality of data extracted from said plurality of output signals from said plurality of functional blocks, and outputs one of said plurality of data according to said data selection code; and a check logic (210) that generates said check data by calculating one of said plurality of data outputted from said multiplexer.

Abstract: An approach is provided for encoding information bits to output a coded signal using turbo code encoding with a low code rate.

Abstract: An approach is provided for efficiently decoding low density parity check (LDPC) codes. A plurality of parallel processors decode the LDPC codes mapped by accessing a mapped matrix in a memory structure. The mapped matrix is constructed based on a parity check matrix of the LDPC codes. No two different entries in an identical row of the mapped matrix connects to identical bit nodes or identical check nodes.

Abstract: A cryptographic system (CS) comprised of generators (502), (504), (510), an encryption device (ED), and a decryption device (DD). The generator (502) generates a data sequence (DS) including payload data. The generator (504) generates an encryption sequence (ES) including random numbers. The ED (506) is configured to perform a CGFC arithmetic process. As such, the ED is comprised of a mapping device (MD) and an encryptor. The MD is configured to map the DS and ES from Galois field GF[pk] to Galois extension field GF[pk+1]. The encryptor is configured to generate an encrypted data sequence (EDS) by combining the DS and ES utilizing a Galois field multiplication operation in Galois extension field GF[pk+1]. The generator (510) is configured to generate a decryption sequence (DS). The DD (508) is configured to generate a decrypted data sequence by performing an inverse of the CGFC arithmetic process utilizing the EDS and DS.

Abstract: A method for generating block codes from Golay code and a method and apparatus for encoding data are provided. The method can effectively generate codes having various lengths, various dimensions, and superior hamming weight distribution, and encodes data such as control information having various lengths into codes having strong resistance to channel errors, resulting in an increase of error correction performance.

Abstract: Provided is a low-density parity-check (LDPC) decoding apparatus and method using a type-classified index. The apparatus includes: a memory allocating unit for multiplying reception data by an estimated channel value and storing a multiplied value in a memory including a plurality of memory block; an index storing unit for storing a Read Only Memory (ROM) index, an address index and a permutation index for the stored data; a check node updating unit for bring the stored data in parallel based on the ROM index, the address index, and the permutation index and updating a check node; and a bit node updating unit for updating a bit node based on the data stored in the memory and check node information updated in the check node updating unit.

Abstract: Methods of data handling include receiving data having a previously-generated error correction code and generating one or more error correction codes for the data, with each error correction code corresponding to the data having one or more particular bits of the data in differing data states. Such methods further include comparing the generated one or more error correction codes to the previously-generated error correction code, and if a particular one of the generated one or more error correction codes matches the previously-generated error correction code, transmitting the data having its one or more particular bits in the data states corresponding to that particular one of the generated one or more error correction codes. Methods of data handling may further include prioritizing the error correction in response to at least locations of known bad or questionable bits of the data.

Abstract: Systems, methods, and devices are disclosed, including a device that includes a plurality of data locations, a quantizing circuit coupled to the plurality of data locations, and an error detection module coupled to the quantizing circuit. In some embodiments, the error detection module includes an encoder configured to encode incoming data with redundant data derived from the incoming data and a decoder configured to detect errors in stored data based on the redundant data.

Abstract: Irregular LDPC codes have a construction which allows one to obtain a number of codes with different length from a single prototype code with a parity check matrix given by H=[Hz Hi], where Hz specifies the well-known zigzag pattern in the corresponding Tanner graph. The parity check matrices for longer codes are obtained as [Hz??diag(Hi, . . . , Hi)], where Hz? specifies a longer zigzag pattern depending on the number of matrices Hi used, and ? represents some permutation. This allows one to construct the decoder for a longer code by reusing hardware components developed for decoding the prototype code.

Abstract: In general, the disclosure describes techniques for detecting and correcting single or multiple occurrences of data error patterns. This disclosure discusses the generation and application of high-rate error-pattern-correcting codes to correct single instances of targeted error patterns in codewords, and to further correct a significant portion of multiple instances of targeted error patterns, with the least redundancy. In accordance with the techniques, a lowest-degree generator polynomial may be constructed that targets a set of dominant error patterns that make up a very large percentage of all observed occurrences of errors. The lowest-degree generator polynomial produces distinct, non-overlapping syndrome sets for the target error patterns.

Abstract: A decoding method and system for stochastic decoding of linear codes with the parity check matrix comprising elements of a Galois field is provided. Each encoded sample of a set of encoded samples is first scaled by a scaling factor proportional to a noise level of the set of encoded samples. Each of the scaled encoded samples is then converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of symbols or bits. Each probability message is then provided to a respective variable node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear code.

Abstract: A data processing method includes the steps of: initializing a syndrome vector to be an (n?1)th symbol; finding a corresponding mask based on the syndrome vector, wherein the mask is zero when the (n?1)th symbol is zero; correcting a known constant, which is zero when the syndrome vector is zero, based on the mask; inputting the syndrome vector to a log look-up table to correspondingly find log data; performing a modulo addition operation corresponding to log maximum data to find a log sum based on the log data and a log known constant; and inputting the log sum to an anti-log look-up table to correspondingly find operational data.

Abstract: An apparatus, system and method can be arranged for coding and/or decoding with a phase invariant coding scheme that is useful for short burst signaling devices. 10-bit data is mapped into a 12-bit data with a non-coherent burst code mapper. A parity generator creates a 12-bit parity data to form a 24-bit extended binary Golay code from the 12-bit data. The values for selected bit fields in the 12-bit data and 12-bit parity data are swapped to generate I and Q data such that sensitivity to changes in rotational phase is removed. I and Q data can be used by a transmitter to transmit a rotationally-invariant signal. On receipt, I and Q signals can be recovered, reverse swapped to generate the parity and data signals, and remapped to recover the transmitted 10-bit data. The receiver can also be arranged to use a soft decoding method for improved signal integrity.

Abstract: A Galois Field multiplier circuit for multiplying two polynomials (multiplicands). The multiplier circuit can use any arbitrary primitive polynomial to preserve the Galois Field. The multiplier circuit includes at least one logic unit that receives as a first input one of the multiplicands and shift the multiplicand in question by 1 bit to the left. The logic unit receives as a second input a pre-determined primitive polynomial and multiplies the primitive polynomial by the highest bit of the multiplicand received at the other input of the logic unit. The bit-shifted multiplicand is XOR-ed with the primitive polynomial multiplied the highest bit of the multiplicand and the result of the XOR operation is provided to a second logic circuit that completes the multiplication of the two polynomials.

Abstract: An apparatus, system and method for detecting errors in a physical interface during the transmission or receipt of data communications between integrated circuits (“ICs”) are disclosed. In one embodiment, a physical interface formed as a first IC on a first substrate portion to detect transmission errors in data exchanged with a second IC formed on a second substrate portion, the physical interface including multiple input ports and output ports, including a first subset of input ports configured to receive in-bound encoded data bits and a first subset of output ports configured to transmit in-bound decoded data bits to the second IC; and one or more error recovery modules coupled between the plurality of input ports and output ports, where a first error recovery module of the one or more error recovery modules is coupled between at least one of the first subset of input ports and at least one of the first subset of output ports.

Abstract: A transmitting apparatus generates and transmits 3t+1 or more number of codewords for a message and multiple faulty encoded message identifying data, wherein the information regarding the message may not be obtained from t or less number of encoded messages and the message can be decoded from 2t+1 or more codewords. The faulty encoded message identifying data are able to detect t or less number of faulty codewords of the message, even if there are t or less number of faulty codewords. A receiving apparatus checks whether there is no fault in each codeword for the message, using the codewords of the message and faulty encoded message identifying data for the codewords of the message received and the corresponding faulty encoded message identifying data and also checks whether the codewords decided to be non-faulty are all of the same message.

Abstract: An apparatus, system and method can be arranged for coding and/or decoding with a phase invariant coding scheme that is useful for short burst signaling devices. 10-bit data is mapped into a 12-bit data with a non-coherent burst code mapper. A parity generator creates a 12-bit parity data to form a 24-bit extended binary Golay code from the 12-bit data. The values for selected bit fields in the 12-bit data and 12-bit parity data are swapped to generate I and Q data such that sensitivity to changes in rotational phase is removed. I and Q data can be used by a transmitter to transmit a rotationally-invariant signal. On receipt, I and Q signals can be recovered, reverse swapped to generate the parity and data signals, and remapped to recover the transmitted 10-bit data. The receiver can also be arranged to use a soft decoding method for improved signal integrity.

Abstract: An apparatus, system and method can be arranged for coding and/or decoding with a phase invariant coding scheme that is useful for short burst signaling devices. 10-bit data is mapped into a 12-bit data with a non-coherent burst code mapper. A parity generator creates a 12-bit parity data to form a 24-bit extended binary Golay code from the 12-bit data. The values for selected bit fields in the 12-bit data and 12-bit parity data are swapped to generate I and Q data such that sensitivity to changes in rotational phase is removed. I and Q data can be used by a transmitter to transmit a rotationally-invariant signal. On receipt, I and Q signals can be recovered, reverse swapped to generate the parity and data signals, and remapped to recover the transmitted 10-bit data. The receiver can also be arranged to use a soft decoding method for improved signal integrity.

Abstract: The present invention relates to a decoding method and system for stochastic decoding of linear block codes with parity check matrix. Each encoded sample of a set of encoded samples is converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of digital symbols. Each probability message is then provided to a respective node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear block code. Using the logic circuitry each probability message is processed for determining an estimated sequence of information symbols. If an equality node is in a hold state a chosen symbol is provided from a corresponding memory which is updated by storing output symbols from the equality node when the same is in a state other than a hold state.

Abstract: Certain aspects of a method and system for dynamically adjusting forward error correction (FEC) rate to adapt for time varying network impairments in video streaming applications over IP networks may be disclosed. At a server side of a client-server communication system, a rate of transmission of forward error correction (FEC) packets to one or more clients may be dynamically adjusted based on receiving at least one upstream FEC packet from a plurality of clients. The rate of transmission of the FEC packets to the plurality of clients may be increased when a rate of occurrence of lost data packets is above a particular threshold value. The upstream FEC packets may comprise an urgent packet requesting transmission of a particular FEC packet in order to recover one or more particular lost data packets.

Abstract: A method is disclosed of determining a coordinate value with respect to patterns printed on a document. Each pattern represents a sequence, with each sequence consisting of a repeating codeword of a cyclic position code. The pattern is sensed, and from each sensed pattern a respective sub-sequence of symbols is obtained. Each of the sub-sequences is then mapped to a respective mapped codeword of the cyclic position code. An offset between each mapped codeword and the codeword is determined, and a difference is derived between pairs of offsets. The coordinate value is derived by interpreting one of the differences as a marker separating the coordinate value from an adjacent coordinate value, and the remaining differences as digits of the coordinate value.

Abstract: An error correction system is disclosed comprising an encoder operable to generate an encoded codeword of a polynomial code over a Galois field GF(q) comprising q elements, wherein the encoded codeword comprises an input data sequence, at least one check symbol, and redundancy symbols. A decoder decodes a received codeword into the encoded codeword by correcting at least one error in the received codeword to generate a corrected codeword, evaluating at least one symbol of the corrected codeword relative to the check symbol in order to detect a shift error, and when the shift error is detected, shift the corrected codeword to correct the shift error.

Abstract: Systems and methods are disclosed for processing data. In one exemplary implementation, there is provided a method of generating H output data streams from W data input streams produced from input data. Moreover, the method may include generating the H discrete output data streams via application of the W data inputs to one or more transforming components or processes having specified mathematic operations and/or a generator matrix functionality, wherein the W data inputs are recoverable via a recovery process capable of reproducing the W data inputs from a subset (any W members) of the H output data streams. Further exemplary implementations may comprise a transformation process that includes producing an H-sized intermediary for each of the W inputs, combining the H-sized intermediaries into an H-sized result, and processing the H-sized result into the H output data streams.

Abstract: Coded video data may be transmitted between an encoder and a decoder using multiple FEC codes and/or packets for error detection and correction. Only a subset of the FEC packets need be transmitted between the encoder and decoder. The FEC packets of each FEC group may take, as inputs, data packets of a current FEC group and also an untransmitted FEC packet of a preceding FEC group. Due to relationships among the FEC packets, when transmission errors arise and data packets are lost, there remain opportunities for a decoder to recover lost data packets from earlier-received FEC groups when later-received FEC groups are decoded. This opportunity to recover data packets from earlier FEC groups may be useful in video coding and other systems, in which later-received data often cannot be decoded unless earlier-received data is decoded properly.

Abstract: A wireless communication device includes a receiver configured to receive a transport block with a sequence of bits wherein A is the number of bits, a first cyclic redundancy check (CRC) coder configured to generate a first block of CRC parity bits on a transport block and to associates the first block of CRC parity bits with the transport block, wherein a number of CRC parity bits in the first block is L, a segmenting entity configured to segment the transport block into multiple code blocks after associating when A+L is larger than 6144, a second CRC coder configured to generate a second block of CRC parity bits on each code block and to associate a second block of CRC parity bits with each code block, and a channel encoder configured to encode each of the code blocks including the associated second block of CRC parity bits if A+L>6144.

Abstract: A decoding apparatus for low density parity check codes includes a variable-to-check message generator and a check-to-variable message generator. The variable-to-check message generator includes a variable-to-check processing unit block, provided with an adder, and which is arranged between registers corresponding to locations of ‘1’s in a check matrix. The check-to-variable message generator includes a check-to-variable processing unit block, provided with a comparator, between registers corresponding to locations of ‘1’s in the check matrix. The decoding apparatus for low density parity check codes is simple in configuration and is able to perform high speed processing without using RAMs without the necessity of performing complex control operations.