Abstract: Systems and methods for constructing Reed-Solomon encoding matrices are provided that are simpler and more regular than existing techniques, and which allow for the coding to be applied to more data disks than previous techniques. More particularly, systems and methods for simplifying the construction of Reed-Solomon based erasure codes, or coding matrices, over GF(2^n) in connection with circumstances wherein the number of errors to be corrected is less than or equal to three are provided.

Abstract: The present invention discloses an apparatus and method for performing cyclic redundancy check (CRC) on partial protocol data units (PDUs). The disclosed apparatus is designed to off-load the CRC calculation for transmit or receive from a host computer. According to the disclosed method, when generating CRC for partial PDUs, for each such PDUs a decision is made to determine whether a CRC action is required, i.e., if CRC should be calculated, checked or placed in the outgoing byte stream. When partial CRC calculation is performed the intermediate value is saved into memory and later is used for calculating the CRC for a consecutive partial PDU. In accordance with a preferred embodiment of the invention, the need to re-calculate the CRC in a case of a re-transmit request is eliminated.

Abstract: Circuits, architectures, methods and algorithms for joint channel-code decoding of linear block codes, and more particularly, for identifying and correcting one or more errors in a code word and/or for encoding CRC (or parity) information. In one aspect, the invention focuses on use of (i) remainders, syndromes or other polynomials and (ii) Gaussian elimination to determine and correct errors. Although this approach may be suboptimal, the present error checking and/or detection scheme involves simpler computations and/or manipulations than conventional schemes, and is generally easier to implement logically.

Abstract: In an embodiment of the invention, an integrated circuit comprises an input module configured to receive a first data segment, an identifier module having a hard coded identifier, a processing module coupled to the input module and coupled to the identifier module and configured to process the first data segment with the hard coded identifier to generate a first error correction code, and an output module configured to transfer the first error correction code for storage on a storage system.

Abstract: An error correction coding method using a low-density parity-check code includes: dividing an information bit sequence to be processed for error correction coding, into (m?r) pieces of first blocks each comprising a bit sequence having a length n and r pieces of second blocks comprising respective bit sequences having lengths k1, k2, . . . , kr; a first arithmetic operation for performing polynomial multiplication on the (m?r) pieces of first blocks, and outputting r pieces of bit sequences having a length n; and a second arithmetic operation for performing a polynomial division and a polynomial multiplication on the r pieces of second blocks and r pieces of operation results of the first arithmetic operation, and outputting a bit sequence including redundant bit sequences having respective lengths n?k1, n?k2, . . . , n?kr.

Abstract: Embodiments of the invention provide methods and systems for improving the reliability of data stored on disk media. Logical redundancy is introduced into the data, and the data within a logical storage unit is divided into sectors that are spatially separated by interleaving them with sectors of other logical storage units. The logical redundancy and spatial separation reduce or minimize the effects of localized damage to the storage disk, such as the damage caused by a scratch or fingerprint. Thus, the data is stored on the disk in a layout that improves the likelihood that the data can be recovered despite the presence of an error that prevents one sector from being read correctly.

Abstract: An apparatus, system, and method are disclosed for mandatory end to end integrity checking. The apparatus includes a compatibility module configured to monitor data from a source and verify integrity information compatibility with a standard, and an integrity module configured to wrap the data from the source with additional integrity information. The system includes a source configured to send data over a network, a target configured to receive data over the network, the apparatus, a main memory module, a storage controller, and a storage device. The method includes monitoring data from a source, verifying integrity information compatibility with a standard, and wrapping the data from the source with additional integrity information.

Abstract: Herein described is a system and a method of detecting and correcting data bit errors using a sequence of one or more codewords transmitted through a communication channel without intersymbol interference. Each of the one or more codewords incorporates or encodes one or more parity bits. The codewords are processed by a Non-ISI Meta-Viterbi detector that utilizes a Meta-Viterbi algorithm. The Non-ISI Meta-Viterbi detector comprises an event weight processor, a computational circuitry, a parity syndrome calculator, and an error correction circuitry. The Non-ISI Meta-Viterbi detector receives an output generated from a symbol detector and processes the received output using a trellis having 2t states. In a representative embodiment, the Non-ISI Meta-Viterbi detector performs ?+2t2t add, compare, and select operations.

Abstract: In a communication system, information data bits are encoded in a preset coding scheme when the information data bits are input, and a Low Density Parity Check (LDPC) codeword is generated. The LDPC codeword is interleaved according to a preset channel-interleaving rule. A channel-interleaved LDPC codeword is modulated in a preset modulation scheme and a modulation symbol is generated.

Abstract: An error correction device, an error correction program and an error correction method can reduce the processing time necessary for the process of correcting errors that involve erasure in a reception word by using a software and hardware properly and effectively. As an error-correcting circuit for correcting errors that do not involve erasure receives a reception word that involves erasure from an RDC, an erasure information holding section holds the erasure information and a syndrome generating section generates a syndrome from the reception word so that a erasure judging section transmits the erasure information and the syndrome to an MPU. In the MPU, an erasure error value computing section and erasure correcting section correct only erasure and store the reception word that does not involve erasure in an RAM. The reception word from the RAM is input again to the error-correcting circuit for correcting errors that do not involve erasure by way of a data bus and a switch.

Abstract: A method of calculating parity for an m-storage element failure in a networked array of storage elements. A first set of n XOR relationships is derived, each first set relationship containing n data symbols from n storage elements and one parity symbol from a first set of parity symbols. A second set of n XOR relationships is derived, each second set relationship containing at least n?1 data symbols from at least n?1 storage elements and one parity symbol from a second set of parity symbols. Additional sets of relationships are derived such that a total of m sets of relationships are derived. Each of the additional sets of relationships are composed of up to (n+i?1)Ci?1 relationships, where i indicates the numbered set of relationship. Using the first, second and additional sets of derived relationships, scripts are generated to resolve unresolved symbols resulting from possible m-storage element failure combinations.

Abstract: We investigate error-correcting codes for a novel storage technology, which we call the rank-modulation scheme. In this scheme, a set of n cells stores information in the permutation induced by the different levels of the individual cells. The resulting scheme eliminates the need for discrete cell levels, and overshoot errors when programming cells (a serious problem that reduces the writing speed), as well as mitigates the problem of asymmetric errors. In this discussion, the properties of error correction in rank modulation codes are studied. We show that the adjacency graph of permutations is a subgraph of a multi-dimensional array of a special size, a property that enables code designs based on Lee-metric codes and L1-metric codes. We present a one-error-correcting code whose size is at least half of the optimal size. We also present additional error-correcting codes and some related bounds.

Abstract: Construction of LDPC (Low Density Parity Check) codes using GRS (Generalized Reed-Solomon) code. A novel approach is presented by which a GRS code may be employed to generate a wide variety of types of LDPC codes. Such GRS based LDPC codes may be employed within various types of transceiver devices implemented within communication systems. This approach may be employed to generate GRS based LDPC codes particular designed for various application arenas. As one example, such a GRS based LDPC code may be specifically designed for use in communication systems that operate in accordance with any standards and/or recommended practices of the IEEE P802.3an (10GBASE-T) Task Force.

Abstract: A system and method for Bluetooth® decoding is disclosed and may include calculating a remainder value based on a received bit sequence and a generator polynomial for a corresponding transmitted Bluetooth bit sequence. Remainders may be generated from known error vectors and the generator polynomial. The generated remainders may result in at least a portion of the known error vectors corresponding to the generator polynomial. A codeword may be selected that may correspond to the calculated reminder value that matches one of the generated remainders. The generated remainders may be stored in a look-up table. An initial metric value may be calculated utilizing the following equation: M 0 = ? n = 0 14 ? ? abs ? ( RX ? ( n ) ) , where RX(n) may include the received bit sequence. The codeword with a metric value equal to M0 may be selected, if the calculated remainder value is equal to 0.

Abstract: Single CRC polynomial for both turbo code block CRC and transport block CRC. Rather than employing multiple and different generation polynomials for generating CRC fields for different levels within a coded signal, a single CRC polynomial is employed for the various levels. Effective error correction capability is achieved with minimal hardware requirement by using a single CRC polynomial for various layers of CRC encoding. Such CRC encoding can be implemented within any of a wide variety of communication devices that may be implemented within a wide variety of communication systems (e.g., a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system, etc.). In addition, a single CRC check can be employed within a receiver (or transceiver) type communication device for each of the various layers of CRC of a received signal.

Abstract: To eliminate the need for buffering in order to calculate data length information on data as an object of computation, a first exclusive-OR unit 53 executes computation of exclusive-OR of a cyclic code R(x) of the integral multiple bit bits block A(x) and a data string of M bits, containing the fraction bits block B(x). A first shifting unit 54 shifts the exclusive-OR of the cyclic code R(x) and the data string of M bits, containing the fraction bits block B(x), by {M?H(k)} bits toward a least significant side, where M is a parallel width and H(k) is a bit length of the fraction bits block B(x). An R?(x) generation unit 55 generates a cyclic code R?(x) that is a cyclic code of the data after shifting. To obtain R?(x), a second shifting unit 56 shifts the cyclic code R(x) by H(k) bits toward a most significant side. A second exclusive-OR unit 57 executes computation of exclusive-OR of the cyclic code R?(x) and data R?(x).

Abstract: A method of decoding linear block code uses an iterative message passing algorithm with a binary image of a parity check matrix of the linear block code, wherein the parity check matrix is adapted from one iteration to another based on the reliabilities of bits in the linear block code. The adaptation involves reducing a submatrix corresponding to the less reliable bits in the linear block code to a sparse nature before applying the message passing algorithm in each iteration. An apparatus that performs the method is also provided and several variations of the algorithm are also provided.

Abstract: Provided are an encoder and a syndrome computer for cyclic codes which process M codeword symbols per cycle where M is greater than or equal to one, whereby the encoder and syndrome computer optionally further provide the configurability of a different M value for each cycle and/or the configurability of a different cyclic code for each codeword. Further provided is a hybrid device which provides the configurability of two modes of operation, whereby in one mode, the hybrid device functions as the encoder as provided above and, in the other mode, the hybrid device functions as the syndrome computer as provided above, with the majority of the components of the hybrid device being shared between the encoding function and the syndrome computing function.

Abstract: Encoder circuitry for applying a low-density parity check (LDPC) code to information words is disclosed. The encoder circuitry takes advantage of a macro matrix arrangement of the LDPC parity check matrix in which the parity portion of the parity check matrix is arranged as a macro matrix in which all block columns but one define a recursion path. The parity check matrix is factored so that the last block column of the parity portion includes an invertible cyclic matrix as its entry in a selected block row, with all other parity portion columns in that selected block row being zero-valued, thus permitting solution of the parity bits for that block column from the information portion of the parity check matrix and the information word to be encoded. Solution of the other parity bits can then be readily performed, from the original (non-factored) parity portion of the parity check matrix, following the recursion path.

Abstract: An apparatus and method for coding a block Low Density Parity Check (LDPC) code having a variable coding rate. The apparatus receives an information word and encodes the information word into a block LDPC code based on one of a first parity check matrix and a second parity check matrix, depending on a coding rate to be applied when generating the information word into the block LDPC code.

Abstract: A method and apparatus for transmitting and receiving data provide for efficient use communication resources by encoding data in accordance with a first code to produce a block of data, determining transmission data rate of a time frame, selecting a portion of the block of data based on the determined transmission data rate, adding a location identifier data to the portion of data to produce a payload data, wherein the location identifier identifies a location of the portion of data within the block of data, and encoding the payload data in accordance with a second code to produce a packet of data for transmission over the time frame. A transmitter transmits the packet of data over the time frame at the determined data rate. A receiver receives the packet of data over the time frame, and processes the received data accordingly to reproduce the block of data.

Abstract: A software implementation of a Reed-Solomon decoder placing a constant load on the processor of a computer. A Berlekamp-Massey Algorithm is used to calculate the coefficients of the error locator polynomial, a Chien Search is used to determine the roots of the error locator polynomial, and a Forney Algorithm is used to determine the magnitude of the errors in the received digital code word. Each step is divided into m small tasks where m is the number of computational blocks it takes to read in a code word and the processor can pipeline or parallel process one task from each step each time a block is read.

Abstract: A method of decoding possibly mutilated codewords (r) of a code (C) into information words (m?) including information symbols (m?1, m?2, . . . , m?k), the information words (m) being encoded into codewords (c) of the code (C). In order not to considerably deviate from the standard method and apparatus for decoding a standard Reed-Solomon code, a method of decoding is proposed including decoding the possibly mutilated codewords (r) into codewords (r?), reconstructing information symbols (m?1, m?2, . . . , m?k) from the codewords (r?), comparing the reconstruct information symbols (m?1, m?2, . . . , m?k) with information symbols (m1) known a priori before decoding, and verifying decoding errors based on the result of the comparison.

Abstract: An error-correcting method used for decoding of data transmissions is disclosed. The error-correcting method is used for data with an error-correcting part and comprises: providing a multinomial for processing an error-correcting part to get an operational result; providing a database for saving the corresponding operational results of each single bit; and finding the error bit according to the operational results.

Abstract: A method and apparatus for encoding and decoding Reed-Muller codes are provided. In exemplary embodiments, a method comprises receiving a code-word encoded with a Reed-Muller code, generating a pattern to retrieve voting bits, decoding the code-word based on the voting bits and, and providing the decoded code-word.

Abstract: A sub-optimal method is disclosed for calculating the reliability values (soft values) for the bits of a multilevel signal. The log-likelihood values are approximated using only the dominant terms, so called max-log approximation, that is for each bit position only the two closest signal symbols of opposite bit value (S8, S6) are considered in the sum. The used modulation scheme is 16-QAM together with Gray-labelling. Two versions of approximation are proposed: one version consists of using the two distances between the received value and the two closest symbols of opposite bit value (?1 ?2 ). In order to simplify and speed up the calculation, the second version consists of using the distance between the two closest symbols (?3 ) to approximate the distance between the second closest symbol and the received value. Furthermore, precalculated results are stored in look-up tables to speed up the calculation.

Abstract: A technique of determining a message residue includes accessing a message and simultaneously determining a set of modular remainders with respect to a polynomial for different respective segments of the message. The technique also includes determining a modular remainder with respect to the polynomial for the message based on the set of modular remainders and a set of constants determined prior to accessing the message. The modular remainder with respect to the polynomial for the message is stored in a memory.

Abstract: The invention relates to an encoding method for encoding a codeword to obtain a parity code. The code is embedded in the codeword and divides the codeword to have intermediate symbol locations between a first and a second set of data symbols. Each data symbol forms a coefficient. The first and the second set of data symbols and the parity code respectively form a first polynomial (M1(x)), a second polynomial (M2(x)), and a parity code polynomial (R(x)).

Abstract: One or more methods and systems of effectively retrieving data stored in a media of a storage device are presented. The one or more methods and systems are implemented by way of correcting and detecting errors using a multi-stage decoding process. In one embodiment, the storage device comprises a magnetic hard drive. In one embodiment, the system and method applies an encoding/decoding technique that allows error correction and detection to be performed over a number of successive decode stages or processing stages. Use of the system and method increases the maximum number of symbol errors that may be corrected in an encoded codeword, providing an improvement in data recovery.

Abstract: A data dependent scrambler for a communications channel that receives a user data sequence including X bits that are organized as N M-bit symbols includes a seed finder that generates a scrambling seed that is dependent upon the symbols in the user data sequence. A first scrambler receives the user data sequence from the data buffer and the scrambling seed from the seed finder and generates the scrambled user data sequence. An H-code finder generates at least one of an H-code token that is dependent upon the symbols in the user data sequence and an offset of the H-code token from the scrambling seed. An H-code encoder receives the scrambled user data sequence and at least one of the H-code token and the offset. The H-code encoder increases a Hamming weight of the scrambled user data sequence using the at least one of the H-code token and the offset.

Abstract: A cyclic code is generated by a circuit including a group of logic gates that generate one multiple-bit code segment from another multiple-bit code segment. The logic gates receive B initial bits, where B is the degree of the generator polynomial, and generate one complete (2B?1)-bit code cycle, from which a clocked address generator and a barrel shifter select successive C-bit segments for output (C>1). This arrangement outputs C bits of code per clock pulse and therefore does not require a special high-frequency clock signal.

Abstract: Systems and methods are provided for performing error correction decoding. The coefficients of the error locator polynomial are iteratively determined for each codeword using a modular implementation of a single recursion key-equation solver algorithm. According to this implementation, a plurality of modules are used to calculate the current and previous coefficients of the error locator polynomial. One module is used for each correctable error. The modular single recursion implementation is programmable, because the number of modules can be easily changed to correct any number of correctable errors. Galois field tower arithmetic can be used to calculate the inverse of an error term. Galois field tower arithmetic greatly reduces the size of the inversion unit. The latency time can be reduced by placing the computations of the inverse error term outside the critical path of the error locator polynomial algorithm.

Abstract: Methods and structures are described for processing signals formatted according to a plurality of different wireless and broadband standards. In some embodiments, network resources are shared to enable energy efficient, pseudo-simultaneous processing. In some embodiments, a timestamp is prepended to input data to remove jitter associated with time division multiplexed processing using shared resources. Systems according to embodiments of the invention are also disclosed.

Abstract: The present invention concerns channel codes particularly well adapted to transmission in channels in which errors tend to occur in bursts. Moreover, the codes according to one embodiment of the invention using an algebraic geometric curve are easy to decode and have a relatively high minimum distance. The invention also relates to the corresponding encoding and decoding methods, as well as the devices and apparatuses adapted to implement those methods. Application is in particular to mass storage, and to systems of communication by OFDM.

Abstract: A syndrome evaluation with partitioning of a received block of symbols into subsets and interleaved partial syndrome evaluations to overcome multiplier latency. Parallel syndrome evaluations with a parallel multiplier.

Abstract: A method of generating a CRC for a composite sub-message based on a CRC generating polynomial having at least two factors. The composite sub-message includes sub-message data and a number, n, of trailing zeros. The method includes generating a first remainder based on the sub-message data and a first factor of the CRC generating polynomial. A second remainder is generated based on the sub-message data and a second factor of the CRC generating polynomial. The CRC for the composite sub-message is generated based on adjusted versions of the first and the second remainders.

Abstract: A method for segmenting an information word into code blocks in a mobile communication system. The method includes setting a number C of code blocks to a minimum integer not less than a value obtained by dividing X by Z; when sizes K of all code blocks are determined to be equal when a length X of the information word is greater than a maximum length Z of each code block, determining a minimum integer value T not less than a value obtained by dividing a size of the information word by a number of code blocks, and determining, as K, a maximum value most approaching the value T among the values based on which a size of the code block can be set in units of eight bits; and generating a code block by inserting filler bits into a specific code block when a value obtained by multiplying K by C is greater than X.

Abstract: A system 100 for protecting a codeword u against an error in at least one <7-ary symbol, where q is an r? of two, r?1 (q=T). The code word u 300 includes information symbols 310 u[0], . . . , u[k?1], k>1, each information symbol representing an integer in the range {?, 2w?1}, where w=n*r, n?1. A processor 130 includes an integer processing unit 140 for, under control of a program, calculating a parity symbol 312 u[k] for protecting the information symbols, where the parity symbol includes ?(?[0]<<u[0]+?[1]<<u[1]+ . . . +a[k?1]*u[k?1]) mod M, where the multiplication · and the addition + are integer operations. The constants ?[0], . . . , ?[£?1] lie in {0, . . . , M?1}, M?1 and are chosen such that the elements a[i]*d*qJ modM are unique for ie {0, . . . , k?1}, j e {0, . . . , n?1}, ?q<d<q, d?0.

Abstract: An OC-192 front-end application-specific integrated circuit (ASIC) de-interleaves an OC-192 signal to create four OC-48 signals, and decodes error-correction codes embedded in each of the four OC-48 signals. The decoder generates a Bose-Chaudhuri-Hocquenghem (BCH) error polynomial in no more than 12 clock cycles. The decoder includes several Galois field multiply accumulators, and a state machine which controls the Galois field units. If the error-correction code is a BCH triple error-correcting code, four Galois field units are used to carry out only six equations to solve the error polynomial. The Galois field units are advantageously designed to complete a Galois field multiply/accumulate operation in a single clock cycle. The Galois field units may operate in multiply or addition pass-through modes.

Abstract: A Low Density Parity Check (LDPC) code encoding apparatus for a communication system is provided. The encoding apparatus receives information bits, and generates an LDPC code by encoding the information bits using an interleaving scheme. The interleaving scheme is generated such that when the LDPC code is punctured, there is no short-length cycle in a Tanner graph of the punctured LDPC code.

Abstract: Techniques are disclosed for modeling a cell of an integrated circuit design. In one aspect of the invention, a full-space polynomial model is fit to cell information comprising measured data points associated with one or more independent variables such as voltage slew, capacitive load, supply voltage or temperature. Error values are generated indicative of error between the measured data points and the full-space polynomial model. The error values are used to partition the modeling space into domains. For at least a given one of the domains, a first polynomial model is generated based on a subset of the measured data points and at least one additional data point determined by interpolation from the measured data points in the subset. Error values are generated indicative of error between the measured data points of the subset and the first polynomial model.

Abstract: A multi-bit acknowledgement word (44) is prepared by a first communications station 22 (such as a base station) for separately acknowledging the success or failure of data packets received over plural communication channels (42) from respective plural second communication stations 28 (such as terminals). The acknowledgement word (44) is a “joint” or “common” acknowledgement word in the sense that one and the same acknowledgement word provides acknowledgement information for data packets received from plural second communication stations. Either separately or in conjunction with the joint acknowledgement word, a terminal checking code (62) can be employed for determining whether a packet is received on a both in a correct channel and from a correct terminal. The terminal checking code (62) comprise a cyclic redundancy check code formed over data bits (66) of the data packet and a terminal identifier (68) of the terminal (28).

Abstract: In this parity data generating circuit, a Galois field multiplying calculation is realized by performing data conversion by index table information generated from a Galois field multiplying table so that data for RAID6 are generated. A table check circuit inspects nonconformity of the index table information in advance by using results in which the Galois field multiplying table is indexed from different directions constructed by the longitudinal direction and the transversal direction. Data and parity for making the multiplying calculation are decomposed into plural data and parities by using this table check circuit, and index table information different from each other are allocated to these data and parities. Thus, a longitudinal index table making circuit and a transversal index table making circuit themselves are checked.

Abstract: A system and method for preventing user-input text strings of illegal lengths from being submitted to a database where, for each character in the string, a character length is determined in quantities of digital units of storage according to an encoding schema, the character lengths are accumulated into a total string length, also measured in digital units of storage, and the total string length is compared to one or more database input field requirements such as non-null and maximum length specifications. If a limit is not met, the system and method are suitable disposed in a manner to block or prevent submission of the user-input string to the database. The invention can alternatively be realized as a plug-in for database front-end application programs, as a stand-alone web services provider, or as a plug-in for a client-side database access program such as a web browser.

Abstract: One or more methods and systems of effectively retrieving data stored in a media of a storage device are presented. The one or more methods and systems are implemented by way of correcting and detecting errors using a multi-stage decoding process. In one embodiment, the storage device comprises a magnetic hard drive. In one embodiment, the system and method applies an encoding/decoding technique that allows error correction and detection to be performed over a number of successive decode stages or processing stages. Use of the system and method increases the maximum number of symbol errors that may be corrected in an encoded codeword, providing an improvement in data recovery.

Abstract: A Cyclic Redundancy Check (CRC) system comprises N+1 shift registers. N+1 logic gates having first inputs communicate with outputs of corresponding ones of said N+1 shift registers. N+1 programmable registers store a corresponding CRC coefficient of a 3rd to Nth order CRC polynomial key word, wherein N is an integer greater than two. N+1 multiplexers communicate with outputs of corresponding ones of said N+1 logic gates. At least N of said N+1 multiplexers communicate with corresponding ones of at least N of said N+1 programmable registers.

Abstract: A method, an apparatus and a carrier medium storing instructions to implement the method. The method is in a first wireless station of a wireless network, and includes wirelessly receiving a signal corresponding to a packet wirelessly transmitted by a second wireless station. The packet includes a subpacket and a check sequence. The method further includes verifying the integrity of the subpacket, the verifying at least using the check sequence. The method further includes, in the case that the subpacket fails the verifying, reducing the power consumption of at least one component in the first wireless station for a time interval.

Abstract: The present invention relates to a module 50 for generating integrated decoding circuits for use, in particular, in turbo devices, to the method for defining the characteristics of and generating convolutional decoding circuits, and to the circuit that can be obtained with said module 50. The module 50 is parametric and, thanks to this feature, makes it possible to generate decoding circuits having different performance characteristics which are such that they can be used in turbo devices employing different decoding modes and different architectures. In addition, the module 50 makes it possible to generate decoding circuits whose distinguishing feature is that they can manage a plurality of generator polynomials selectively and can thus also be used in asymmetrical turbo devices.

Abstract: A method of encoding a binary source message u, by calculating x:=Au, calculating y:=B?x, resolving the equation Dp=y for p, and incorporating u and p to produce an encoded binary message v, where A is a matrix formed only of permutation sub matrices, B? is a matrix formed only of circulant permutation sub matrices, and D is a matrix of the form D = ( T 0 ? 0 0 0 T ? 0 0 ? ? ? ? ? 0 0 ? T 0 I I ? I I ) where T is a two-diagonal, circulant sub matrix, and I is an identity sub matrix.

Abstract: The present invention concerns an encoding method in which encoding is performed of any information word a of length k in the form of a word ? belonging to a Reed-Solomon code C of dimension k? and length n? (with n??k?=n?k) such that the components of ?? situated in (n??n) arbitrary predetermined positions be systematically equal to respective predetermined constants (for example, all zero). The possibility then exists of deleting those components of fixed value to obtain a word ? of length n belonging to a code C, which thus constitutes a code that is shortened with respect to code C. The invention also relates to devices and apparatuses adapted to implement the encoding method. The invention may be used for encoding by means of an algebraic geometric code, when such encoding may be implemented by encoding by means of a plurality of shortened Reed-Solomon codes.