Abstract: An apparatus and a method of processing cyclic codes are disclosed herein, where the apparatus includes at least one reconfigurable module and an encoder controller. The reconfigurable module includes a plurality of linear feedback shift registers. The encoder controller can control the reconfigurable module to factor a generator polynomial into a factorial polynomial. In the reconfigurable module, the linear feedback shift registers can register a plurality of factors of the factorial polynomial respectively.

Abstract: Systems and methods for signal analysis are described. The method can include digitizing a signal modulated by a pseudo noise (PN) sequence, dividing the digitized signal into a plurality of sample blocks, and estimating a PN phase embedded in a sample block of the plurality of sample blocks using an iterative message passing algorithm (iMPA) executed on a redundant graphical model.

Abstract: This disclosure relates to method, device and system for detecting errors in a communication system. A signal is received from a transmitter at a receiver wherein the signal includes a data portion and a result of a hash function. The hash function is computed in part from a transmitter identification code. The receiver determines if the result of the hash function matches both the data portion and the transmitter identification code. The receiver discards the signal if the result of the hash function does not match both the data portion and the transmitter identification code of the transmitter.

Abstract: System and method for designing Slepian-Wolf codes by channel code partitioning. A generator matrix is partitioned to generate a plurality of sub-matrices corresponding respectively to a plurality of correlated data sources. The partitioning is performed in accordance with a rate allocation among the plurality of correlated data sources. A corresponding plurality of parity matrices are generated based respectively on the sub-matrices, where each parity matrix is useable to encode data from a respective one of the correlated data sources.

Abstract: A data writing method for flash memory and an error correction encoding/decoding method thereof are disclosed. In an embodiment of the data writing method, a 6-bit ECC scheme using a Reed-Solomon code derived from a Galois Field GF (29) is used to encode a data for generating a redundant which requires smaller storing space. In an embodiment of the error correction encoding/decoding method, an erase checking value corresponding to the status where all the bytes of data area and parameter storing area are “0xff” is provided to improve the security of stored data.

Abstract: A method includes receiving payload data from a data source at error correction code (ECC) logic, where the ECC logic is adapted to process a block of data of a particular size via a plurality of stages. The ECC logic is initialized to a selected stage of the plurality of stages. The selected stage includes an initial value and an initial number of cycles. The initial value and the initial number of cycles are related to a number of symbols of padding data corresponding to a difference in size between the payload data and the block of data. The selected stage is related to a state of the ECC logic as if the number of symbols of padding data had already been processed by the ECC logic. The payload data is processed via the ECC logic beginning with the selected stage to produce parity data related to the payload data.

Abstract: Methods and apparatus for creating codewords of n-valued symbols with one or more n-valued check symbols are disclosed. Associating the codewords with a matrix allows for detection of one or more symbols in error and the location of such symbols in error. Methods to reconstruct symbols in error from other symbols not in error are also disclosed. Systems for using the methods of error detection and error correction by symbol reconstruction are also disclosed. Using two or more matrices to determine check symbols is also provided.

Abstract: In one aspect, circuitry to determine a modular remainder with respect to a polynomial of a message comprised of a series of segment. In another aspect, circuitry to access at least a portion of a first number having a first endian format, determine a second number based on a bit reflection and shift of a third number having an endian format opposite to that of the first endian format, and perform a polynomial multiplication of the first number and the at least a portion of the first number.

Abstract: Error detection and error location determination circuitry is provided for detecting and locating soft errors in random-access-memory arrays on programmable integrated circuits. The random-access-memory arrays contain rows and columns of random-access-memory cells. Some of the cells are loaded with configuration data and produce static output signals that are used to program associated regions of programmable logic. Cyclic redundancy check error correction check bits are computed for each column of each array. The error correction check bits are stored in corresponding columns of cells in the array. During normal operation of an integrated circuit in a system, the cells are subject to soft errors caused by background radiation strikes. The error detection and error location determination circuitry contains linear feedback shift register circuitry that processes columns of array data. The circuitry continuously processes the data to identify the row and column location of each error.

Abstract: A method is disclosed of determining a coordinate value of a position on a printed document having patterns printed thereon. Each pattern represents a sequence having a repeating codeword of a cyclic position code. The method includes sensing the patterns printed on the document, obtaining from each sensed pattern a sub-sequence, mapping each of the sub-sequences to a respective mapped codeword of the cyclic position code, and determining an offset indicative of the position, in the corresponding sequence, between each mapped codeword and the codeword. Also included are the steps of deriving, for each pair of the sequences, a difference between the corresponding pair of offsets, as well as deriving the coordinate value by interpreting the differences as a digit of the coordinate value, and by interpreting the differences as a marker separating the coordinate value from an adjacent coordinate value.

Abstract: A data dependent scrambler for a communications channel that receives a user data sequence including N symbols and host cyclic redundancy check (CRCU) bits comprises a data buffer that receives the user data sequence and the host CRCU bits. A seed finder generates a scrambling seed that is dependent upon the symbols in the user data sequence. A first scrambler receives the user data sequence from the data buffer and the scrambling seed from the seed finder and generates the scrambled user data sequence. A second scrambler generates a difference sequence that is based on the user data sequence and the scrambled user data sequence.

Abstract: Systems and methods correct multiplied errors generated by feedback taps in self-synchronous descramblers. The multiplication of errors degrades the performance of most linear cyclic error check codes. Disclosed techniques are general applicable to multiplied errors even when those errors are not confined to a single block. Disclosed techniques permit a reduction in the amount of forward error correction used. For example, in general, to correct t errors, a linear cyclic error correction code requires a Hamming distance of at least 1+(2t)[wt(s(x))]. Embodiments of the invention allow correcting the multiplied errors with a Hamming distance of only 1+(t)(1+wt(s(x))) over the block size n, wherein wt(s(x)) is the weight of the scrambler polynomial s(x).

Abstract: In various embodiments, methods and systems are disclosed for integrating a remote presentation protocol with a datagram based transport. In one embodiment, an integrated protocol is configured to support lossless or reduced loss transport based on Retransmission (ARQ) combined with Forward Error Correction (FEC). The protocol involves encoding and decoding of data packets including feedback headers and FEC packets, continuous measurement of RTT, RTO and packet delay, dynamically evaluating loss probability to determine and adjust the ratio of FEC, congestion management based on dynamically detecting increase in packet delay, and fast data transmission rate ramp-up based on detecting a decrease in packet delay.

Abstract: A method, a codebook, and a Base Station (BS) for precoding are provided. The precoding method includes: obtaining a total uplink power of a User Equipment (UE); if the total uplink power is greater than ¾ of a rated total transmit power of antennas, selecting a codeword from a first codebook with imbalanced power between layers; otherwise, selecting a codeword from the first codebook and a second codebook with balanced power between layers, so as for precoding data to be transmitted according to the selected codeword. Thus, a loss of an antenna performance at a high signal-to-noise ratio is reduced, and the loss of the power amplification of the antenna is reduced if the transmit power of the antenna is restricted.

Abstract: The present invention provides a data storage device comprising a disk storage medium containing user data in a plurality of sectors, a head for writing or reading the user data and error correcting means for correcting an error that occurs in the user data during the reading process. The error correcting means comprises a syndrome generator for generating syndromes on the basis of the user data contained in predetermined sectors, registers for storing the syndromes generated and an exclusive OR circuit for exclusive ORing the values stored in the registers.

Abstract: The present invention provides a data storage device comprising a disk storage medium containing user data in a plurality of sectors, a head for writing or reading the user data and error correcting means for correcting an error that occurs in the user data during the reading process. The error correcting means comprises a syndrome generator for generating syndromes on the basis of the user data contained in predetermined sectors, registers for storing the syndromes generated and an exclusive OR circuit for exclusive ORing the values stored in the registers.

Abstract: Methods and apparatus to provide a pipelined cyclic redundancy check (CRC) are described. In one embodiment, a plurality of stages determines a plurality of CRC values corresponding to portions of a data packet. The plurality of CRC values are accumulated to determine a CRC value for the data packet. Other embodiments are also described.

Abstract: An apparatus and method for encoding/decoding a non-binary low density parity check (LDPC) code in a communication system. The apparatus and method includes receiving an information vector; generating a non-binary LDPC code by encoding the information vector into a non-binary LDPC code according to a non-binary LDPC encoding scheme.

Abstract: An error correction encoding apparatus wherein the apparatus structure is simple; an iterative decoding is used to achieve a decoding with a close-to-optimum precision; and a simple mathematical expression is used to perform an evaluation of the characteristic of an error floor area without using any computer experiments. In a polynomial multiplying block 1, (n?1)-th-order polynomial multiplying units (12-1 to 12-(m?1)) further divide an information bit string, which has been blocked for an error correction encoding, into (m?1) blocks having a length n and a single block having a length (n?r) (where m and n represent integers equal to or greater than two and where r represents an integer between 1 and n inclusive); receive blocks, which have the length n, of divided information bit strings; and output a series having the same length.

Abstract: The optical line terminal has a PON transceiver including an error correction code decoder. The error correction decoder includes: a shortening compensation parameter table; and a syndrome calculator for calculating a syndrome by referring to the shortening compensation parameter table, or an error search part for calculating an error position or an error value by referring to the shortening compensation parameter table. Also the optical network terminal has a PON transceiver including an error correction code decoder. The error code decoder includes: a shortening compensation parameter table; and a syndrome calculator for calculating a syndrome by referring to the shortening compensation parameter table, or an error search part for calculating an error position or an error value by referring to the shortening compensation parameter table.

Abstract: A data recording and/or reproducing apparatus and method for an information recording medium includes: an extra ECC encoder; and an extra ECC controller determining whether extra ECC is applied to the information recording medium, and controlling the extra ECC encoder to generate an extra parity data block corresponding to data that is to be recorded on the information storage medium. The extra ECC encoder includes: an extra parity generator generating an extra ECC data block based on data that is to be recorded on the information recording medium, performing ECC on the extra ECC data block, and generating at least one extra parity. An extra parity interleaver interleaves the at least one extra parity and generating the extra parity data block.

Abstract: A transmitter is capable of performing both Galois Field (GF) (16) and GF (256) encoding in a visual light communication system. The transmitter includes a GF (256) encoder. The transmitter also includes a first bit mapper configured to map a first number of bits to a second number of bits. The Galois Field (256) encoder is configured to receive and encode the second number of bits. The transmitter also includes a second bit mapper configured to map the second number of bits to the first number of bits. The transmitter also includes an interleaver unit that can pad bits based on a frame size and puncture the bits after interleaving and prior to transmission.

Abstract: Described herein are 8-bit wide data error detection and correction mechanisms that require fewer memory chips and therefore provide reduces system complexity and reduced system power consumption as compared to traditional mechanisms. This technique relies on testing a fixed set of possible solutions in order to correct the fault. This error code provides a very high error detection rate, but requires a set of error trials to correct the detected faults. The extra correction latency for infrequent errors may be acceptable given a low frequency. For repeated corrections, a log may be maintained to simplify error correction.

Abstract: A method of operating an integrated circuit which includes an input module, an output module, and a processing module coupled to the input module and the output module. The method includes, in the input module, receiving a first data segment; in the processing module, reading a hard coded identifier from an identifier module coupled to the processing module, processing the first data segment with the hard coded identifier to generate a first encoded data segment; and in the output module, transferring the first encoded data segment for storage on a storage system.

Abstract: A method and apparatus to perform Cyclic Redundancy Check (CRC) operations on a data block using a plurality of different n-bit polynomials is provided. A flexible CRC instruction performs a CRC operation using a programmable n-bit polynomial. The n-bit polynomial is provided to the CRC instruction by storing the n-bit polynomial in one of two operands.

Abstract: A Bose, Ray-Chaudhuri, Hocquenghem (BCH) decoder is employed in non-volatile memory applications for determining the number of errors and locating the errors in a page of information. The decoder includes a syndrome calculator responsive to a sector of information. The sector includes data and overhead, with the data being organized into data sections and the overhead being organized into overhead sections. The syndrome calculator generates a syndrome for each of the data sections. A root finder is coupled to receive the calculated syndrome and to generate at least two roots. A polynomial calculator responds to the two roots and generates at least two error addresses, each identifying a location in the data wherein the error lies.

Abstract: A technique for reducing parity bit-widths for check bit and syndrome generation through the use of additional check bits to increase the number of minimum weighted codes in the Hamming Code H-Matrix. The technique of the present invention may be implemented while adding no additional correction/detection capability, in order to reduce the number of data bits that are used for each check bit/syndrome generation and to reduce the width of the parity generating circuitry.

Abstract: A memory device has an error detection and correction system constructed on a Galois finite field. The error detection and correction system includes calculation circuits for calculating the finite field elements based on syndromes obtained from read data and searching error locations, the calculation circuits having common circuits, which are used in a time-sharing mode under the control of internal clocks.

Abstract: In a method and apparatus to conceal an error in an audio signal, when the current frame has no error and a past frame input prior to the current frame has an error, a parameter for the past frame is generated using a parameter for the current frame and a parameter of a frame out of frames input prior to the past frame and a previously stored parameter is updated with the generated parameter, thereby concealing an error of an audio signal without additional delay and preventing degradation in sound quality in a frame that is input after a frame having an error.

Abstract: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

Abstract: In a method of detecting an error pattern in a codeword transmitted across a noisy communication channel, a codeword is detected. A syndrome is then generated by applying a generator polynomial to the codeword. The generator polynomial is adapted to produce a distinct syndrome set for each of “L” (L>1) different error patterns potentially introduced in the codeword during transmission across the communication channel. A type of an error pattern within the codeword is detected based on the syndrome or a shifted version of the syndrome, and then a start position of the error pattern within the codeword.

Abstract: The present invention discloses a set-cyclic comparison method for an LDPC (Low-Density Parity-Check) decoder, which applies to a CNU (Check Node Unit) or a VNU (Variable Node Unit). In the systematized method of the present invention, all the input elements are initialized to obtain a matrix. Based on the symmetry of the matrix and the similarity between the rows of the matrix are sequentially formed different sets respectively corresponding to the horizontally-continuous elements having the maximum iteration number in the horizontal and vertical directions, the symmetric non-continuous non-boundary elements, and the boundary elements plus the end-around neighboring elements in the same row. The present invention applies to any input number. Via the large intersection between the compared sets, the present invention can effectively reduce the number of comparison calculations and greatly promote the performance of an LDPC decoder.

Abstract: A system for protecting a codeword u against an error in at least one <7-ary symbol, where q is an rth power of two, r>1 (q=2r). The code word u includes information symbols u[0] . . . u[k?1] , k>1 , each information symbol representing an integer in the range {0 . . . 2w?1}, where w=n*r, n?1. A processor includes an integer processing unit for, under control of a program, calculating a parity symbol u[k] for protecting the information symbols, where the parity symbol includes ?(a[0]·u[0]+a[1] ·u[1]+. . . +a[k?1]•u[k?1]) mod M, where the multiplication · and the addition + are integer operations. The constants a[0] . . . a[£?1] lie in {0 . . . M?1}, M>1 and are chosen such that the elements a[i]*d*qi mod M are unique for i?{0, . . . ,k?1}, j?{0 . . . n?1}, ?q<d<q, d?0.

Abstract: A memory device includes an error detection and correction system with an error correcting code over GF(2n) wherein the system has an operation circuit configured to execute addition/subtraction with modulo 2n?1, and wherein the operation circuit has a first operation part for performing addition/subtraction with modulo M and a second operation part for performing addition/subtraction with modulo N (where, M and N are integers which are prime with each other as being obtained by factorizing 2n?1), and wherein the first and second operation parts perform addition/subtraction in parallel to output an operation result of the addition/subtraction with modulo 2n?1.

Abstract: A decoder is disclosed that can reduce power consumption at different stages of a decoding process. At a first stage where the decoder calculates residual values, the decoder can reduce power consumption by calculating residual values using less than a full set of division circuits. A reduced number of division circuits may be sufficient to successfully calculate residuals associated with the codeword to complete the decoding process. Division circuits that are not used may be disabled to reduce power consumption. At another stage of the decoding process where the decoder generates coefficients that are used to identify locations of errors in the codeword, the decoding process can limit power consumption by reducing the number of iterations of a polynomial generator by incorporating termination decision circuitry.

Abstract: An apparatus, system and method for detecting errors in a physical interface during the transmission and/or receipt of data communications between integrated circuits (“ICs”) are disclosed. In one embodiment, an apparatus for generating error-detection codes in a physical interface for the transmission of data communications between integrated circuits (“ICs”) includes an N-bit-to-N+2-bit (“N bit/(N+2) bit”) physical layer (“PHY”) encoder configured to insert a physical interface error detection bit with N application data bits to form N+1 unencoded data bits, and encode said N+1 unencoded data bits to yield N+2 encoded data bits. The apparatus further includes an error-detection code generator configured to generate a number of bits constituting an error-detection code that includes said physical interface error detection bit, wherein N represents any integer number of data bits.

Abstract: The present discloses a method for detection and correction of errors, based on the proposition of multidimensional error correcting code, presenting the first example of implementation of MECC called BCHMD, that employ the BCH or BCH algebraic in each dimension of the set of symbols in the encoder and decoder sides of the communication system, in the error correcting code stage. Especially the described method claimed by the present invention embraces bits in different dimensions, which improves performance, speed and capacity in the ECC.

Abstract: An apparatus for improving the data access reliability of flash memory is provided, including an instruction register, an address register, a flash memory control circuit, a data register, an encoder, an error correction code (ECC) generator, a signal converter, a comparator, an arbitrator, and a decoder. The instruction register and the address register are connected to a flash memory respectively for storing the access instructions and the addresses. The flash memory control circuit is connected to both instruction register and address register for controlling the access to the flash memory. The data register is connected to flash memory control circuit for loading data to be written to the flash memory. The encoder encodes the written data, and the ECC generator generates an ECC, which is written to the flash memory through the signal converter. The comparator and the arbitrator provide the comparison with ECC and informing decoder f suspicious bit values when data is read from the flash memory.

Abstract: An encoder structure for an error correcting code with arbitrary parity positions is presented. The invention is effective for all error correcting codes whose parity check matrix is of the Vandermonde type. In contrast to conventional encoder circuits, the parity symbols produced by this encoder are not restricted to form a block of consecutive parity symbols at the beginning or at the end of a codeword, but may be spread arbitrarily within the codeword. A general structure of the parity check matrix for such a code is found by exploiting the special Vandermonde structure of matrices. From this general parity check matrix, an expression for the evaluation of the parity symbols in terms of a polynomial with limited degree is derived. An efficient hardware implementation of the proposed encoder is suggested.

Abstract: Systems and methods correct multiplied errors generated by feedback taps in self-synchronous descramblers. The multiplication of errors degrades the performance of most linear cyclic error check codes. Disclosed techniques are general applicable to multiplied errors even when those errors are not confined to a single block. Disclosed techniques permit a reduction in the amount of forward error correction used. For example, in general, to correct t errors, a linear cyclic error correction code requires a Hamming distance of at least 1+(2t)[wt(s(x))]. Embodiments of the invention allow correcting the multiplied errors with a Hamming distance of only 1+(t)(1+wt(s(x))) over the block size n, wherein wt(s(x)) is the weight of the scrambler polynomial s(x).

Abstract: An integrated circuit communications interface operable consistent with multiple data transmission protocols includes error detection circuitry that implements a cyclic redundancy check (i.e., CRC) function. The error detection circuitry generates a checksum based, at least in part, on a selected one of the multiple data transmission protocols. The error detection circuitry includes at least one circuit that generates a digital code according to an operation including terms common to the multiple data transmission protocols. That digital code is combined with a selected digital code to generate the CRC. The selected digital code is generated by an individual circuit corresponding to a respective one of the multiple data transmission protocols. The individual circuit generates the selected digital code according to an operation including at least terms exclusive to the respective one of the multiple data transmission protocols.

Abstract: A method of encoding a binary source message u, by calculating x:=Au, calculating y:=B?x, resolving the equation Dp=y for p, and incorporating u and p to produce an encoded binary message v, where A is a matrix formed only of permutation sub matrices, B? is a matrix formed only of circulant permutation sub matrices, and D is a matrix of the form D = ( T 0 … 0 0 0 T … 0 0 … … … … … 0 0 … T 0 I I … I I ) where T is a two-diagonal, circulant sub matrix, and I is an identity sub matrix.

Abstract: A semiconductor device comprising processing logic. The processing logic is arranged to configure interleaver logic to re-order data symbols of a data stream according to a quadrature permutation polynomial function. The processing logic is further arranged to: divide a cyclic group of values defined by the QPP function into a set of subgroups, the set of subgroups being capable of being defined by a set of linear functions; derive inverse functions for the set of linear functions defining the subgroups; and configure the interleaver logic to load the data symbols of the data stream into a buffer at locations within the buffer corresponding to a cyclic group of values representative of the inverse function for the QPP function based on the inverse functions of the set of linear functions defining the subgroups.

Abstract: A method of constructing an effective generator polynomial for error correction by which a unique set of syndromes for each error event is produced is provided. The method includes preparing a set of dominant error events from the intersymbol interference characteristics of media; and generating a codeword from the data using a non-primitive generator polynomial that produces a unique syndrome set which completely specifies each dominant error event.

Abstract: Techniques for validating the integrity of a data communications link are provided. By executing error correction/detection calculations, such as CRC calculations, in a pipelined manner, logic may be distributed over multiple machine cycles. As a result, delay involved in the logic for each cycle may be reduced, allowing calculations in systems with higher clock frequencies.

Abstract: A determination of indexes allocated to error correcting symbols is provided. Encoded code symbols are generated by means of a generator matrix of a block code from number of source symbols and the encoded transmission errors occur in the received code symbols, the indexes of the error correcting symbols are determined by unambiguously identifying the area of the encoded code symbols by means of first and second parameters, which can be requested in the form of at least one error correcting symbol by the receiving device from the transmitting device for reconstructing the source symbols in an error-free manner.

Abstract: A method and an apparatus for checking a pipelined parallel cyclic redundancy is disclosed. In accordance with the method and the apparatus of the present invention, after an entire CRC (cyclic redundancy check) logic is divided into a feedback portion and an input data portion, the input data portion is divided using a pipelined structure such that the input data portion is designed to have the pipelined structure based on an algorithm that maintains a logic level of each stage to be lower than that of the feedback portion and an algorithm that optimizes a size of a register inserted during the division to improve a speed thereof and to detect an error of a received data in a high speed data communication apparatus.

Abstract: A computer-implemented method for correcting transmission errors. According to the method, a transmitted vector corrupted by error can be recovered solving a linear program. The method has applications in the transmission of Internet media, Internet telephony, and speech transmission. In addition, error correction is embedded as a key building block in numerous algorithms, and data-structures, where corruption is possible; corruption of digital data stored on a hard-drive, CD, DVD or similar media is a good example. In short, progress in error correction has potential to impact several storage and communication systems.

Abstract: One embodiment of the present includes a electronic data storage card having a Reed Solomon (RS) decoder having a syndrome calculator block responsive to a page of information, the page being organized into a plurality of data sections and the overhead being organized into a plurality of overhead sections. The syndrome calculator generates a syndrome for each of the data sections. The decoder further includes a root finder block responsive to the calculated syndrome and for generating at least two roots, a polynomial calculator block responsive to the at least two roots and operative to generate at least one error address, identifying a location in the data wherein the error lies, and an error symbol values calculator block coupled to the root finder and the polynomial calculator block and for generating a second error address, identifying a second location in the data wherein the error(s) lie.

Abstract: A description of techniques of determining a modular remainder with respect to a polynomial of a message comprised of a series of segments. An implementation can include repeatedly accessing a strict subset of the segments and transforming the strict subset of segments to into a smaller set of segments that are equivalent to the strict subset of the segments with respect to the modular remainder. The implementation can also include determining the modular remainder based on a set of segments output by the repeatedly accessing and transforming and storing the determined modular remainder.