Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.

Abstract: A semiconductor integrated circuit includes a first transmission circuit generating and outputting a first transmission signal reflecting a first data signal supplied from outside, a first reception circuit reproducing the first data signal based on a first reception signal, a first isolation element isolating the first transmission circuit from the first reception circuit and transmitting the first transmission signal as the first reception signal, a second transmission circuit generating and outputting a second transmission signal reflecting a second data signal supplied from outside, a second reception circuit reproducing the second data signal based on a second reception signal, a second isolation element isolating the second transmission circuit from the second reception circuit and transmitting the second transmission signal as the second reception signal, and a third transmission circuit generating and outputting a third transmission signal reflecting the second data signal.

Abstract: A semiconductor memory apparatus including a test circuit configured for generating compressed data by comparing and compressing data stored in a plurality of memory cells inside a memory bank during a first test mode, and configured for outputting the compressed data as test data to an input/output pad through one selected global line during the first test mode, and the test circuit is configured for transmitting the compressed data to a plurality of global lines during a second test mode, combining the compressed data loaded in the respective global lines during the second test mode, and outputting the combination result as the test data to the input/output pad during the second test mode.

Abstract: An apparatus and a method for digital-analog conversion are provided. The apparatus includes a first cell matrix for outputting a current of a signal corresponding to a number of Most Significant Bits (MSBs) of an input digital signal, a second cell matrix for outputting a current of a signal corresponding to a number of Least Significant Bits (LSBs) of the input digital signal, an amplifier for amplifying the output current of the second cell matrix at a preset amplification, and an adder for adding the output current of the first cell matrix and the output current of the amplifier.

Abstract: To produce a memory which resists ion or photon attack, a memory structure is chosen whose memory point behaves asymmetrically with regard to these attacks. It is shown that in this case, it is sufficient to have a reference cell for an identical and periodic storage structure in order to be able to correct all the memory cells assailed by an attack. An error correction efficiency of ½ is thus obtained, with a simple redundancy, whereas the conventional methods make provision, for the same result, to triple the storage, to obtain a less beneficial efficiency of ?.

Abstract: A receiver path including first, second, third, and fourth comparator modules. The first comparator module is configured to generate, based on a signal received via the receiver path, a first digital output signal indicative of a sum of first data in the received signal and a first error. The second comparator module is configured to generate, based on the signal received via the receiver path, a second digital output signal indicative of a sum of second data in the received signal and a second error. The third comparator module is configured to generate, based on the signal received via the receiver path, a third digital output signal indicative of the first data in the received signal. The fourth comparator module is configured to generate, based on the signal received via the receiver path, a fourth digital output signal indicative of the second data in the received signal.

Abstract: An information management apparatus for managing data includes a rewritable nonvolatile memory, and a memory controller configured to control inputting information into and outputting information from the nonvolatile memory. The memory controller overwrites a data, which includes a first validity check information, a first data body, a second validity check information, a second data body having the same data as the first data body and a third validity check information arranged in this order, in a designated address area in the nonvolatile memory when the memory controller performs a writing control in which the memory controller writes data in the nonvolatile memory.

Abstract: One embodiment comprises a network that includes a plurality of bi-directional links and a plurality of nodes. Each node is communicatively coupled to two neighbor nodes and to two skip nodes using the plurality of bi-directional links. Three neighboring nodes of the plurality of nodes form a triple modular redundant (TMR) set having a first end node, a second end node, and a center node, the first end node configured to transmit output data in a first direction and the second end node configured to transmit output data in a second direction.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for detecting a sync mark with a ratio-adjustable detection system.

Abstract: In particular embodiments, a method includes receiving from a remote system a binary decision diagram (BDD) representing data streams from sensors, an input, and a first hash code, transforming the received BDD to a second arithmetic function by performing the arithmetic transformation on the received BDD, calculating a second hash code from the second arithmetic function and the input, and if the first hash code equals the second hash code, then indicating that the received BDD is uncorrupted data, else indicating that the received BDD is corrupted data.

Abstract: A fault analyzing circuit has: a comparing circuit to compare fault data stored in a storage area with a fault being caused with data of an alternation register; and a position identifying circuit to identify an error bit position from data of a comparative result of the comparing circuit.

Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

Abstract: The present invention provides for applying a cyclic redundancy check (CRC) to a data signal. The present invention includes attaching a first CRC to a first data signal block having a first length, segmenting the first data signal block attached with the first CRC into a plurality of second data signal blocks having a length shorter than the first length, respectively generating a second CRC for each second data signal block, and attaching the generated second CRC to the respective second data signal block. Moreover, the first CRC and second CRC may be generated from respectively different CRC generating polynomial equations.

Abstract: There is provided a trace/failure observation system which is capable of comprehensive collection of information that is needed for checking a desired operation in a system or the like where the amount of information to be observed is large, and which allows easy analysis of the desired operation. The system includes, in a system LSI to be subjected to trace/failure observation: an event detecting means for observing behavior of a portion to be observed; a first data reducing means for performing observation data reduction processing so that observation data from the event detecting means has an amount of information processable to a second data reducing means; and the second data reducing means for performing one or more steps of observation data reduction processing.

Abstract: A circuit includes a first one-time programmable (OTP) element and a second OTP element. The circuit also includes error detection circuitry coupled to receive a first representation of data from the first OTP element. The circuit further includes output circuitry responsive to an output of the error detection circuitry to output an OTP read result based on the first representation of the data or based on a second representation of the data from the second OTP element.

Abstract: One-time programmable integrated circuit security is described. An example of a method of protecting memory assets in an integrated circuit includes sampling values of multiple OTP memory arrays and comparing the sampled value of each OTP memory array with the sampled value of each other OTP memory array and with an unprogrammed OTP memory array value. The method further includes determining if an integrated circuit performance fault has occurred based on the compared sampled values, booting the integrated circuit, and operating the integrated circuit with access to memory determined by the fault occurrence determination.

Abstract: A check engine includes a plurality of comparators each including a first directional characteristic aligned to store at least one reference bit included in a set of reference bits, and a second directional characteristic aligned to present at least one target bit included in a set of target bits. Each of the plurality of comparators is configured to produce an output representing a level of matching between the at least one target bit and the at least one reference bit, based on a relative alignment between the first directional characteristic and the second directional characteristic. The check engine is configured such that the outputs of the plurality of comparators are combined to produce a combined output. The check engine is configured to determine that the set of target bits matches the set of reference bits based on the combined output of the plurality of comparators.

Abstract: Technology for testing a target recognition, analysis, and tracking system is provided. A searchable repository of recorded and synthesized depth clips and associated ground truth tracking data is provided. Data in the repository is used by one or more processing devices each including at least one instance of a target recognition, analysis, and tracking pipeline to analyze performance of the tracking pipeline. An analysis engine provides at least a subset of the searchable set responsive to a request to test the pipeline and receives tracking data output from the pipeline on the at least subset of the searchable set. A report generator outputs an analysis of the tracking data relative to the ground truth in the at least subset to provide an output of the error relative to the ground truth.

Abstract: An embodiment of a method of operating a memory device includes reading data from a memory array into a data buffer, checking the data using a first checker, checking the data using a second checker, and when an error is detected by the first checker and the error is not detected by the second checker returning the data to the memory array from the data buffer.

Abstract: The invention provides a nonvolatile memory controller. In one embodiment, the nonvolatile memory controller receives new data for writing a nonvolatile memory from a host, and comprises a signature calculating circuit, a signature buffer, a signature comparison circuit, a data comparison circuit, and a nonvolatile memory interface circuit. The signature calculating circuit calculates a first signature according to the new data. The signature buffer outputs a second signature corresponding to old data stored in the nonvolatile memory, wherein the old data has the same logical address as that of the new data. The signature comparison circuit determines whether the first signature is identical to the second signature. The nonvolatile memory interface circuit writes the new data to the nonvolatile memory when the first signature is determined to be different from the second signature by the signature comparison circuit.

Abstract: Methods, systems, and computer program products are provided for hardware enforced data protection mechanisms to protect software data structures. Software data structures can be protected against malicious software or software code errors that may result in data/buffer overruns or failures in computing systems. Software data structures are identified that need to be validated before they are used by software programs. A hardware mechanism receives instructions from various security privilege levels and validates an entire software data structure before the software data structure is used by software programs. Being able to detect whether a software data structure is corrupted improves defenses and security against malicious or erroneous code, provides a method for early identification, isolation, ease of debugging of software, and protects overall system integrity in computer systems and applications thereof.

Abstract: Memory systems, systems and methods are described that may include a plurality of stacked memory device dice and a logic die connected to each other by through silicon vias. One such logic die includes an error code generator that generates error checking codes corresponding to write data. The error checking codes are stored in the memory device dice and are subsequently compared to error checking codes generated from data subsequently read from the memory device dice. In the event the codes do not match, an error signal can be generated. The logic die may contain a controller that records the address from which the data was read. The controller or memory access device may redirect accesses to the memory device dice at the recorded addresses. The controller can also examine addresses or data resulting in the error signals being generated to identify faults in the through silicon vias.

Abstract: A system is provided for generating data packets of a message according to a first protocol, then analyzing the message according to a second protocol. The system determines if the message provides a correct checksum according to the second protocol. If the message provides the correct checksum according to the second protocol, the system alters the message and transmits the message according to the first protocol.

Abstract: A method of processing signal data comprises receiving signal data, calculating a first k-th moment from the signal data based on a first number of samples N1, calculating a second k-th moment from the signal data based on a second number of samples N2, the first number N1 being different than the second number N2, calculating a combined error, the combined error being a function of the first and second k-th moments, classifying a data region of the signal data as flat if the combined error is below or equal to a threshold curve in the data region, and classifying a data region of the signal data as non-flat if the combined error is higher than the threshold curve in the data region.

Abstract: Methods and apparatuses are described for formally verifying a bit-serial division circuit design or a bit-serial square-root circuit design. Some embodiments formally verify a bit-serial division circuit design using a set of properties that can be efficiently proven using a bit-level solver. In some embodiments, the set of properties that are used for verifying a bit-serial division circuit design does not include any terms that multiply a w-bit partial quotient with the divisor. Some embodiments formally verify a bit-serial square-root circuit design using a set of properties that can be efficiently proven using a bit-level solver. In some embodiments, the set of properties that are used for verifying a bit-serial square-root circuit design does not include any terms that compute a square of a w-bit partial square-root.

Abstract: A memory device includes but is not limited to a non-volatile memory array and control logic integrated with and distributed over the non-volatile memory array. The control logic can be operable to maintain a plurality of copies of data in the non-volatile memory array and detect errors by comparison of selected ones of the plurality of copies.

Abstract: A method, system and apparatus of lossy compression technique for video encoder bandwidth reduction using compression error data are disclosed. In one embodiment, a method includes storing an error data from a compression of an original reference data in an off-chip memory, accessing the error data during a motion compensation operation, and performing the motion compensation operation by applying the error data through an algorithm (e.g., determined by the method of storing the error data). The method may include generating a predicted frame in the motion compensation operation using a motion vector and an on-chip video data. In addition, the method may include determining the error data as a difference between a compressed reference data (e.g., is created by compressing the original reference data) and an original reference data (e.g., reconstructed from a prior predicted frame and a decompressed encoder data).

Abstract: An error detecting device of a dual controller system is provided. The first controller receives a sensing data from a sensor to calculate and generate a first data and outputs a final data if an error is not detected by comparing the first data with a second data transmitted from a second controller. The CAN transceiver receives the final data from the first controller and transmits the final data through a CAN bus. The second controller receives the sensing data from the sensor to calculate and generate a second data and transmits to the first controller an interrupt signal which prevents an output of the final data if an error is detected by comparing the second data with the final data fed back from the CAN transceiver. Accordingly, output transmission to the vehicle is controlled and the stability and reliability of the output data is increased.

Abstract: Systems and methods for computing sign disagreement between Le and La signals may implement one or more operations including, but not limited to: receiving an extrinsic log likelihood ratio (LLR) value; incrementing a sign-disagreement counter according to a sign disagreement between the extrinsic LLR value and an a priori LLR value; providing a value of the sign-disagreement counter to a binary short media defect (SMD) detector.

Abstract: Disclosed is a display device including a first storage unit having driving data for driving a display panel and a first check SUM data on the driving data stored therein, a second storage unit for retrieving the driving data and the first check SUM data from the first storage unit and storing the driving data and the check SUM data in response to the instruction of a ROM interface, and a data error detection/correction unit generating a second check SUM data with reference to the driving data stored in the second storage unit.

Abstract: Systems and techniques for improved error detection in data communication. A sending station encodes unencoded data to create an encoded message and passes the encoded data to transmission elements for transmission to a destination receiver. At the same time, error detection is performed using copies of the unencoded data and the encoded message. The encoded message is decoded using a decoding procedure identical to that to be used by the destination receiver. The copy of the unencoded data is compared to the decoded copy of the encoded message, and if the copy of the unencoded data does not match the decoded copy, the presence of an error is identified and error recovery procedures are performed.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a media defect detector circuit. The media defect detector circuit is operable to compare a data input derived from a medium against at least a first defect level to yield a first level output, and a second defect level to yield a second level output; and provide a combination of the first level output and the second level output as a defect quality output. A value of the defect quality output corresponds to a likelihood of a defect of the medium.

Abstract: A data processing device acquires a first parameter value of a hardware component, and calculates a first prediction value of the first parameter using a prediction algorithm. If a difference of the first prediction value and the first parameter falls within a deviation range, the first parameter value is determined as a real value and is stored. Otherwise, the device acquires a second parameter value of the hardware component that follows the first parameter value, and calculates a second prediction value of the second parameter value. If a difference between the second prediction value and the second parameter value falls with a second deviation range, the first parameter value is determined as a real value and is stored. Otherwise, the first parameter value is determined as a false value and is abandoned.

Abstract: There are included an opposite-side transmitter unit for transmitting the same messages to plural communication paths, respectively; and a host-side receiver unit for receiving the messages flowing through the plural communication paths, respectively; wherein, the receiver unit, compares the plural received messages to perform verification using error-detection code on any one of the messages when they are identical, or on all of the messages when there is a mismatch; and when detected error of message due to error inclusion or reception failure, discards all of the messages received at that time, and calculates an accumulated number of error detections for each of the communication paths through which the messages has been transmitted, so as to stop receiving the control-related message, when the number of error detections has reached a given number, from the communication path where the number of error detections has reached the given number.

Abstract: A method is disclosed for transferring a number of medical image data records from a first computation facility to a second computation facility, with the second computation facility sending a transmission confirmation to the first computation facility after transmission is completed. In at least one embodiment, before the image data records are transmitted, a first checksum is determined for all the image data records and sent with the image data records; the first checksum is extracted at the second computation facility and is compared with a second checksum determined from the transmitted image data records in the same manner as the first checksum; and the transmission confirmation indicates a failure if the checksums do not correspond.

Abstract: Method and high availability clusters that support synchronous state replication to provide for failover between nodes, and more precisely, between the master candidate machines at the corresponding nodes. There are at least two master candidates (m=2) in the high availability cluster and the election of the current master is performed by a quorum-based majority vote among quorum machines, whose number n is at least three and odd (n?3 and n is odd). The current master is issued a current time-limited lease to be measured off by the current master's local clock. In setting the duration or period of the lease, a relative clock skew is used to bound the duration to an upper bound, thus ensuring resistance to split brain situations during failover events.

Abstract: Various embodiments of the present invention provide systems and methods for media defect detection. For example, a data transfer system is disclosed that includes a data detector, a defect detector and a gating circuit. The data detector provides a soft output, and the defect detector is operable to receive the soft output and the data signal, and to assert a defect indication based at least in part on the soft output and the data signal. The gating circuit is operable to modify the soft output of the detector whenever the defect indication is asserted.

Abstract: Even if data includes a defect or an outlier in features thereof, the influence of the defect or the outlier of the features is suppressed to perform a highly precise abnormality detection, and data including high-dimensional features is processable to accomplish the highly stable detection of an abnormality. The abnormality detection system which detects abnormal data in a data sequence including data of multi-dimensional features, and the system includes storing or generating a generation distribution of features of the data and reference data indicative of normal data; obtaining, every piece of the data sequence, a probability that when features are virtually generated from the generation distribution, the features are nearer to the reference data than the features of each piece of the data; and taking the probability as a one-dimensional dissimilarity degree between each piece of the data and the reference data, thereby determining abnormal data.

Abstract: A measurement and authentication engine in a nonvolatile memory computes an original hash value on data read from the nonvolatile memory. A measurement and authentication engine in a host processor recomputes the hash value on the data received from nonvolatile memory and checks that the computed hash value matches the hash value generated and transferred from the nonvolatile memory.

Abstract: A comparison unit compares polarities of a plurality of redundant input signals. A comparison-result storing unit stores a comparison result of the comparison unit for each predetermined sampling cycle. A judgment unit judges whether the redundant input signals are normal using a plurality of comparison results for a predetermined number of samplings in a time-series order from a latest comparison result among a plurality of comparison results stored in the comparison-result storing unit.

Abstract: A method of testing a data connection using at least one test sequence, the method including providing a first bit sequence by a first generator; duplicating the first bit sequence to generate a second bit sequence identical to the first; and generating the at least one test sequence based on the first and second bit sequences and transmitting the at least one test sequence over a data connection to be tested.

Abstract: An information processing device includes: a receiving operation for receiving, from a transmission device, content and first verification data corresponding to divided content obtained by dividing the content; a detecting operation for detecting an error of the divided content based on second verification data to be calculated based on the divided content and the first verification data received in the receiving operation; and an obtaining operation for obtaining other divided content corresponding to the divided content having the error detected in the detecting operation from another information processing device different from the transmission device, when the error of the divided content is detected in the detecting operation.

Abstract: Data is compressed using content addressable memory without disruption despite error using a plurality of content addressable memories to detect sequentially repeating data elements of the data. Compression information is generated for each sequence of repeating data elements that repeat for at least a compression threshold without any one of the plurality of content addressable memories generating an indication of an error for a matching content addressable memory entry. Individual data elements are output for each of the data elements that do not repeat for the compression threshold. Compression information is generated for each sequence of repeating data elements that repeat for at least the compression threshold and then generating a currently searched data element that matches the repeating data elements when any one of the plurality of content addressable memories generates an indication of an error for a content addressable memory entry that matches the currently searched data element.

Abstract: An analyzer may include a body housing having a first ID, a first measurement module having a second ID that is different from the first ID, the first measurement module being releasably attachable to the body housing, a first memory in the body housing, the first memory being configured to store the first ID, first setting data and first correction data, a second memory in the first measurement module, the second memory being configured to store the second ID, second setting data and second correction data, a first CPU in the body housing, the first CPU being configured to detect the first measurement module having the second ID, and a first data transmission unit in the body housing, the first data transmission unit being configured to transmit the first setting data and the first correction data to the second memory.

Abstract: A network device for building up a network connection via a high-definition multimedia interface, includes a scrambler, a descrambler, a comparator and a control unit. The scrambler is utilized for generating a transmission signal according to a first seed. The descrambler is for decoding a receiving signal to generate a second seed. The comparator is for generating a comparing result according to the first seed and the second seed. The control unit is for controlling the network connection according to the comparing result.

Abstract: Systems and methods for 1553 bus operation self checking are provided. In one embodiment, a fault tolerant computer comprises a self-checking processor pair that includes a master processor, a checking processor, and self-checking pair logic; a 1553 bus transceiver; and a device comprising 1553 self-checking logic coupled between the self-checking processor pair and the 1553 bus transceiver, wherein the 1553 self-checking logic manages data communication between the 1553 bus transceiver and the self-checking processor pair. The 1553 self-checking logic includes a primary logic and a secondary logic that operate in lock-step. When the 1553 self-checking logic writes data to the 1553 bus transceiver, the 1553 self-checking logic compares a first 1553 formatted message generated by the primary logic to a second 1553 formatted message generated by the secondary logic, and generates an error indication when the first 1553 formatted message does not match the second 1553 formatted message.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for variable rate encoding and/or decoding in a data processing system.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a noise injection circuit. The noise injection circuit is operable to: determine a difference between a first data output and a second data output to yield an error; and augment an interim data with a noise value corresponding to the error to yield a noise injected output. The interim data may be either the first data output or the second data output.

Abstract: An apparatus for comparing pairs of binary words includes an intermediate value determiner and an error detector. The intermediate value determiner determines an intermediate binary word so that the intermediate binary word is equal to a reference binary word for a first pair of equal or inverted binary words, so that the intermediate binary word is equal to the inverted reference binary word for a second pair of equal or inverted binary words and so that the intermediate binary word is unequal to the reference binary word and the inverted reference binary word for a pair of unequal and uninverted binary words, if the intermediate value determiner works faultlessly. Further, the error detector provides an error signal based on the intermediate binary word so that the error signal indicates whether or not the binary words of a pair of binary words are equal or inverted.

Abstract: A bill identification apparatus accurately identifying an authenticity with a folding line formed in a watermark. The bill identification apparatus includes: bill reading means; a converter which converts the watermarked image read by the bill reading means for each pixel containing color information having brightness; a image correction processing part which calculates an average density value for each pixel array in one direction, an average density value for each pixel array in the other direction, and an average density value of an entire watermarked image and corrects density values of respective pixels so as to approximate or match the average density value of the entire watermarked image; a reference data storage part which stores a reference watermarked image; an identification processing part which compares the corrected image by the image correction processing part with the reference watermarked image and identifies an authenticity.