Abstract: A method for writing a logical block into a storage pool includes receiving a request to write the logical block, selecting a block allocation policy, by a file system associated with the storage pool, from a set of allocation policies, obtaining a list of free physical blocks in the storage pool, allocating a physical block from the list of free physical blocks, based on the block allocation policy, and writing the logical block to the physical block.

Abstract: A test and measurement instrument including an input configured to receive a signal and output digitized data; a memory configured to store reference digitized data including a reference sequence; a pattern detector configured to detect the reference sequence in the digitized data and generate a synchronization signal in response; a memory controller configured to cause the memory to output the reference digitized data in response to the synchronization signal; and a comparator configured to compare the reference digitized data output from the memory to the digitized data.

Abstract: A method for auditing and verifying configuration items (CIs) in an information technology (IT) configuration management database (CMDB) includes identifying which configuration item (CI) types should be part of an audit, defining link rules to link an authorized CI type stored in a CMDB to an actual CI type that is part of an IT infrastructure, retrieving all authorized CI instances of the identified CI types from the CMDB, retrieving all actual CI instances of the identified CI types from a discovery upload of a current IT environment, comparing the actual CI instances to the authorized CI instances, and taking remedial action when variances are discovered.

Abstract: An error detection device for an address decoder converting an input address to an associated output address out of a plurality of valid output addresses using a 1-out-of-n decoder, the error detection device including a regenerator for generating a regenerated address on the basis of the output address from the 1-out-of-n decoder, and a comparer for receiving the input address and the regenerated address and to output a signal, on the basis of a comparison of the input address and the regenerated address, which indicates an error in the conversion of the input address to the output address if the input address and the regenerated address do not match, and which indicates an error-free conversion of the input address to the output address if the input address equals the regenerated address.

Abstract: In an arithmetic circuit, every time a numerical value is stored in a register, a partial solution is predicted on the basis of the numerical value, an intermediate value is generated by a predetermined calculation using one or more predicted partial solutions, an extended sign bit is appended to the intermediate value by sign extension, and the intermediate value to which the extended sign bit is appended is stored in the register. In addition, the solution is generated on the basis of the one or more partial solutions. A value of a sign bit constituting the intermediate value stored in the register is compared with a value of the extended sign bit stored in the register, and an error signal is outputted when the value of the sign bit is different from the value of the extended sign bit.

Abstract: Some embodiments of the present invention provide a system that provides error detection and correction after a failure of a memory component in a memory system. During operation, the system accesses a block of data from the memory system, wherein the memory system is previously determined to have a specific failed memory component. Each block of data in the memory system includes an array of bits logically organized into R rows and C columns, including a row checkbit column including row-checkbits for each of the R rows, an inner checkbit column including X<R inner checkbits and R?X data bits, and C?2 data-bit columns containing data bits. Note that each column is stored in a different memory component, and the checkbits are generated from the data bits to provide block-level detection and correction for a failed memory component. Next, the system attempts to correct a column of the block from the failed memory component by using the checkbits and the data bits to produce a corrected column.

Abstract: Exemplary method, system, and computer program product embodiments for data verification in a storage system are provided. A read of data is asynchronously submitted to nonvolatile storage media. A read of a first checksum signature is submitted to a solid state, sidefile memory location of a storage controller in the storage subsystem. The first checksum signature is representative of the data previously written to the nonvolatile storage media. A second checksum signature is calculated from the read of the data. The first and second checksum signatures are compared. If a match is not determined, a critical event is reported.

Abstract: A method for validating SRS registry transaction data includes receiving OLTP transaction data from a first database, parsing the OLTP transaction data, and comparing the parsed OLTP transaction data to one or more of a set of profiles. Each of the one or more of the set of profiles includes metadata in XML files. The method also includes caching the parsed OLTP transaction data in a first data cache, receiving log data associated with the OLTP transaction data; and caching the log data in a second data cache. The method further includes correlating the parsed transaction data cached in the first data cache with the log data cached in the second data cache.

Abstract: Methods for automatically identifying and classifying a crisis state occurring in a system having a plurality of computer resources. Signals are received from a device that collects the signals from each computer resource in the system. For each epoch, an epoch fingerprint is generated. Upon detecting a performance crisis within the system, a crisis fingerprint is generated consisting of at least one epoch fingerprint. The technology is able to identify that a performance crisis has previously occurred within the datacenter if a generated crisis fingerprint favorably matches any of the model crisis fingerprints stored in a database. The technology may also predict that a crisis is about to occur.

Abstract: Systems and methods are disclosed for monitoring a voltage supplied by a voltage regulation module to a processor in response to a dynamic VID generated by the processor. In one embodiment, a voltage monitoring system monitors the voltage generated by the voltage regulation module to ensure the supplied voltage is within regulation thresholds. The voltage monitoring system acquires an analog reading of the supplied voltage and converts it to a digital value. If the VID changes during the conversion, the result of the A/D conversion is discarded. If the VID does not change, the voltage monitoring system accepts the result of the A/D conversion and compares the supplied voltage to the voltage expected in response to the VID. The voltage monitoring system may compute the error between the actual and expected voltage for each accepted A/D conversion. These errors may be accumulated and averaged. The accumulated error may be compared with regulation thresholds, such as a predefined allowable margin of error.

Abstract: A system and method for ensuring or verifying the integrity of data transmitted between protection domains. When the data is transmitted, it may be received in a different logical configuration (e.g., as a different number of “chunks”). The receiving domain computes its data integrity metadata (e.g., checksum, CRC, parity) on its form of the data using its protection scheme (e.g., checksum algorithm), and also applies the sending domain's protection scheme to the data as it was received from the sending domain. Similarly, the sending domain applies the receiving domain's protection scheme to compute data integrity metadata on the transmitted data as it appears in the receiving domain. The metadata may be compared to determine whether the data was corrupted during the transfer. Either domain may forward its data integrity metadata to the other, which may store and/or forward it as needed.

Abstract: The apparatus for appending CRC to the data or signaling to be transmitted in the communication systems is proposed in present invention. If the length of the CRC-bit sequence is 16, one of the CRC generation polynomials listed in present invention can be adopted. If the length of the CRC bit sequence is 18, one of the CRC generation polynomials listed in present invention can be adopted. If the length of the CRC bit sequence is 20, one of the CRC generation polynomials listed in present invention can be adopted. With the optimized CRC generation polynomials proposed in present invention, mistakes in signaling detection can be effectively reduced so that system spectrum utility can be improved.

Abstract: A radio LSI is provided that is not to cause a delay in sending acknowledgement data. A latch circuit provided in a sending/receiving section latches frame control information out of data being received. A decoder decodes the frame control information to decode a data length and structure of an address field. Furthermore, a latch circuit latches the address-field data of the reception data according to the decoded address-field information. A comparing circuit compares a content of a register entered with an address of the opposite-of-communication completely prepared data to be sent, with a source address of the data being received, to determine a setting/resetting of frame pending in acknowledgement data. A content of the determination is sent to a data-link section. This provides information required for acknowledgement data before completely receiving data, thus eliminating the possibility to cause a delay in sending acknowledgement data.

Abstract: Provided are methods, systems, and apparatus for error detection of bits of a data packet received at a receiver unit by detecting corrupted data bits.

Abstract: In an integer partitioning process S701, an integer partitioning unit 110 inputs an order p of a finite group G and an integer e, and calculates an integer e1 and an integer e2 that satisfy e1·e?e2(mod p) based on the order p of the finite group G and the integer e which are input. In a verification value calculation process S702, a verification value calculation unit 130 inputs an element s of the finite group G and an element h of the finite group G, and calculates an element a (=e1·h?e2·s) of the finite group G based on the element s and the element h which are input and the integer e1 and the integer e2 which are calculated by the integer partitioning unit 110 in the integer partitioning process S701. In a verification judging process S703, a verification judging unit 150 judges, based on the element a calculated by the verification value calculation unit 130, whether or not the element a is an identity element O of the finite group G. Hence, whether or not h=e·s is established is judged at high speed.

Abstract: An apparatus for managing a data backup is disclosed. In accordance with the apparatus of the present invention, an integrity verification data randomly extracted according to a predetermined condition is used to facilitate a checking of an error that may exist in a backup data, and extracting and locating the integrity verification data are facilitated by using an index data, thereby minimizing a work time for verifying an integrity of the backup data.

Abstract: An estimating unit includes: an error detecting unit which detects an error among a plurality of frames received from an interface unit of a transmission device; a request sending unit which produces a first frame including a data collection request for requesting data collection upon the error detecting unit detecting the error, and which sends the first frame to the interface unit; an extracting unit which extracts, from the plurality of frames received from the interface unit, a second frame including the error detected by the error detecting unit and a third frame including a reply of the interface unit to the data collection request; and a saving unit in which the second frame extracted by the extracting unit is saved.

Abstract: The invention relates to decode data transmitted via US National Weather Service NOAA Weather Radio (NWR) transmitters or any other data transmitted in a comparable way. According to the invention a method to decode a received data string comprises the steps of locating a predefined significant part of the data string, disregarding an insignificant part of the data string, and further checking only the located significant part of the data string. Decoding according to the proposed algorithm is very reliable.

Abstract: An apparatus, system, and method are disclosed for storing information in a storage device that includes multi-level memory cells. The method involves storing data that is written to the storage device in the LSBs of the multi-level memory cells, and storing audit data in the MSBs of the multi-level memory cells. The audit data can be read separately from the data and used to determine whether or not there has been any unintended drift between states in the multi-level cells. The audit data may be used to correct data when the errors in the data are too numerous to be corrected using error correction code (ECC). The audit data may also be used to monitor the general health of the storage device. The monitoring process may run as a background process on the storage device. The storage device may transition the multi-level memory cells to operate as single-level memory cells.

Abstract: Consensus testing of electronic system. A tester (112) for testing an electronic system (100) includes: a traffic interface (114) to receive traffic (102) from a test of an electronic system (100); an element comparator (118) to extract a value from an element of the traffic (102) and to compare the extracted element value with an element value (110) obtained from another test of another electronic system (104, 106, 108); and a test result generator (122) to generate consensus information (124) on the interoperability of the electronic system (100), based on comparing (120) the extracted element values of the electronic system (100) with the element values obtained from the other test of the other electronic system (104, 106, 108).

Abstract: Configuration information including number of normal cell areas and number of spare cell areas arranged in a memory macro and a size of each cell area is extracted from circuit design information, and electrical test results of the normal cell areas and the spare cell areas arranged in the memory macro are collected. Arrangement information corresponding to a collection order of the electrical test results is converted to a two-dimensional coordinate value for two-dimensionally displaying the arrangement information corresponding to a collection order of the electrical test results in a unit of cell area in association with a physical layout of a memory cell in the memory macro based on the configuration information. The collected electrical test results are displayed based on the two-dimensional coordinate value so that the normal cell areas and the spare cell areas can be distinguished.

Abstract: Methods and apparatuses for using interpolation to associate timestamp values to data received in a data capture and analysis system. An analysis processor receives data representing data transferred in a communications link. The analysis processor also receives timestamp signals. The analysis processor performs an interpolation between at least two timestamp values received and associates results of the interpolation with the data. The analysis processor analyzes the data. A logic device can be coupled to the analysis processor to interleave timestamp signal values with the data and transmit the interleaved data and timestamp signals to the analysis processor.

Abstract: For the transmission of information with verification of transmission errors, a useful information message (M) is transmitted in a determined frame while being associated with a determined number p of transmission error verification bits (CRC,S) also transmitted in the frame. In order to have an element allowing the verification of intentional errors, determined number p1 of the transmission error verification bits form a seal (S) obtained from a determined sealing function, where p1 is a number less than p. Application to radiocommunications equipment requiring the verification of the integrity and the authentication of the messages transmitted.

Abstract: The present invention discloses a method for self-routing in synchronous digital cross-connection, comprising: self-routing transmitting means insert a CM data into a STM-N data stream according to a frame header indicator and a self-routing start address signal; self-routing receiving means extract the CM data from the STM-N data stream according to the frame header indicator and the self-routing start address signal, and write the CM data into a cross-connection control memory. The present invention also discloses a system for self-routing in synchronous digital cross-connection, comprising: self-routing transmitting means and self-routing receiving means, wherein, the self-routing transmitting means comprise a self-routing transmitting control unit, a first CRC checking unit and an inserting data generating unit, the self-routing receiving means comprise a self-routing extracting control unit, a second CRC checking unit and a cross-connection control memory.

Abstract: A checking method in which serial data protected by check data are transmitted via a serial data bus from a transmitter to a receiver, the receiver then conditions the data and compares them with the transmitted check data in order to recognize transmission errors, wherein the transmitter bases the production of the check data and the receiver bases the conditioning of the data on the same check data formation method, wherein the check data formation/conditioning is performed using error recognition hardware, wherein the region of the receiver contains not only the error recognition hardware but also error recognition software which are used to additionally check the received data, and wherein also an error in the transmitted data and/or check data is caused by a transmitter-end error stimulation. A transmission and reception circuit for carrying out the above method and also the use thereof is also disclosed.

Abstract: Certain embodiments of the invention may be found in a method and system for handling data in port bypass controllers for storage systems and may comprise receiving a data stream from a receive port bypass controller's port and buffering at least a portion of the received data stream in at least one EFIFO buffer integrated within the port bypass controller. A data rate or frequency of the received data stream may be changed by inserting at least one extended fill word in the buffered portion of the received data stream or by deleting at least one fill word from the received data stream buffered in the EFIFO buffer. The extended fill word may comprise a loop initialization primitive (LIP), a loop port bypass (LPB), a loop port enable (LPE), a not operation state (NOS), an offline state (OLS), a link reset response (LRR) and/or a link reset (LR).

Abstract: The invention relates to a microprocessor system (60) for controlling and/or regulating at least partly security-critical processes, which system comprises two central processing units (1, 2) integrated into a chip housing, a first and a second at least one complete memory (7) on the first bus system, and check data in one or more check data memories, said data being related to data of the memory in the first bus system. The check data memory is smaller than the complete memory. The bus systems comprise comparative and/or driver components which facilitate data exchange and/or comparison of data between the two bus systems. The one or more check data memories are arranged on the first bus system. On the second bus system, neither a check data memory nor a memory safeguarding data of the memory on the first bus is used. The invention also relates to the use of the inventive microprocessor system in automotive control devices.

Abstract: A method for a bounds test includes receiving a base value, a size value, and a test value; subtracting the base value from the test value to generate a result value in a signed format; comparing the result value and the size value, and passing the bounds test when the size value exceeds the result value interpreted as an unsigned value. A computer readable medium stores instructions for a bounds test, the instructions for causing a computer to perform: receiving a base value, a size value, and a test value; subtracting the base value from the test value to generate a result value in a signed format; comparing the result value and the size value; and passing the bounds test when the size value exceeds the result value interpreted as an unsigned value. A bounds test system includes a processor, wherein the processor supports two's-compliment notation; and a memory, operatively connected to the processor.

Abstract: A method of verifying a digital design is disclosed. The method comprises generating a reference model for a first digital design and creating an operational model for a second digital design, wherein the first digital design and the second digital design are intended to have a same logical function. A plurality of testcase types are then created by constraining one or more internal signals, and one or more test scripts representing the plurality of testcase types are produced. The method also includes verifying the second digital design with a testing simulation program by comparing results of the test scripts from the operational model and the reference model.

Abstract: A demodulator cancels out the echo signal properties in the received signal to generate a primary signal, and cancels out the primary signal properties in the received signal to generate a separate echo signal. In addition, the demodulator may combine the primary signal and the echo signal in a comparison/combination operation to generate a third combined signal. Error correction operations may then be performed on all three of the primary signal, echo signal and combined signal, with the results of those error correction operations being used to select which of the three signals will serve as the transport stream.

Abstract: Embodiments of an invention for verifying firmware using system memory error check logic are disclosed. In one embodiment, an apparatus includes an execution core, firmware, error check logic, non-volatile memory, comparison logic, and security logic. The error check logic is to generate, for each line of firmware, an error check value. The comparison logic is to compare stored error check values from the non-volatile memory with generated error check values from the error check logic. The security logic is to prevent the execution core from executing the firmware if the comparison logic detects a mismatch between the stored error code values and the generated error code values.

Abstract: A method and apparatus for verifying non-volatile memory. A first transmission of data is received by a first memory of a device. The data is received by a non-volatile memory of the device. The data received by the non-volatile memory is verified by comparing it to the data in the first memory with comparison logic of the device. The verification is performed without receiving a second transmission of the data and without sending a second transmission of the data. A result is generated from the comparison.

Abstract: Embodiments of apparatuses and methods for correcting intermittent errors in data storage structures are disclosed. In one embodiment, an apparatus includes a data storage location, error detection logic, inverting logic, control logic, operating logic, and evaluation logic. The error detection logic is to detect an error in a data value read from the data storage location. The inverting logic is to invert the erroneous data value to produce an inverted erroneous data value. The control logic is to cause the inverted erroneous data value to be stored in the data storage location and subsequently read from the data storage location to produce an operand value. The operating logic is to perform a logical operation using the erroneous data value and the operand value. The evaluation logic is to evaluate the result to determine if the error is a soft error.

Abstract: A method reads a datum saved in a memory by selecting an address of the memory in which the datum to be read is saved, reading the datum in the memory at the selected address, saving the datum read in a storage space, and when the memory is not being accessed by a CPU, reading the datum in the memory, reading the datum saved in the storage space, and activating an error signal if the datum read in the memory is different from the datum saved. The method can be applied particularly to the protection of smart card integrated circuits.

Abstract: Systems, integrated circuits, and methods for protecting data stored in third dimensional vertically stacked memory technology are disclosed. An integrated circuit is configured to perform duplication of data disposed in multi-layered memory that can comprise two-terminal cross-point memory arrays fabricated BEOL on top of a FEOL logic layer that includes active circuitry for performing data operations (e.g., read, write, program, and erase) on the multi-layered memory. For example, the integrated circuit can include a first subset of BEOL memory layers configured to store data, a second subset of the BEOL memory layers configured to store a copy of the data from the first subset of memory layers, a FEOL redundancy circuit coupled to the first subset of the memory layers and the second subset of the memory layers, the redundancy circuit being configured to provide both a portion of the data and a copy of the portion of the data.

Abstract: A storage device includes a solid-state storage medium having a plurality of cells adapted to store data and an analog-to-digital converter (ADC) coupled to at least one cell of the plurality of cells. The ADC includes a first operating mode having a first number of quantization levels to determine a value stored in the at least one cell based on a number of possible values represented by the at least one cell. The ADC further includes a second operating mode having a second number of quantization levels to determine the value stored in the at least one cell, where the second number of quantization levels is greater than the first number of quantization levels. The ADC selectively enables the first or the second operating mode as a selected operating mode and determines a signal representative of the value stored in the at least one cell using the selected operating mode.

Abstract: A system and method are provided for storing and using recovery state information during a data stream transfer, such as a download. During the download of compressed, archived data, the system tracks the position of the last file boundary and the position of the last compression block boundary before the last file boundary, and the system stores this information as a recovery state. If the download is interrupted, the system uses the recovery state information to resume the download at an efficient location in the data stream.

Abstract: Detection of faults in a transmitted signal stream occurs by recovering, from the information stream, a water mark embedded in the stream prior to transmission. The embedded watermark has data characteristic of stream quality. Thereafter, the at least one watermark property is analyzed to detect faults in the received information stream.

Abstract: A processor includes an arithmetic device, a storage device that holds arithmetic data, a data generator that generates test data, an address generator that generates an address at which the test data is to be written, a test data number counter that counts a number of test data, an error information holder that holds mismatch error information, an error occurrence bit position holder that holds a position of a bit at which a mismatch error has occurred, an error occurrence test data number holder that holds number of test data counted by the test data number counter, and a comparator that compares test data written to the storage device with test data read from the storage device and stores error information in the error information holder and a position of a bit and number of the test data in which the mismatch error has occurred.

Abstract: An apparatus for verifying training data using machine learning includes: a training data separation unit for separating provided initial training data into N training data and N verification data, where N is a natural number; a machine learning unit for performing machine learning on the separated training data to generate a training model; an automatic tagging unit for automatically tagging an original text of the verification data using the generated training model to provide automatic tagging results; and an error determination unit for comparing the verification data to the automatic tagging results to determine error candidates of the training data.

Abstract: A semiconductor device includes a memory module provided with a plurality of memory cells, a verify determination unit that performs quality determination of read data that have been read from the memory cells on the basis of the read data and an expected value prepared in advance, and a power source monitoring circuit that detects fluctuations equal to or greater than a predetermined variation rate in a power source voltage supplied to the memory module and outputs a power source abnormality detection signal. Furthermore, the verify determination unit invalidates a result of the quality determination when the power source abnormality detection signal indicates an abnormal state of the power source voltage.

Abstract: A method to detect an event between a data source and a data sink using a trigger core is described herein. The method comprises monitoring control lines and an associated data stream for a programmable pattern, wherein the pattern is one or more of a condition, state or event. The method further comprises generating an indication by updating a status register, sending an interrupt or asserting a control line upon a pattern match.

Abstract: A system, apparatus, computer program product and method of performing functional validation testing in a system are provided. Generally, functional validation testing includes data acquisition and data validation testing. During the functional validation testing two devices may be exchanging data. The exchange of data by the two devices may be referred to as data acquisition. The data from one device and the data from the other device may be compared to each other. This may be referred to as data validation. When data is exchanged during data acquisition, it is also stored in appropriate locations in a pool of buffers in memory. During the data acquisition, checks are made to determine if the system is entering an idle cycle. If so, the data validation test is performed by using the data in the pool of buffers in memory.

Abstract: A inter-network interface device usable in a highly reliable industrial control system provides an interface between a producer module transmitting redundant messages in accordance with a communication protocol and a consumer module receiving the messages in accordance with a different communication protocol. The inter-network interface device includes a first network interface receiving two messages from the producer, a microprocessor capable of converting the messages from the producer communication protocol to consumer communication protocol, and a second network interface transmitting the messages to the consumer. One of the messages is reversible altered with respect to the other message. The altered message is uninverted in the consumer module, and compared to the other message to ensure that no transmission errors have occurred.

Abstract: A method for reconstructing a logical block, wherein the logical block comprises a first set of sectors. The method including obtaining a copy of the logical block comprising a second set of sectors, determining which of the sectors in the first set of sectors are identical to sectors in the second set of sectors to obtain identical sectors, selecting a first combination of non-identical sectors from the first set of sectors and the second set of sectors, combining a copy of each of the identical sectors with the first combination of non-identical sectors to obtain a first reconstructed logical block, calculating a first checksum for the first reconstructed logical block, and determining whether the first calculated checksum is equal to the stored checksum associated with the first logical block.

Abstract: An error checking system includes an input device for receiving a data element including parity information; a parity check device for checking the parity information of the data element to determine whether the data element is valid; a CRC generator coupled to the parity check device for generating a CRC for the data element; and an output device for transmitting the data element with the parity information and CRC to a downstream device over a transmission link. The parity check device is operative to output a corruption signal to the CRC generator if the parity check device determines that the data element is invalid, to instruct the CRC generator to corrupt the CRC generation for that data element.

Abstract: A network device and a method for controlling the same. The device and method each performed the operations of transforming an input signal so as to allow the input signal to be divided according to frequency bands and resolutions, comparing the transformed input signal with abnormal signal information stored in an abnormal signal database (DB), and determining whether the input signal is a normal signal. When the input signal is a normal signal, the network and method each perform the operation of delivering the transformed input signal to a codec.

Abstract: Provided is a method of forming reference information for defining a fault pattern of equipment, and monitoring equipment. One example embodiment method may include performing an angle spectrum analysis by re-classifying fault points distributed on a plane, the plane including a first component axis and a second component axis, and the re-classifying fault points including calculating an angle for each of the fault points with reference to any one of the first component axis and the second component axis of the plane, and forming a reference fault pattern for defining a fault pattern of the re-classified fault points.

Abstract: A comparison unit compares polarities of a plurality of redundant input signals. A comparison-result storing unit stores a comparison result of the comparison unit for each predetermined sampling cycle. A judgment unit judges whether the redundant input signals are normal using a plurality of comparison results for a predetermined number of samplings in a time-series order from a latest comparison result among a plurality of comparison results stored in the comparison-result storing unit.

Abstract: First, a yield is calculated by employing conventional SSTA. Next, an independent LL set is determined, the independent LL set being a subset having sets of delay element sets that only include gates and nets not being shared by two or more paths. Next, a yield is calculated by employing SSTA while using only the independent LL set. Thereby, it is understood that the actual yield is between the yield obtained by employing the conventional SSTA and the yield obtained by employing the SSTA using only the independent LL set.