Abstract: A method for measuring multimedia communication quality is disclosed. The multimedia video communication quality may be objectively reflected through the embedment and extraction of digital watermark under a precondition that the quality of the multimedia video data is not obviously affected. In the invention, each frame of the multimedia video data is uniformly divided into blocks of equal size and watermark data is embedded in each of the blocks, so that the watermark may be uniformly distributed. The multimedia video data are divided into groups, and the watermark is embedded in a part of the frames with equal interval between the frames in each group to reduce the effect of the watermark on the data. The watermark information is directly embedded in the spatial domain of the original video data.

Abstract: Techniques, apparatus, and systems for injecting a memory fault can include obtaining first data and second data different from the first data, generating first error detection information based on the first data, writing the second data to a memory unit using a specified address, and using the first error detection information as error detection information for the second data to create a memory fault condition.

Abstract: Methods, systems, and computer-readable media to compare values of a bounded domain are disclosed. A particular method includes, for each value in a bounded domain, determining a corresponding set of allowable errors associated with the value. The sets of allowable errors are stored at a memory. The method includes determining a comparison score between a first value of the bounded domain and a second value of the bounded domain based on a comparison of a first set of allowable errors corresponding to the first value and a second set of allowable errors corresponding to the second value.

Abstract: An error detection system is provided. The system includes a data array that includes one or more data entries. A copy datastore selectively stores a copy of a first single data entry of the data array. An index generator selectively increments an index that references the data array. A first comparator compares the copy with a second single data entry from the data array based on the index. An error generator generates an error signal based on a result from the first comparator.

Abstract: A memory system has a redundancy coding circuit that performs redundancy coding process for write data, an inverter circuit which inverts values of individual bits of the data that has resulted from the redundancy coding process, a selector which selects the data that has resulted from the redundancy coding process or data that has been inverted by the inverter circuit based on a selecting signal, a memory which stores the selected data, a comparator which compares data read from the memory with the selected data and outputs a comparison result, a write control circuit which generates the selecting signal based on the comparison results, and a redundancy decoding circuit that performs a redundancy decoding process for data read from the memory to output the processed data.

Abstract: Processed results are received when processors make compatible computations on data of a common object. A computation command signal is generated and fed to the processors in response to a start signal from any one of the processors so that the processors can make computations with different operation timings. Then, the results of the computations made by the processors are compared with each other. Thus, apparatus capable of small size, high performance and safety at the same time can be achieved by the above construction using the processors.

Abstract: Provided are a system, method and article of manufacture for validating an expected data output of an application under test. A first table comprising named columns populated with the expected data output and a second table comprising named columns associated with the expected data output of the named columns of the first table are retrieved. The named columns of the first table are compared with the named columns of the second table. An alert is generated in response to detecting a difference between a characteristic of a named column of the first table and a characteristic of a named column of the second table.

Abstract: A data read-out circuit is provided with a sense amplifier circuit and a selector. The sense amplifier circuit senses a stored data stored in a memory cell array by using a plurality of reference levels to generate a plurality of read data, respectively. Thus, the sense amplifier circuit outputs the plurality of read data with regard to the stored data. The selector selects a data corresponding to any one of the plurality of read data based on a control signal and outputs the selected data as an output data.

Abstract: An addressable interface selectively enables JTAG TAP domain operations or Trace domain operations within an IC. After being enabled, the TAP receives TMS and TDI input from a single data pin. After being enabled, the Trace domain acquires data from a functioning circuit within the IC in response to a first clock and outputs the acquired data from the IC in response to a second clock. An addressable two pin interface loads and updates instructions and data to a TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller.

Abstract: Example embodiments provide a method and apparatus of correcting error data due to charge loss within a non-volatile memory device including a plurality of memory cells. The method of correcting error data within the non-volatile memory devices may include detecting error data in a second data group by comparing a first data group read from memory cells in response to a first voltage with the second data group read from memory cells in response to a second voltage. The second voltage is higher than the first voltage. Error data in the first data group is detected by error-correcting code (ECC). Re-writing data in the memory cells is performed by correcting error data in the first data group and error data in the second data group. A central processing unit (CPU) may detect error in the second data group. The second data group may be read through a page buffer and compared with the first data group stored in a SRAM. The detected error may be updated to the page buffer.

Abstract: A matched state detection unit (33) of a video matching device (100) detects a reference video frame, of the respective video frames of a reference video (1) and degraded video (2B), which is in a matched state in which it is spatially and temporally matched with each degraded video frame. A matching degree derivation unit (34) controls a degradation amount derivation unit (40) to acquire the first degradation amount indicating the degradation amount between a reference video frame and a degraded video frame in the matched state and the second degradation amount indicating the degradation amount between a reference video frame and a degraded video frame in a state shifted from the matched state by a predetermined number of pixels and calculate a matching degree on the basis of the ratio between the first degradation amount and the second degradation amount. A matching information output unit (35) outputs the matching degree between the reference video and the degraded video after matching.

Abstract: In an electronic apparatus, a first microcomputer is monitored by a second microcomputer, which periodically transmits data relating to a main function to the first microcomputer to be processed. The first microcomputer periodically updates a variable value, performs a predetermined calculation operation whose final result should be a specific fixed value, adds that final result to the updated variable value to obtain a sum value, and transmits the sum value and updated variable value concurrently to the second microcomputer. The second microcomputer determines that the first microcomputer is operating abnormally if the difference between the received sum value and variable value is not equal to the specific fixed value.

Abstract: Apparatus and methods for detecting data bit edge in a meander encoded information bit from a satellite positioning system (SPS) such as GLONASS (Global Navigation Satellite System) are discussed. A method comprises receiving meander encoded data samples from a meander encoded information bit. The method includes computing a set of accumulated values for a corresponding set of hypotheses, each of the hypotheses corresponding to a hypothesized bit edge phase. The process of computing an accumulated value of the set of accumulated values includes providing a toggled subset of the meander encoded data samples, and integrating the toggled subset of the meander encoded data samples with an un-toggled subset of the meander encoded data samples to produce the accumulated value. The method also includes selecting a best hypothesis from the set of hypotheses corresponding to a maximum value of the set of accumulated values, wherein the best hypothesis represents the data bit edge.

Abstract: A method to detect an event between a data source and a data sink using a trigger core is described herein. The method comprises monitoring control lines and an associated data stream for a programmable pattern, wherein the pattern is one or more of a condition, state or event. The method further comprises generating an indication by updating a status register, sending an interrupt or asserting a control line upon a pattern match.

Abstract: The disclosed embodiments relate to a memory system that facilitates probabilistic error correction for a failed memory component with partial-component sparing. During operation, the memory system accesses blocks of data, wherein each block of data includes an array of bits logically organized into R rows and C columns. The C columns include (1) a row-checkbit column containing row-parity bits for each of the R rows, (2) an inner-checkbit column containing X=R?S inner checkbits and S spare bits, and (3) C-2 data-bit columns containing data bits. Moreover, each column is stored in a different memory component, and the checkbits are generated from the data bits to provide guaranteed detection and probabilistic correction for a failed memory component.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a system is disclosed for monitoring a voltage supplied by a voltage regulation module to a processor in response to a dynamic VID generated by the processor. The voltage monitoring system monitors the voltage generated by the voltage regulation module to ensure the supplied voltage is within regulation thresholds. The voltage monitoring system acquires an analog reading of the supplied voltage and converts it to a digital value. If the VID changes during the conversion, the result of the A/D conversion is discarded. If the VID does not change, the voltage monitoring system accepts the result of the A/D conversion and compares the supplied voltage to the voltage expected in response to the VID. The voltage monitoring system may also compute the error between the actual and expected voltage for each accepted A/D conversion.

Abstract: Illustrative embodiments provide a computer implemented method, an apparatus, and a computer program product for error detection and recovery using an asynchronous transaction journal. In an illustrative embodiment the computer implemented method receives a request message from a requester, stores the request message in the asynchronous transaction journal and determines whether a sequence number contained within the request message is equal to a predetermined number. When the sequence number is equal, the computer implemented method performs a request in the request message to obtain a result and returns the result to the requester; otherwise the computer implemented method detects an error. The computer implemented method then attempts recovery from the error; otherwise the computer implemented method notifies the requestee.

Abstract: Embodiments of the invention relate to page faulting of memory operations in a subject code block. An aspect of the invention concerns an apparatus comprising a component for identifying a first object node having a first dependency path and second object node having a second dependency path, and a component for calculating a numerical difference between a first addressing value and a second addressing value, where the first and second addressing values are respectively associated with the first and second dependency paths. The apparatus may include a dependency generator for ordering a subject order list of the subject code block in an object dependency non-page-faulting order when the numerical difference is equal to or less than an assigned memory page size.

Abstract: A method for detecting microprocessor hardware faults includes sending at least one input signal to a logic block within the microprocessor, collecting an output response to the input signal from the logic block, and determining whether the output response matches an expected output response of the logic block.

Abstract: Multiple embodiments relate to a method for detecting a fault on a data line in a bus system in a two-line data network having at least two control units. A data signal is emitted by a transmitter-receiver unit on the two data lines as a differential voltage signal that includes a defined quiescent current. The data lines are mutually connected through a resistance bridge for detecting the middle voltage. The middle voltage is detected directly by a microcontroller after a low-pass filter or as a digital value after an analog-to-digital conversion. The result is displayed and/or stored. A circuit arrangement for implementing the method is also provided.

Abstract: A method begins by a processing module dispersed storage error encoding data to produce a plurality of sets of encoded data slices in accordance with dispersed storage error coding parameters. The method continues with the processing module determining a plurality of sets of slice names corresponding to the plurality of sets of encoded data slices. The method continues with the processing module determining integrity information for the plurality of sets of slice names and sending the plurality of sets of encoded data slices, the plurality of sets of slice names, and the integrity information to a dispersed storage network memory for storage therein.

Abstract: Protection of access information in wireless communications is achieved by transmitting access information related to configuration to a terminal, receiving a result of a countermeasure procedure performed by the terminal, deciding whether the configuration is correct or not based on the received result, and if not correct, allowing the terminal to receive access information, or if correct, performing the configuration.

Abstract: A method for controlling power consumption of an iterative decoder based on one or more criteria is described. The method may include performing iterative decoding on a demodulated signal to provide a decoded signal, determining whether the iterative decoding is suffering an impairment, and terminating the iterative decoding responsive to the determination of the impairment, otherwise continuing the iterative decoding to provide the decoded signal.

Abstract: Cyclic redundancy check (CRC) processing is applied to a received sequence of data blocks that are defined by respective sequences of sets of parallel data. For each data block, there is produced a sequence of syndromes that respectively correspond to the sets of parallel data within the data block. The final syndrome in the sequence of syndromes corresponds to all of the data in the data block. The time required for CRC processing can be reduced by concurrently producing first and second ones of the syndromes that respectively correspond to first and second ones of the sets that are respectively contained in first and second ones of the data blocks.

Abstract: A method of testing a processing includes performing a test of at least one logic block of a processor of a data processing system; receiving an interrupt; stopping the performing the test for the processor to respond to the interrupt, wherein the stopping the performing the test includes storing test data of the test to a memory prior to the processor responding to the interrupt; and after the processor responds to the interrupt, resuming performing the test, wherein the resuming performing the test includes retrieving the test data from the memory and using the retrieved test data for the resuming performing the test.

Abstract: Methods, systems, and computer-readable media to compare values of a bounded domain are disclosed. A particular method includes, for each value in a bounded domain, determining a corresponding set of allowable errors associated with the value. The sets of allowable errors are stored at a memory. The method includes determining a comparison score between a first value of the bounded domain and a second value of the bounded domain based on a comparison of a first set of allowable errors corresponding to the first value and a second set of allowable errors corresponding to the second value.

Abstract: The present disclosure describes a method, performed by a data processor comprising a cyclic redundancy check (CRC) module configured for calculating CRC remainders for encoded data and a comparator comprising a shift register, for making a cyclic redundancy check of an encoded data record of bit length L, in which at least A bits of the record represent content data and at least B bits represent check data. A system for performing a cyclic redundancy check is also described.

Abstract: A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time.

Abstract: Even if data includes a defect or an outlier in features thereof, the influence of the defect or the outlier of the features is suppressed to perform a highly precise abnormality detection, and data including high-dimensional features is processable to accomplish the highly stable detection of an abnormality. Disclosed is an abnormality detection system which detects abnormal data in a data sequence including data of multi-dimensional features, and the system includes storing or generating a generation distribution of features of the data and reference data indicative of normal data; obtaining, every piece of the data sequence, a probability that when features are virtually generated from the generation distribution, the features are nearer to the reference data than the features of each piece of the data; and taking the probability as a one-dimensional dissimilarity degree between each piece of the data and the reference data, thereby determining abnormal data.

Abstract: An apparatus includes a receiver, an error detection unit, and an acknowledgement unit. The receiver may receive frames of data from a transmitter unit of a second apparatus via a first communication path. The error detection unit may detect data errors in the frames of data received via the first communication path. The acknowledgment unit may maintain an acknowledgement indicator indicative of whether frames received by the apparatus are error free. In response to the error detection unit detecting an error, the acknowledgement unit may indicate an error condition exists by freezing a value of the acknowledgement indicator, or alternatively the acknowledgement unit may set a current value of the acknowledgement indicator to a predetermined error value. Further, the apparatus may successively convey values of the acknowledgement indicator to the second apparatus via a second communication path while the apparatus is receiving frames.

Abstract: A method and apparatus are provided for facilitating access from a control system to the memory of a processor across two buses, one of which acts as a bottleneck to communication between the control system and the processor. A bridge between the two buses acts as an intermediary. The control system issues simple diagnosis and data loading verification commands across a slow bus to the bridge. The bridge then performs the data intensive tasks by communicating with the processor through a faster bus. The bridge writes and reads data to the processor, and generates checksums of the written and read data. The bridge then returns status information to the control system indicative of the comparison of the checksums. In the case of memory diagnosis, the control system need only issue a simple command to the bridge through the slower, which then diagnoses the memory through the fast bus by writing and reading data, and returns a status to the control system through the slow bus.

Abstract: A data slicer includes an error bit predictor, a DC level compensator, a co-channel detector, and an output device. The data slicer generates four bytes according to four slicing levels respectively. The four slicing levels are a DC level, a level generated by adding a predetermined offset to the DC level, a level generated by subtracting the predetermined offset from the DC level, and a compensated level generated by the DC level compensator. The co-channel detector determines if the compensated level has the co-channel interference. The output device generates an output byte according to indication signals generated by the co-channel detector and the error bit predictor and the parity check of the four bytes.

Abstract: When a data write request to a disk drive 210 is received from a host computer 20, a first error detecting code of write data to be written to the disk drive 210 in response to the data write request is generated and stored, write processing of the write data to the disk drive 210 is executed, whether or not response time as time required for the write processing exceeds a predetermined threshold value is determined, data stored in a sector as a writing destination of the write data is read from the sector when the response time exceeds the threshold value, a second error detecting code of the read data is generated, and when the first error detecting code and the second error detecting code are compared with each other and the two codes do not coincide with each other, a signal indicating that the write processing is not normally performed is generated.

Abstract: A method and apparatus for determining the reliability of decoded data in a communication system. The method includes calculating a total sum of absolute values corresponding to Log Likelihood Ratio (LLR) values of received data, generating a first value obtained by multiplying the total sum of the absolute values by a predetermined threshold value, performing iterative decoding with respect to the LLR values of the received data, generating a survived path metric value having a maximum value among all path metric values as a decoded result and generating decoded data, comparing the first value with the survived path metric value, and determining whether the decoded data has suitable reliability according to the compared result.

Abstract: A test circuit of a semiconductor memory device for performing a test in cooperation with a tester having a plurality of input/output pins connected to a plurality of input/output lines. The test circuit may include a first comparing unit adapted to compare, on a bit-by-bit basis, read data that may be read from memory cells corresponding to an address with expected data, and to output the comparison results as first comparison signals, a second comparing unit adapted to perform a logic operation on the first comparison signals and to generate a flag signal when determining a failure of at least one of the memory cells on the basis of the operation result, and a storage unit adapted to store the first comparison signals in response to the flag signal.

Abstract: An apparatus and method for assessing image quality in real-time in consideration of both a coding error generated in an image processing process and a packet error generated in an image transmission process are provided. The apparatus for assessing image quality in real-time includes: an image quality measurement unit measuring image degradation generated in processing an image; a packet degradation detection unit detecting a packet error generated in transmitting the image; and final outcome drawing unit finally assessing the quality of the image in consideration of both a degradation degree of the image measured by the image quality measurement unit and the packet error measured by the packet degradation detection unit.

Abstract: A blanking primitive masking circuit has a detection and handling circuit that receives data containing blanking primitives. The detection and handling circuit generates a dynamic blanking signal when blanking primitives are detected. The received data is delayed and provided to a pattern detector that generates a synchronization signal provided to a memory and a phase sync signal provided to the detection and handling circuit and to a comparator. The comparator receives reference data from the memory, the delayed data, and the dynamic blanking signal. The comparator compares the reference data with the delayed data and generates bit error outputs from mismatched reference data bits and delayed data bits when the dynamic blanking signal from the detection and handling circuit is absent and suppressing the generation bit error outputs when the blanking primitive are in the delay data and the dynamic blanking signal is present.

Abstract: Transforming portions of a message to a destination via a communication protocol. A message is received. It is detected whether the received message includes an encoded envelope. The encoded envelope includes a stack defining parameters including information for handling the received message in an original format. If the received message includes the encoded envelope, the defined parameters are transformed to coded parameters in a common format. The coded parameters express the same information for handling the received message in the communication protocol. The encoded envelope is encapsulated in the received message, and the received message in the common format is delivered to the destination. If the received message does not include an encoded envelope, coded parameters are generated in the common format for the received message by encoding addressing information from the received message. The received message having the coded parameters in the common format is delivered to the destination.

Abstract: A third party that performs data stream computation is requested to return not only the solution to the computation, but also “annotations” to the original data stream. The annotations are then used by the data owner (in actuality, a “verifier” associated with the data owner) to check the results of the third party's computations. As implemented, the verifier combines the annotations with the original data, performs some computations, and is then assured of the correctness of the provided solution. The cost of verification is significantly lower to the data owner than the cost of fully processing the data “in house”.

Abstract: A lighting system controller is provided that is configured to automatically synchronize a lighting controller with a centralized configuration. In a particular example, this automatic synchronization activity may include modifying the configuration of the lighting controller to match configuration information stored locally on the lighting system controller. Conversely, this automatic synchronization activity may include modifying the locally stored configuration information to match the current configuration of the lighting controller. In some examples, the lighting system controller is configured to use cyclic redundancy checks when determining whether to modify configuration information.

Abstract: A non-volatile memory device includes a block remapping system that offsets an input block address by the addresses of non-functional blocks to provide an output block address that is used to address the memory device. The system generates the output block addresses by, in effect, adding to the input block address the addresses of all non-functional blocks of memory that are between an initial address and the output block address. The system performs this function be comparing the input block address to the address of any defective block. If the address of the defective block is less than or equal to the input block address, the addresses of all defective blocks starting at the block address are added to the input block address. The system then iteratively performs this process using each output block address generated by the system in place of the input block address.

Abstract: Systems and methods for analyzing and affecting manifestations of subtle energy resonance are provided. A memory array associated with a transducer is read and stored in a memory of an analysis device. The memory array is then exposed to an energy environment which causes changes to the memory array. A second reading of the memory array indicates the changes to the memory array as compared to the first reading. The detected changes are analyzed and used to generate an energy signature and a report concerning any combination of the changes, the rate of changes, and the generated energy signature. The energy data concerns subtle energy in a designated energy environment which may include one or more animate or inanimate crystalline resonators. Tuning of a generator allows for manipulation of cell resonance, which may be used for research or in order to produce a desired resonance.

Abstract: A method of detecting a fault including generating at least one blinded data value based on at least one input value and at least one blinding parameter selected from a plurality of blinding parameters generating a first signature based on said at least one blinded data value; selecting, from a memory storing a plurality of reference signatures, one or more reference signatures and comparing said first signature with said one or more reference signatures in order to detect a fault.

Abstract: A fault detection apparatus comprises a signal translation stage having an input arranged to receive an input waveform derived from a signal for a capacitive load. The signal translation stage is arranged to generate a translated output signal representative of at least an aspect of the input waveform. The apparatus also comprises a detection stage arranged to receive the translated output signal from the signal translation stage and analyse a first part and a second part of the translated output signal respectively corresponding to a first step function and a second step function, the first and second step functions being opposite in direction of transition. The analysis performed by the detection stage is a comparison of the first and second parts of the translated output signal respectively with an expected first part and an expected second part of the translated output signal.

Abstract: A method for checking reading errors of a memory includes receiving a first data fragment and accordingly generating a first ECC and a first count index; writing the first data fragment, the first ECC and the first count index into a memory; reading the first data fragment from the memory as a second data fragment, generating a second ECC and second count index according to the second data fragment; determining whether the first count index and second count index are equal; determining whether the first ECC and the second ECC are equal; and outputting the second data fragment when the first count index is equal to the second count index and the first ECC is equal to the second ECC.

Abstract: A data receiving method for an electronic system including a host apparatus and a target apparatus, wherein the host apparatus transmits at least one request to the target apparatus for requesting at least one desired data, and the target apparatus transmits the desired data to the host apparatus according to the request. The data receiving method comprises: (a) generating a statistic value according to a number of the requests; (b) varying the statistic value according to a number of the desired data; and (c) determining whether data received by the host apparatus is the desired data corresponding to the request or not according to the static value, to thereby determine whether the data received by the host apparatus is stored to the host apparatus or not.

Abstract: An optimum pathway to data stored on a data storage system having N storage devices and more than N pathways is determined in response to a read request for the data. A sorter separates the read request into an appropriate segment size for sending to the storage devices of the data storage system. An assigner generates the set of read permutations satisfying the read request. A read permutation is selected based on a metric. A collector receives the requested data from the N storage devices in response to the selected read permutation being sent to the storage devices.

Abstract: A method of processing signal data comprises receiving signal data, calculating a first k-th moment from the signal data based on a first number of samples N1, calculating a second k-th moment from the signal data based on a second number of samples N2, the first number N1 being different than the second number N2, calculating a combined error, the combined error being a function of the first and second k-th moments, classifying a data region of the signal data as flat if the combined error is below or equal to a threshold curve in the data region, and classifying a data region of the signal data as non-flat if the combined error is higher than the threshold curve in the data region.

Abstract: In response to a disagreement between a previously generated check code associated with previously programmed data bits and a more recently generated check code generated in response to a read command, the comparison process is changed, between i) a value representing accessed data and ii) a reference applied to such accesses to distinguish between logical levels. For example, the ratio of resistances characterizing input circuits of a sense amplifier and/or the read bias arrangement and/or a read reference of a memory integrated circuit is/are changed.

Abstract: A field programmable device is disclosed, including a plurality of logic blocks; a plurality of connections connecting the logic blocks; configuration circuitry for outputting configuration data for programming the field programmable device, the configuration circuitry providing at least one pair of outputs; and error detection circuitry for comparing the outputs to determine if there has been a configuration error.