Abstract: A control channel may be used to transmit control information, such as Downlink Control Information (DCI), to a mobile device from a network component, such as a base station or a base node. The mobile device may use a blind decoding scheme to detect DCIs. A DCI may be falsely detected by the mobile device. According to some embodiments, data that has been decoded by a blind decoder, from buffer data for a candidate control channel, is re-encoded. The re-encoded data is compared to buffer data for the control channel. The decoded data is treated as control information dependent on the comparison of the re-encoded data with the buffer data. In some embodiments, comparing the re-encoded data to the buffer data includes generating a metric as a function of a degree of similarity between the re-encoded data and the buffer data. The metric may be compared to a threshold.

Abstract: There is provided with an apparatus including: a receiving section which receives a frame including an error detection code from a network; an error detecting section which performs error detection on the frame received by the receiving section based on the error detection code; a data storage which stores data in a predetermined field of the frame as replacement data in a case where an error is not detected in the frame; a data selecting section which selects the replacement data from the data storage in a case where an error is detected in the frame; and a frame generating section which generates a frame in which data in the predetermined field of the frame is replaced with the replacement data selected by the data selecting section in the case where an error is detected in the frame; wherein the error detecting section performs error detection on the generated frame.

Abstract: A method, system and device for monitoring error code of CPRI link are disclosed. The method comprises: a CPRI link data transmitting end forming data to be transmitted into frames, outputting data, and calculating to obtain FCS of each frame; the CPRI link data transmitting end adds FCS of a former frame into FCS field of a current frame when forming frame; a CPRI link data receiving end splitting frame of received frame data to obtain FCS of the former frame carried in the current frame, calculating received frame data to obtain FCS of the current frame, caching FCS of the current frame, comparing FCS of the former frame which is carried in the current frame with cached FCS of the former frame, and judging CPRI link has error codes if the comparison result is inconsistent. Error code condition of CPRI link can be monitored without influencing normal service operation.

Abstract: A system for serially transmitting vital data includes first and second processors to determine first and second data, a serial communication apparatus to input third data and output serial data based upon the third data, and a memory having first and second ports accessible by the first and second processors, a first memory writable by the first processor and readable by the second processor, and a second memory writable by the second processor and readable by the first processor. The first and second processors store the first and second data in the first and second memories, cooperatively agree that the first data corresponds to the second data, and responsively cause the apparatus to employ: one of the first and second data as the third data, or parts of the first and second data as the third data, and output the serial data based upon the third data.

Abstract: System and method for testing jitter tolerance by using a built-in jitter modulation circuit is disclosed. An embodiment comprises a jitter modulation circuit, a transmitter, a receiver and a data comparison unit. The jitter modulation circuit includes a plurality of data latches, a phase-select block and a multi-phase clock generator. The multi-phase clock generator is capable of generating a plurality of signals having different phase shifts wherein one signal having a phase shift from the system clock signal is selected by the phase-select block. The selected signal alters the data by injecting jitter through a plurality of data latches. The jitter-contaminated data is transmitted to a data comparison unit through a transmitter and a receiver. The on-chip test circuit compares the jitter-contaminated data with the original data and calculates the bit error rate so as to determine whether the jitter tolerance of this semiconductor device satisfies the specification.

Abstract: Technology for testing a target recognition, analysis, and tracking system is provided. A searchable repository of recorded and synthesized depth clips and associated ground truth tracking data is provided. Data in the repository is used by one or more processing devices each including at least one instance of a target recognition, analysis, and tracking pipeline to analyze performance of the tracking pipeline. An analysis engine provides at least a subset of the searchable set responsive to a request to test the pipeline and receives tracking data output from the pipeline on the at least subset of the searchable set. A report generator outputs an analysis of the tracking data relative to the ground truth in the at least subset to provide an output of the error relative to the ground truth.

Abstract: An apparatus, system, and method are disclosed for storing information in a storage device that includes multi-level memory cells. The method involves storing data that is written to the storage device in the LSBs of the multi-level memory cells, and storing audit data in the MSBs of the multi-level memory cells. The audit data can be read separately from the data and used to determine whether or not there has been any unintended drift between states in the multi-level cells. The audit data may be used to correct data when the errors in the data are too numerous to be corrected using error correction code (ECC). The audit data may also be used to monitor the general health of the storage device. The monitoring process may run as a background process on the storage device. The storage device may transition the multi-level memory cells to operate as single-level memory cells.

Abstract: A method, system and apparatus of lossy compression technique for video encoder bandwidth reduction using compression error data are disclosed. In one embodiment, a method includes storing an error data from a compression of an original reference data in an off-chip memory, accessing the error data during a motion compensation operation, and performing the motion compensation operation by applying the error data through an algorithm (e.g., determined by the method of storing the error data). The method may include generating a predicted frame in the motion compensation operation using a motion vector and an on-chip video data. In addition, the method may include determining the error data as a difference between a compressed reference data (e.g., is created by compressing the original reference data) and an original reference data (e.g., reconstructed from a prior predicted frame and a decompressed encoder data).

Abstract: An apparatus and method for detecting data bit edge in a meander encoded information bit from a GLONASS (Global Navigation Satellite System). The method includes receiving meander encoded data samples from a meander encoded information bit, and computing a set of accumulated values corresponding to a hypothesized bit edge phase. The process of computing an accumulated value of the set of accumulated values includes providing a toggled subset of the meander encoded data samples, and integrating the toggled subset of the meander encoded data samples with an un-toggled subset of the meander encoded data samples to produce the accumulated value. The method also includes selecting a best hypothesis from the set of hypotheses corresponding to a maximum value of the set of accumulated values, where the best hypothesis represents the data bit edge.

Abstract: An estimating unit includes: an error detecting unit which detects an error among a plurality of frames received from an interface unit of a transmission device; a request sending unit which produces a first frame including a data collection request for requesting data collection upon the error detecting unit detecting the error, and which sends the first frame to the interface unit; an extracting unit which extracts, from the plurality of frames received from the interface unit, a second frame including the error detected by the error detecting unit and a third frame including a reply of the interface unit to the data collection request; and a saving unit in which the second frame extracted by the extracting unit is saved.

Abstract: A test generator and methods for generating tests from a hybrid diagram are provided. A hybrid diagram is a diagram that primarily uses one higher-level semantic notation with portions utilizing one or more secondary higher-level semantic notations. Example higher-level semantic notations are statechart notation and data-flow notation. A test generator processes the hybrid diagram without reducing the higher-level semantic constructs to lower-level semantic constructs. The test generator generates test-generation templates as needed based on the higher-level semantic model used in the diagram. The test generator uses the test-generation templates to generate tests for a system-performing device specified by the diagram. The generated tests may be executed automatically by a test driver or manually by a human tester.

Abstract: A method of determining frame loss between two management points (C, D) in an Ethernet network, in which the said management points each transmit frames to each other and each of the said two management points transmits in regular intervals to the other measurement messages which contain current counts of frames transmitted and received by the respective transmitting management point. At least one of the said two management points responds to a received management message to compute from counts of actual packets transmitted and/or received by a given one of the management points the frame loss at said given management point. At least one of the management points computes the said frame loss only once in a measurement interval which consists of a multiplicity of said regular intervals and employs in the computation the counts indicated by the measurement message most recently received by said one of the management points.

Abstract: A clock and data recovery device recovers data from a sequential stream of data that includes bursts of data separated by gaps. Each burst of data arrives with its own phase and with its own deviation from a nominal frequency. The bursts of data begin with a preamble that is utilized to determine the timing of the burst. The clock and data recovery device determines the timing of a burst of data using signals from one or more demultiplexers or samplers. At the start of each burst of data, sampled input signals are analyzed by an edge detector to determine a sample phase for the burst. A selector utilizes the sample phase determined by the edge detector to choose which of the sampled input signals to use to produce output data signals from the clock and data recovery device.

Abstract: Control circuitry is coupled between an error event output and a data input of a pseudorandom binary sequence (PRBS) checker. The control circuitry is configured to switch between a first operating state in which a received PRBS signal is applied to the data input of the PRBS checker and a second operating state in which an error signal is applied to the data input of the PRBS checker, responsive to detection of a designated condition of the PRBS checker. In an illustrative embodiment, the designated condition is an end-of-test condition indicating that the PRBS checker has completed a test involving the received PRBS signal.

Abstract: A computer-implemented method for focusing product testing based on areas of change within the product is described. A link between resource files of a product and test cases associated with the product is created. The resource files of a first build of the product are compared with the resource files of a second build of the product. A report that comprises which resource files changed between the first build of the product and the second build of the product is generated. The resource files that have changed and the test cases linked to the changed resource files are displayed. The test cases linked to the changed resource files are executed.

Abstract: A method of error control in a wireless access system is disclosed. More particularly, a method of error control using a random liner coding method is disclosed. A method of error control in a wireless access system comprises receiving code blocks generated as data blocks included in a data block set are randomly linear-coded; decoding a predetermined number of code blocks to a first data block set, wherein the predetermined number of code blocks are selected from the code blocks; replacing one or more code blocks among the predetermined number of code blocks with code blocks other than the predetermined number of code blocks selected from the code blocks and decoding them to a second data block set; and comparing the first data block set with the second data block set.

Abstract: According to one embodiment, a semiconductor integrated device which stores secret data and is capable of operating in a test mode in which a scan test with respect to an internal circuit is executed, the semiconductor integrated device comprises a mode signal receiving module configured to receive a scan mode signal designating the test mode, a mask module configured to mask the secret data when the mode signal receiving module receives the scan mode signal, and an error detection module configured to detect presence or absence of error in the secret data and to store detection result in a first flip-flop.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a media defect detector circuit. The media defect detector circuit is operable to compare a data input derived from a medium against at least a first defect level to yield a first level output, and a second defect level to yield a second level output; and provide a combination of the first level output and the second level output as a defect quality output. A value of the defect quality output corresponds to a likelihood of a defect of the medium.

Abstract: Some embodiments include apparatus and methods to prevent at least one of misidentifying and ignoring multiple-bit errors if the multiple-bit errors include a plurality of erroneous data bits that belong to only one specific group of a plurality of groups of data bits and if none of the other groups of the plurality of groups have errors.

Abstract: A method of detecting communications errors by coding messages as pictures. A communications method useable to safely communicate a message or a signal from a first safety approved entity to a second safety approved entity via a third, non-safety approved entity including that each command is sent with the aid of a command message from the first to the second entity, an acknowledge message from the second to the first entity, and a go-ahead message from the first to the second entity.

Abstract: A sending part sends a data generated by a second device from the second device to a first device. A data collating part collates the data sent from the sending part with a data generated by the first device, and determines that it is abnormal when a mismatch between these data occurs. Thus, a data generated by the first device is collated with a data generated by the second device and when a mismatch between these data occurs, it is determined that it is abnormal, so that abnormality can be detected surely.

Abstract: Detection of faults in a transmitted signal stream occurs by recovering, from the information stream, a water mark embedded in the stream prior to transmission. The embedded watermark has data characteristic of stream quality. Thereafter, the at least one watermark property is analyzed to detect faults in the received information stream.

Abstract: A method for checking reading errors of a memory includes the following steps. A first data fragment is received. A first count index according to the first data fragment is generated, wherein the first count index is corresponding to a quantity of one kind of binary value in the first data fragment. The first data fragment is written into the memory. The first data fragment is read from the memory as a second data fragment. A second count index is generated according to the second data fragment. The first count index is compared with the second count index.

Abstract: A reading method for a memory device with error-correcting encoding envisages the steps of: carrying out a first reading of a plurality of memory locations (A0, A1, . . . , ALS-1) to generate a first recovered string (S1), and performing a first decoding attempt using the first recovered string (S1). When the first decoding attempt fails, the memory locations are read at least one second time, and at least one second recovered string (S2-SN) is generated. On the basis of a comparison between the first recovered string (S1) and the second recovered string (S2-SN), a modified string (SM) is generated, in which erasures (X) are located, and at least one second decoding attempt is carried out using the modified string (SM).

Abstract: A test and measurement instrument including an input configured to receive a signal and output digitized data; a memory configured to store reference digitized data including a reference sequence; a pattern detector configured to detect the reference sequence in the digitized data and generate a synchronization signal in response; a memory controller configured to cause the memory to output the reference digitized data in response to the synchronization signal; and a comparator configured to compare the reference digitized data output from the memory to the digitized data.

Abstract: A network device and a method for controlling the same. The device and method each performed the operations of transforming an input signal so as to allow the input signal to be divided according to frequency bands and resolutions, comparing the transformed input signal with abnormal signal information stored in an abnormal signal database (DB), and determining whether the input signal is a normal signal. When the input signal is a normal signal, the network and method each perform the operation of delivering the transformed input signal to a codec.

Abstract: Various embodiments of the present invention provide systems and methods for media defect detection. As an example, a data processing circuit is disclosed that includes a defect detector circuit and a comparator circuit. The defect detector circuit is operable to calculate a correlation value combining at least three of a data input derived from a medium, a detector extrinsic output, a detector intrinsic output and a decoder output. The comparator circuit is operable to compare the correlation value to a threshold value and to assert a media defect indicator when the correlation value is less than the threshold value.

Abstract: This invention has as its object to attain strong security and to implement network solutions with high convenience and simplicity with low cost upon providing Web services. To this end, an information processing apparatus according to this invention has the following arrangement.

Abstract: A data transmission system includes at least one transmission line. A sender is configured to send data frames to the at least one transmission line and a recipient is configured to receive the data frames from the at least one transmission line. The sender and the recipient are both configured to determine a check sum based on a plurality of corresponding data frames that are sent to and, respectively, received from the at least one transmission line. A check sum comparing unit is configured to receive and to compare the check sum determined by the sender and the corresponding check sum determined by the recipient. The check sum comparing unit is also configured to signal a transmission error or initiate a safety function when the check sums compared are not equal.

Abstract: An apparatus, system, and method are disclosed for storing information in a storage device that includes multi-level memory cells. The method involves storing data that is written to the storage device in the LSBs of the multi-level memory cells, and storing audit data in the MSBs of the multi-level memory cells. The audit data can be read separately from the data and used to determine whether or not there has been any unintended drift between states in the multi-level cells. The audit data may be used to correct data when the errors in the data are too numerous to be corrected using error correction code (ECC). The audit data may also be used to monitor the general health of the storage device. The monitoring process may run as a background process on the storage device. The storage device may transition the multi-level memory cells to operate as single-level memory cells.

Abstract: A failure is detected immediately and certainly, and continuation of processing in an unstable state is prevented. A first error detection code is generated from first information which is output as a result of execution of a predetermined program conducted by a first processor. A second error detection code is generated from second information which is output as a result of execution of the program conducted by a second processor which is configured so as to output the same computation result as that of the first processor. It is detected whether the first information is the same as the second information, and it is detected whether the first error detection code is the same as the second error detection code. Writing the first information or the second information into a main memory is controlled on the basis of a result of the detection.

Abstract: When a data write request to a disk drive 210 is received from a host computer 20, a first error detecting code of write data to be written to the disk drive 210 in response to the data write request is generated and stored, write processing of the write data to the disk drive 210 is executed, whether or not response time as time required for the write processing exceeds a predetermined threshold value is determined, data stored in a sector as a writing destination of the write data is read from the sector when the response time exceeds the threshold value, a second error detecting code of the read data is generated, and when the first error detecting code and the second error detecting code are compared with each other and the two codes do not coincide with each other, a signal indicating that the write processing is not normally performed is generated.

Abstract: A signal control circuit and a signal control apparatus that can reduce processing time and can send or receive correct data with reliability. When a data generation block outputs data, a data judgment block judges the number of changed bits by comparing each bit of the data output in the preceding session with the corresponding bit of the data to be sent in the current session and outputs position information indicating the position of each changed bit and the number of changed bits when the number of changed bits has reached a predetermined level. An output control block keeps a time period for stabilizing the change in value of the bit corresponding to the position information when the data is output, and directs a data storage block to send the value of the bit corresponding to the position information to an external circuit after the kept period has passed.

Abstract: A patrol function performed in a storage controller connected to a flash memory storage module. The function causes selected areas of the flash storage to be read for purposes of detecting and correcting errors.

Abstract: An apparatus for determining information in order to temporally align first and second information signals, each including one or several information values for successive sampling times, the apparatus including a characteristic extractor for extracting a characteristic per sampling time or per subsequence of sampling times from the first information signal within a first search pattern to obtain a first characteristic curve, and for extracting the characteristic per sampling time or per subsequence of sampling times from the second information signal within a second search pattern to obtain a second characteristic curve and a determiner for determining the information for temporal alignment based on similarities between the first and second characteristic curves of the characteristic by means of a first search for a search pattern from one of the first and second characteristic curves of the characteristic within the other of the first and second characteristic curves of the characteristic.

Abstract: Systems, methods, and computer program products that can be used concurrently or alternatively to detect errors in data as well as to protect access to data are provided. Embodiments enable a coherent data set (CDS) which is a data set guaranteed to be genuine and error-free at run-time. Embodiments provide systems, methods, and computer program programs to create a CDS, identify a CDS, and verify the coherency of a data set purported to be a CDS. Embodiments further enable privileged functions which are functions that can only be accessed by a restricted set of other privileged functions. Embodiments provide systems, methods, and computer program products to create, identify, and protect access to privileged functions.

Abstract: The invention relates to a microprocessor system (60) for controlling and/or regulating at least partly security-critical processes, which system comprises two central processing units (1, 2) integrated into a chip housing, a first and a second bus system, at least one complete memory (7) on the first bus system, and check data in one or more check data memories, said data being related to data of the memory in the first bus system. The check data memory is smaller than the complete memory. The bus systems comprise comparative and/or driver components which facilitate data exchange and/or comparison of data between the two bus systems. The one or more check data memories are arranged on the first bus system. On the second bus system, neither a check data memory nor a memory safeguarding data of the memory on the first bus is used. The invention also relates to the use of the inventive microprocessor system in automotive control devices.

Abstract: A semiconductor device including an electronic circuit, a memory, and an error detecting module. The electronic circuit is configured to receive an input signal having been generated by a test module, and generate an output signal based on the input signal. The memory is configured to store a predetermined output value that is expected to be output from the electronic circuit based on the electronic receiving the input signal, wherein the predetermined output value is stored in the memory prior to the input signal being generated by the test module. The error detecting module is configured to (i) generate a sample value of the output signal, (ii) compare the sample value of the output signal to the predetermined output value stored in the memory, and (iii) generate a result signal that indicates whether the sample value of the output signal matches the predetermined output value.

Abstract: A data processing device acquires a first parameter value of a hardware component, and calculates a first prediction value of the first parameter using a prediction algorithm. If a difference of the first prediction value and the first parameter falls within a deviation range, the first parameter value is determined as a real value and is stored. Otherwise, the device acquires a second parameter value of the hardware component that follows the first parameter value, and calculates a second prediction value of the second parameter value. If a difference between the second prediction value and the second parameter value falls with a second deviation range, the first parameter value is determined as a real value and is stored. Otherwise, the first parameter value is determined as a false value and is abandoned.

Abstract: An integrity monitoring system (IMS) monitors data upload errors, internal data processing errors, clock faults, and transmit signal distortions in a transmitter system. The IMS includes a receiver with an A/D converter that under-samples a multi-band RF signal to produce a composite, aliased IF digital signal. Individual signals are extracted from the composite signal via correlation with the appropriate spreading code. The resulting signals are evaluated to determine whether any signal distortion is present in the RF signals being transmitted, and data is extracted from the signals to perform checks of data uploaded to the transmitter system and data present in the transmitted RF signals that was generated within the transmitter system. The IMS also checks for clock faults in the transmitter system without requiring an independent timing reference by using clock phase information provided by the transmitter system's time keeping system.

Abstract: Technology for testing a target recognition, analysis, and tracking system is provided. A searchable repository of recorded and synthesized depth clips and associated ground truth tracking data is provided. Data in the repository is used by one or more processing devices each including at least one instance of a target recognition, analysis, and tracking pipeline to analyze performance of the tracking pipeline. An analysis engine provides at least a subset of the searchable set responsive to a request to test the pipeline and receives tracking data output from the pipeline on the at least subset of the searchable set. A report generator outputs an analysis of the tracking data relative to the ground truth in the at least subset to provide an output of the error relative to the ground truth.

Abstract: A technology in which it is detected whether errors occur in a packet received from a satellite terminal device, a modulation and coding (MODCOD) value is calculated according to a result of the detection and the calculated MODCOD value is transmitted to the satellite terminal device, so that pack loss is reduced based on the yield of actual traffic when the satellite terminal device transmits a return link packet. A plurality of return link packets are received from the satellite terminal device. An occurrence of a packet error is detected by generating a first return link packet by sequentially assembling the plurality of return link packets and performing a comparison analysis by comparing the first return link packet with a second return link packet that is newly received.

Abstract: A processor on a delegator receives an input upon which an expensive function is to be evaluated. The delegator incorporates the input into a request to perform a task that is different from evaluating the function. When the task is performed, it provides a secondary result that is observable by the delegator. The secondary result is different from an answer to the expensive function and can be verified by the delegator with less computational expense than evaluation of the expensive function. The task can be performed by the server only after the server has verifiably evaluated the function based on the input. Request data, that is indicative of the request to perform a task with the input incorporated therein is transmitted to the server for performance of the task. The delegator then receives a returned result from the server indicative of the server performing the task.

Abstract: Disclosed is a method and system for validating a data packet by a network processor supporting a first network protocol and a second network protocol and utilizing shared hardware. The network processor receives a data packet; identifies a network packet protocol for the data packet; and processes the data packet according to the network packet protocol comprising: updating a first register with a first partial packet length specific to the first network protocol; updating a second register with a second partial packet length specific to the second network protocol; and updating a third register with a first checksum computed from fields independent of the network protocol. The system produces a second checksum utilizing a function that combines values from the first register, the second register, and the third register. The system validates the data packet by comparing the data packet checksum to the second checksum.

Abstract: A generalized hardware architecture that supports built-in self testing (BIST) for a range of different computer memory configurations and a generalized BIST algorithm can be compiled, based on specified configuration characteristics (e.g., the number of write ports, the number of read ports, the number of entries, and the number of bits per entry in the computer memory), to generate the hardware design for a particular computer memory system. In one embodiment, the generalized hardware architecture includes a multiplexer block that enables a single BIST comparator to be multiplexed for use in performing BIST testing via different read ports of the computer memory.

Abstract: A method of creating backup files having less redundancy. The method creates a backup file by creating an overhead segment for each file that is to be backed up and creating a data segment containing the data that is to be backed up for each file. After creating the overhead segment and the data segment, the overhead segment is placed into an overhead stream data segment is stored in memory. The overhead segment is also positioned in the overhead stream with a pointer that identifies the data segment within the memory. For backups of subsequent servers or the same server at a later time, the backup software will create a separate overhead stream. However, a plurality of overhead streams may contain pointers to the same data segments such that redundant data segments do not need to be stored in a backup server.

Abstract: A data buffer control unit obtains data from a cache according to a command retained in a command queue retaining a command(s) for reading data from the cache, and a magic ID generation circuit generates a magic ID. The data buffer control unit assigns the data obtained from the cache with the magic ID, writes the assigned data to a data buffer, and returns the magic ID to the command queue. When the data buffer control unit receives a read request and the magic ID which is returned to the command queue, it reads the data, which corresponds to the read request, from the command queue and compares the magic ID assigned in the read data and the received magic ID. If the two magic IDs compared by the data buffer control unit are not identical, a packet generator detects an error and reports the error to a host.

Abstract: Automatic detection of errors among different formatted sound tracks of the same language on a motion picture film stock can be achieved by first acquiring successive audio segments from each of the sound tracks. During a time window of prescribed duration, the audio of each different formatted track undergoes analysis to yield a numeric value. The successive analysis of the audio continues until no further audio exists for analysis. The resultant collection of numeric values undergoes formatting into a numeric file for comparison against a reference file representing audio obtained from a particular source, such as originally recorded material, a sound print, or a duplicated copy of a sound film. If the difference between a formatted numerical file and the reference file exceeds a threshold value, then an error exists in that formatted sound track, and an operator can take appropriate action.

Abstract: A method for comparing data in a computer system having at least two execution units, the comparison of the data taking place in a comparison unit and each execution unit processing input data and generating output data, wherein one execution unit specifies to the comparison unit that the next piece of output data is to be compared to a piece of output data of the at least second execution unit, and thereupon a comparison of the at least two output data takes place.

Abstract: A method for checking reading errors of a memory includes the following steps. A first data fragment is received. A first count index according to the first data fragment is generated, wherein the first count index is corresponding to a quantity of one kind of binary value in the first data fragment. The first data fragment is written into the memory. The first data fragment is read from the memory as a second data fragment. A second count index is generated according to the second data fragment. The first count index is compared with the second count index.