Abstract: An automatic data recovery circuit includes a register, an error detection unit and a data recovery unit. The register stores a register data including an input data and a remainder data generated by a cyclic redundancy check calculation on the input data using a predefined generation polynomial. The error detection unit performs a modular calculation on the register data stored in the register using the predefined generation polynomial to generate an error detection signal indicating whether an error is detected in the register data stored in the register. The data recovery unit recovers the input data when an error is detected in the input data based on the error detection signal and a comparison data generated by comparing the input data stored in the register with a reference voltage using a capacitor.

Abstract: The present disclosure generally pertains to systems and methods for updating script images in wireless sensor networks. In one exemplary embodiment, a system has logic that is configured to display a list of nodes of a wireless sensor network. The logic is further configured to display a script source of a first script image stored at one of the nodes in response to a selection of the one node from the displayed list of nodes. The logic is also configured to modify the script source based on user input and to convert the modified script source to a second script image. The logic is configured to transmit at least one remote procedure call through the wireless sensor network to the one node. The one node is configured to write the second script image in memory of the one node in response to the at least one remote procedure call.

Abstract: In this parity data generating circuit, a Galois field multiplying calculation is realized by performing data conversion by index table information generated from a Galois field multiplying table so that data for RAID6 are generated. A table check circuit inspects nonconformity of the index table information in advance by using results in which the Galois field multiplying table is indexed from different directions constructed by the longitudinal direction and the transversal direction. Data and parity for making the multiplying calculation are decomposed into plural data and parities by using this table check circuit, and index table information different from each other are allocated to these data and parities. Thus, a longitudinal index table making circuit and a transversal index table making circuit themselves are checked.

Abstract: A data processing system has cache circuitry having a plurality of ways. Mirroring control logic indicates a mirrored way pair and a non-mirrored way of the plurality of ways. The mirrored way pair has first and second ways wherein the second way is configured to store cache data fields redundant to cache data fields of the first way. In one form, comparison logic, in response to an address hitting in the first way or the second way within the mirrored way pair, performs a bit comparison between cache data from the first way addressed by an index portion of the address with cache data from the second way addressed by the index portion of the address to provide a bit parity error signal. In another form, allocation logic uses a portion of the address and line locking information to determine whether a mirrored or non-mirrored way is selected for allocation.

Abstract: A method of stabilizing an identification series of bits by iteratively reading the identification series and logical OR'ing the identification series with a mask string after each read of the identification series. This produces a mask string having a first value in all positions of the mask string where bits in the identification series have never changed value during all of the readings of the identification series, representing stable bits, and a second value in all positions of the mask string where bits in the identification series have changed value during at least one of the readings of the identification series, representing unstable bits. The number of the unstable bits in the mask string having the second value is counted, and a method failure code is selectively reported when the number of unstable bits exceeds a maximum allowable number of unstable bits. An identification string is produced from the stable bits, and an identification code is calculated from the identification string.

Abstract: Systems and methods are described which allow the detection of gaps in a set of data. These systems and methods may include defining streams of data from a network topology, associating incoming data with one or more of these streams, and processing these streams. A gap may be detected by comparing the times of events in the stream. If a gap is detected remedial action may be taken, and processing of the streams temporarily halted. Processing of the streams may continue when data for a certain stream is received, or after the lapse of a certain period of time.

Abstract: A method begins by receiving at least a portion of a merchant master file. The method continues, for a merchant data file, by determining whether a corresponding merchant profile record exists within a merchant profile database. The method continues, when the corresponding merchant profile record exists in the merchant profile database, by comparing the merchant data file with the corresponding merchant profile record. The method continues, when an inconsistency exists between the corresponding merchant profile record and the merchant data file, by determining status of the merchant data file with respect to the at least a portion of the merchant master file. The method continues, when the status of the merchant data file is a first status level, by generating an inconsistency message that identifies the inconsistency.

Abstract: A system for analyzing an information system comprising a computer readable medium; and a set of computer readable instructions embodied in the computer readable medium for transmitting an audit application to a first store controller so that the audit application can generate audit data representing audit information from the first store controller, receiving audit data from the first store controller, transmitting an audit application to a second store controller so that the audit application can generate audit data representing audit information from the second store controller, receiving audit data from the second store controller, determining a comparison basis according to the audit information from the first store controller, comparing the audit date from the second store controller to the comparison basis, generating a set of comparison data resulting from the comparison, displaying items from the second store controller that are different from the comparison basis.

Abstract: According to the present invention, the outputs of the last scanning flip-flop circuits 12 included in scan chains 111 are compiled and compressed in an output compression circuit 112, a sum of the outputs from the scan chains 111 and an expected value written in an expected value storage circuit 113 from the outside are compared with each other in an expected value decision circuit 114, the sum being outputted from the output compression circuit 112, a pass/fail decision result obtained by the comparison can be outputted from an output terminal 116 of the expected value decision circuit 114 to the outside, and the decision result can be stored regardless of the reset of a system.

Abstract: A semiconductor device that includes a module under test that is integrated with the semiconductor device, that receives an input signal from a test module, and that provides an output signal to at least one output terminal based on the input signal. An error detecting module is integrated with the semiconductor device, samples values of the output signal, and outputs the sampled values to the test module.

Abstract: Various embodiments comprise apparatus, methods, and systems that include an apparatus comprising a memory device configurable as a plurality of erase block groups including a base erase block group, wherein each of the plurality of erase block groups comprises a plurality of erase blocks each identified by a matching unique plurality of erase block numbers unique within the plurality of erase blocks and matching across the plurality of erase block groups; and a mapping table coupled to the plurality of erase block groups to store at least one group address number corresponding to one of the matching unique plurality of erase block numbers identifying a non-defective erase block in the base erase block group, and corresponding to several of the matching unique plurality of erase block numbers identifying a single non-defective erase block in each of the plurality of erase block groups other than the base erase block group.

Abstract: A clock data recovering circuit solving a problem in which a stable clock signal cannot be extracted is provided. A phase comparator includes a main-signal-discriminator. The main-signal-discriminator discriminates a reception signal by a clock signal to generate recovery data indicating the discrimination result. Phase comparator 2 uses the discrimination result of the main-signal-discriminator to compare phases of a reception signal and a recovery clock and outputs a phase comparison signal indicating the comparison result. A generator generates a recovery clock with a frequency corresponding to the comparison result indicated by the phase comparison signal outputted from phase comparator 2. An eye opening monitor detects an optimal discrimination point of main-signal-discriminator 1 based on a monitor signal split from the reception signal and the recovery data generated by the main-signal-discriminator.

Abstract: Provided is a memory system that can specify a cause of an error. According to the memory system, during writing, when write data is looped back, and the write data is an error, the error has occurred between first processing units (51 to 53) or second processing units (56 to 58) and an input/output unit (60). Thus, whether the error has occurred between the first processing units (51 to 53) or the second processing units (56 to 58) and the input/output unit (60), or in a memory (8) can be specified.

Abstract: This invention has as its object to attain strong security and to implement network solutions with high convenience and simplicity with low cost upon providing Web services. To this end, an information processing apparatus according to this invention has the following arrangement.

Abstract: Memory systems, systems and methods are disclosed that may include a plurality of stacked memory device dice and a logic die connected to each other by through silicon vias. One such logic die includes an error code generator that generates error checking codes corresponding to write data. The error checking codes are stored in the memory device dice and are subsequently compared to error checking codes generated from data subsequently read from the memory device dice. In the event the codes do not match, an error signal can be generated. The logic die may contain a controller that records the address from which the data was read. The controller or memory access device may redirect accesses to the memory device dice at the recorded addresses. The controller can also examine addresses or data resulting in the error signals being generated to identify faults in the through silicon vias.

Abstract: An interface circuit comprises at least one supply input and at least one data input with a protective circuit coupled between the at least one supply input and the at least one data input. A power supply circuit is coupled to the at least one supply input. The interface circuit further comprises an error detection circuit coupled to the supply input and to the at least one data input. The error detection circuit is designed to compare a supply signal applied to the supply input with a data signal applied to the at least one data input and to generate an error signal on the basis of the comparison result.

Abstract: A method for determining a contribution of burst noise to a bit error rate in a digital system for reception of an interleaved forward error correction-enabled digital symbol stream is described. The method is based on identifying errored symbols at a decoding stage, determining their positions in the interleaved stream, and performing a windowing operation such that the errored symbols located within the window in the interleaved stream are designated as burst errored symbols. A corresponding digital receiver and a digital transmission system are also disclosed.

Abstract: Methods and apparatus for performing, using smaller, more efficient shared logic circuitry, the parity checking function and the compare function in a mutually exclusive manner in different cycles of a ternary content addressable memory are disclosed.

Abstract: According to one embodiment, a semiconductor integrated device which stores secret data and is capable of operating in a test mode in which a scan test with respect to an internal circuit is executed, the semiconductor integrated device comprises a mode signal receiving module configured to receive a scan mode signal designating the test mode, a mask module configured to mask the secret data when the mode signal receiving module receives the scan mode signal, and an error detection module configured to detect presence or absence of error in the secret data and to store detection result in a first flip-flop.

Abstract: A technique for monitoring a primary data stream comprising a plurality of secondary data streams for abnormalities is provided. A deviation value for each of two or more of the plurality of secondary data streams is determined. The two or more deviation values of the two or more secondary data streams are combined to form a combined deviation value. An abnormality signal is generated based at least in part on the combined deviation value.

Abstract: A method includes determining a length of a file and storing the length of the file in a first memory location. An endpoint of a last complete record within the file is determined and the endpoint is stored in a second memory location. The length of the file stored in the first memory location is compared to a current length of the file, and a data structure associated with the file is updated beginning at the endpoint if the current length of the file exceeds the length of the file stored in the first memory location.

Abstract: Circuits and associated methods for testing internal operation of an application integrated circuit. Features and aspects hereof add configurable test interrupt circuits to an application circuit design to permit dynamic, configurable interrupt generation from an integrated circuit based on conditions determined from monitoring of internal signals of the application circuit. The internal signals that may be tested and used to generate test interrupts are those not exposed to the external processor interface of the integrated circuit and thus may be configured to interrupt based on any internal state of the application specific functional circuits of the integrated circuit.

Abstract: A radio communications device includes a first error detection part configured to perform error detection on a header included in a packet; a determination part configured to determine whether there is consistency with respect to the length of the packet based on the header in response to the first error detection part detecting no error in the header; a decryption part configured to decrypt the packet in response to the determination part determining that there is consistency with respect to the length of the packet; and a second error detection part configured to perform error detection on the packet in response to the determination part determining that there is consistency with respect to the length of the packet, wherein the decryption part is configured to start to decrypt the packet before completion of the error detection by the second error detection part.

Abstract: A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for receiving and storing therein the data which have passed through the data input section; memory cell arrays for storing therein the data which have passed through the data input section; and a data compressor for determining whether or not the data stored in the latch section and the data stored in the memory cell arrays are identical to each other.

Abstract: A method of processing a stream of coded data before decoding comprises a step of detecting missing or erroneous data in the stream of coded data. It comprises a step of generating a series of data ready for decoding formed from the stream of coded data, and a series of additional data supplying information representing the position of the missing or erroneous data detected.

Abstract: In a computer system in which personalization data for an ASIC is stored in latches, this data is susceptible to soft errors. Many computer systems require high levels of error detection, error correction, fault isolation, fault tolerance, and self-healing. In order to complete an ASIC design and release it to a foundry, it must first be verified that the design meets the frequency requirements of its specification. A fault tolerant, self-correcting, non-glitching, low power circuit is described which meets all the requirements for reliability, while also eliminating any requirement to add area or power to the ASIC in order to meet the frequency specification for personalization latches. By using the circuits as a repeatable structure, the verification of the self-healing property is simplified relative to a collection of Error Correction Code usages of various bit widths.

Abstract: In one embodiment, a programmable logic device for recovery from soft error upsets (SEUs) includes: a configuration memory operable to store configuration data; a configuration engine operable to configure the configuration memory; an error detection circuit operable to determine if the stored configuration data in the configuration memory has an error; and a configuration reset circuit operable to trigger the configuration engine to reconfigure the configuration memory if the error detection circuit detects the error.

Abstract: The storage apparatus is provided with a host interface adapter unit, a storage interface adapter unit, a cache memory unit storing data temporarily, a switch unit connecting the host interface adapter unit, the storage interface adapter unit, and the cache memory unit, a compressed data circuit unit producing compressed data based upon writing data into the physical storing device, and a compressed data saving unit saving compressed data produced in the compressed data circuit unit, where the compressed data circuit unit compressed reading data at a reading time of the data from the physical storing device, and compares the compressed data with compressed data corresponding to reading data saved in the compressed data saving unit with each other, and detects data rigging.

Abstract: A method and apparatus for a structure of a flip-flop that is tolerant to the noise pulses occurring due to the presence of crosstalk faults by sampling the input data multiple times before and after the active clock edge. The final stored value at the flip-flop is determined by the resolution of a counter circuit residing in the flip-flop, which is activated at the change of the sampled input data. This counter based resolution mechanism allows for the detection and filtering of the noise pulse induced at the input of the flip-flop due to a crosstalk fault.

Abstract: Noise is detected within an operating frequency of a communication medium. Messages are monitored on the communication medium for corrupted messages. A noise detected signal is generated when a number of corrupted messages detected reaches a corrupted message threshold.

Abstract: A technique to detect errors in a computer system. More particularly, at least one embodiment of the invention relates to using redundant virtual machines and comparison logic to detect errors occurring in input/output (I/O) operations in a computer system.

Abstract: A detector to detect the magnitude of the jitter that may occur in a first clock signal and a second clock signal and to generate an alarm signal if the magnitude of the jitter exceeds the threshold value. The detector comprises a one-hot register storing a one-hot value comprising a first logic bit (=1) centered around one or more second logic bits (=0). The detector comprises a threshold register storing a threshold value comprising one or more second logic bits centered around one or more first logic bits. An event of a first clock rotates the contents of the one-hot value and an event of a second clock rotates the contents of the threshold value. A match between the pre-specified bit of the one-hot value and the threshold value indicates the occurrence of the jitter having a magnitude greater than the threshold value.

Abstract: Decentralized orchestration of composite services results in a number of flow topologies which differ in their messaging patterns and the distribution of flow code amongst different partitions of a topology. Different performance metrics result for different topologies, and this is governed by the availability of resources, such as CPU cycles, memory, network bandwidth, and so on. A performance model is used to evaluate the performance of different topologies based on availability of resources, and dynamically direct client requests between different topologies according to prevailing conditions.

Abstract: Techniques are described for detecting corruption of buffer pointers passed between a local processor and a remote processor on a network device. For example, the first processor, which may be a memory controller, receives and stores packets within memory. A second processor, such as a host processor for the network device, is coupled to the first processor by a bus. The first processor communicates a memory pointer associated with an a given packet to the second processor for processing of the packet, and maintains a backup copy of the memory pointer. Upon receiving the memory pointer back from the second processor, the first processor compares at least a portion of the memory pointer received from the second processor with an equivalent portion of the copy of the memory pointer to determine whether the received memory pointer has been corrupted.

Abstract: A method for comparing data in a computer system having at least two execution units, the comparison of the data taking place in a comparison unit and each execution unit processing input data and generating output data, wherein one execution unit specifies to the comparison unit that the next piece of output data is to be compared to a piece of output data of the at least second execution unit, and thereupon a comparison of the at least two output data takes place.

Abstract: When a plurality of data blocks are divided into a plurality of frames and the divided frames are transmitted, every time a frame is received, a interim calculation result of a check code is updated using a transitional calculation result of the check code of the data block corresponding to the frame received and the data included in the frame. When a final calculation result of the check code of a data block is obtained, the calculation result is compared with the check code included in the data block.

Abstract: A circuit for a data processing apparatus and a method for detecting spurious signals is disclosed, the circuit comprising a data input operable to receive digital signal values, spurious signal detection logic operable to monitor a digital signal value within the circuit, and to determine at least one of: a safe time window during which it is expected that the digital signal values input into the circuit may cause data transitions in the monitored digital signal value and a transition time window in which it is expected a data transition will occur; and in response to detecting either a data transition in the monitored digital signal value outside of the at least one safe time window or no data transition in the transition window, the spurious signal detection logic is operable to output a detection signal.

Abstract: An image data test unit includes a data acquisition unit configured to acquire image data having individual frames, an image data temporary storage unit configured to receive the acquired image data from the data acquisition unit to store a certain amount of the image data, and a test calculation unit configured to sequentially receive the image data from the image data temporary storage unit to store a certain amount of the image data, and compare the stored image data with pre-set test elements. In addition, an image apparatus having the image data test unit and a method of testing image data using the image data test unit are also provided.

Abstract: A process for identifying the location of a break in a scan chain in real time as fail data is collected from a tester. Processing a test pattern before applying it on a tester provides a signature enabling a method for a tester to identify a scan cell which is stuck during the time the tester is operating on a device under test rather than accumulating voluminous test data sets for delayed offline analysis.

Abstract: A method, system and apparatus of lossy compression technique for video encoder bandwidth reduction using compression error data are disclosed. In one embodiment, a method includes storing an error data from a compression of an original reference data in an off-chip memory, accessing the error data during a motion compensation operation, and performing the motion compensation operation by applying the error data through an algorithm (e.g., determined by the method of storing the error data). The method may include generating a predicted frame in the motion compensation operation using a motion vector and an on-chip video data. In addition, the method may include determining the error data as a difference between a compressed reference data (e.g., is created by compressing the original reference data) and an original reference data (e.g., reconstructed from a prior predicted frame and a decompressed encoder data).

Abstract: A code error detecting device that can more precisely detect a code error due to a delayed wave is disclosed. The code error detecting device includes a receiving antenna (121) for receiving a on-off keying modulated pulse and its code-reversed pulse, a pulse detector (124) for outputting detected data in accordance with the pulses, a code comparing unit (128) for comparing each code of first received data (R1) with one of second received data (R2), wherein the first and second received data are derived from the output detected data, and an error detecting unit (129) for detecting an error of each code from a comparison result (D2) indicative of a result compared in the code comparing unit (128).

Abstract: An error detecting device enables proper detection of an occurrence of a data error in a register. The error detecting device for detecting an occurrence of a data error in a register for holding input data with reception of a write permission comprises an operation circuit for performing a prescribed operation with each data output from a plurality of registers, a comparison register for storing data for comparison, a write unit for writing data obtained through the operation in the operation circuit into the comparison register in accordance with the timing of write permission by the write permission signal and a comparator for comparing the data for comparison stored in the comparison register with the data obtained through the operation in the operation circuit so as to detect garbled data in the registers.

Abstract: A microprocessor simulation method, system, and program product, which are built upon the underlying hardware design of the microprocessor, stop normal functions of a simulation testcase, start the scan clocks, and record a first “snap shot” of the scan ring data at an initial time. The hardware logic then rotates (shifts) the scan ring using the current scan data, and when the scan clock stops (where the stop of the scan clock is controlled based on the number of latches on the scan ring), another “snap shot” of scan ring data is taken. The “snap shots” are compared and if both of the “snap shots” are identical the functional scan is successful. But if the functional scan verification fails to rotate the scan chain correctly, that is, if some of the latches do not match in the two “snap shots,” it becomes necessary to locate the broken spot within the large number of scan latches.

Abstract: Embodiments of apparatuses and methods for reducing the soft error vulnerability of stored data are disclosed. In one embodiment, an apparatus includes storage logic, determination logic, and selection logic. The determination logic is to determine a condition of a dataword. The storage logic includes logic to store a first portion of the dataword, a second portion of the dataword, and a result generated by the determination logic. The selection logic is to select, based on the contents of the storage logic to store the result, either the contents of the storage logic to store the second portion of the dataword, or a replacement value. The replacement value depends on the contents of a predetermined bit of the storage logic to store the first portion of the dataword.

Abstract: According to one embodiment, an information processing system is coupled to a number of sensors for receiving information generated by the sensors. The information processing system generates records from the received information and binds the records in a multi-dimensional structure including a temporal dimension and another dimension including other records that share a common criterion. The information processing system compares a particular record against other records to detect an abnormality of the particular record.

Abstract: A decoder provided according to an aspect of the present invention determines a type of each network abstraction layer (NAL) unit, and discards a NAL unit when the size of the NAL unit is inconsistent with the size according to the determined type. According to another aspect, a decoder corrects for errors in the non-pay load portions and uses the corrected non-pay load portions to recover the original data contained in the payload portions of the data stream. In an embodiment, various global parameters (which are applicable to the data stream unless changed further in the data stream) and the values in the slice headers are examined to correct the parameters in the slice headers. According to one more aspect, an end of frame is reliably detected by using an expected number of macro-blocks in a frame and a set of logical conditions of slice header parameters.

Abstract: A system for checking basic input output system read only memory (BIOS ROM) data includes a keyboard, a display, a computer host, and a checking device. The computer host has a BIOS ROM installed therein. The checking device includes: a data dividing module for dividing the BIOS ROM data into a plurality of sections; a data obtaining module for capturing BIOS ROM data from one or more sections, and for counting a check datum; a data checking module for comparing the check datum with a standard datum, and for determining whether the two data are equal; and a checking result outputting module for outputting the checking results.

Abstract: A configurable and reusable hardware-software NAND system adaptive to various NAND devices independent of the NAND device manufacturer and NAND device characteristics. A device identification signature is decoded from a NAND device in a NAND system; the device identification signature signal is analyzed to obtain a control phase sequence value descriptive of a characteristic of the NAND device; the control phase register is populated with the control phase sequence value; and control phase register provides the control phase sequence values to the command sequencer. The control phase register can be programmed by a low level driver for devices which NAND system cannot decode the device identification signature.

Abstract: To identify errored bits in a binary data set, an ordered plurality of modulo-2 summations of respective selections of the data-set bits are compared with a target syndrome. The selections of data-set bits are defined by the connection of sum nodes to variable nodes in a logical network of nodes and edges where each variable node is associated with a respective data-set bit and each sum node corresponds to a respective modulo-2 summation. Any sum node for which the corresponding summation of selected data-set bits is found to be inconsistent with the target syndrome is identified as errored. Predetermined patterns of errored sum nodes are then looked for to identify one or more associated errored data-set bits.

Abstract: A method for testing an internal bus of a random access memory (“RAM”) device, the RAM device having an internal cache coupled to a memory array by the internal bus, the method comprising: writing a value to an address in the RAM device, the value being stored in the internal cache, the value corresponding to at least one line of an external bus; writing a number of additional values to addresses in the RAM device other than the address to push the value from the internal cache into the memory array; reading a value from the address; and, determining whether the internal bus is faulty by comparing the value written to the value read.