Responding To The Occurrence Of A Fault, E.g., Fault Tolerance, Etc. (epo) Patents (Class 714/E11.021)

  • Publication number: 20090216489
    Abstract: Systems and methods for deriving parameters for frequency domain impulse noise detectors are described. At least one embodiment is a method for deriving a set of parameters associated with a frequency domain impulse noise detector. In accordance with such embodiments, the method comprises setting values for ?pivot and ?c, wherein ?pivot and ?c are values associated with a monotonic function of a ratio of a statistical parameter of disruptive noise to a statistical parameter of nominal noise. The method further comprises selecting a fixed ratio (m/M), wherein M is a number of monitored tones, and wherein m is a number of slicer error samples that must exceed a decision threshold for a symbol to be flagged as corrupted.
    Type: Application
    Filed: February 22, 2008
    Publication date: August 27, 2009
    Applicant: CONEXANT SYSTEMS, INC.
    Inventors: Amitkumar Mahadevan, Patrick Duvaut, Julien D. Pons
  • Publication number: 20090217109
    Abstract: Endpoint crashes in a real time communication system are detected by a home server providing presence and other services to the endpoint upon receipt of an error message from an access server between the endpoint and the home server. The home server uses a cookie inserted into a dialog between itself and the endpoint identifying the endpoint, a session state created by the access server identifying the endpoint, or a transaction state maintained by the home server to look up the endpoint associated with the error message. Race conditions occurring when an endpoint crashes and recovers rapidly can be avoided employing a timestamp or sequence number incremented for each new endpoint registration and comparing a current timestamp or sequence number to the stored one before updating records at the home server. By notifying other subscribers about crashed endpoints, routing fidelity is enhanced.
    Type: Application
    Filed: February 27, 2008
    Publication date: August 27, 2009
    Applicant: Microsoft Corporation
    Inventors: Dhigha D. Sekaran, Sankaran Narayanan
  • Publication number: 20090210738
    Abstract: A data control unit includes a primary power supply line to which a primary power supply voltage is supplied; a secondary power source line to which a secondary power supply voltage is supplied; a voltage converter for converting the primary power supply voltage into the secondary power supply voltage; a voltage level detection unit which is connected to the primary power source line, and outputs a voltage level detection signal; a reset signal generator which is connected to the secondary power source line, and outputs a reset signal; and a control signal generation unit which receives the voltage level detection signal and the reset signal, and outputs a control signal. The data control unit detects power supply cutoff, and secures the time for sufficient backup process.
    Type: Application
    Filed: February 12, 2009
    Publication date: August 20, 2009
    Applicant: Rohm Co., Ltd.
    Inventor: Hiromitsu Kimura
  • Publication number: 20090208019
    Abstract: The present invention relates to a method and apparatus for encrypting data (105) by means of a first key (115), and a method and apparatus for decrypting encrypted data by means of a second key (185). The present invention alleviates the need for exact key information by allowing encryption of data (105) by means of a first key (115) and subsequent decryption of the encrypted data by means of a second key (185) without the need for the first key (115), provided that the first key (115) and the second key (185) form a sufficient estimate of an encryption/decryption key pair. During encryption, multiple encryption keys (135), at least in part based on the first key (115), are used to encrypt a redundant representation (122) of the data (105). The encrypted data (124) may subsequently be decrypted by using multiple decryption keys (165) based on the second key (185), without the need for the first key (115), provided that the second key (185) forms a sufficient estimate of the first key (115).
    Type: Application
    Filed: June 29, 2007
    Publication date: August 20, 2009
    Applicant: Koninklijke Philips Electronics N.V.
    Inventors: Mehmet Utku Celik, Boris Skoric, Pim Theo Tuyls
  • Publication number: 20090204559
    Abstract: Given a set of training examples—with known inputs and outputs—and a set of working examples—with known inputs but unknown outputs—train a classifier on the training examples. For each possible assignment of outputs to the working examples, determine whether assigning the outputs to the working examples results in a training and working set that are likely to have resulted from the same distribution. If so, then add the assignment to a likely set of assignments. For each assignment in the likely set, compute the error of the trained classifier on the assignment. Use the maximum of these errors as a probably approximately correct error bound for the classifier.
    Type: Application
    Filed: February 7, 2008
    Publication date: August 13, 2009
    Inventors: Eric Bax, Augusto Callejas
  • Publication number: 20090199044
    Abstract: Software running on a processor is operable to control the cycled powering down and powering up of components of a self-service terminal (SST) in order to attempt to rectify a fault within the SST without the need to power down the SST core processor. The software can also control the resetting of universal serial bus (USB) ports associated with the components of the SST in order to try and clear faults associated with a communications link between a component and the SST core processor.
    Type: Application
    Filed: January 31, 2008
    Publication date: August 6, 2009
    Inventor: Nicholas J. Hurrell
  • Publication number: 20090193296
    Abstract: A test system tests a full system integrated circuit (IC) model that includes a device under test (DUT) IC model and a support IC model. A test manager information handling system (IHS) maps the full system IC model on a hardware accelerator simulator via an interface bus. The hardware accelerator simulator thus emulates the full system IC model. Of all possible fault injection points in the model, the test manager IHS selects a subset of those injection points for fault injection via a statistical sampling method in one embodiment. In response to commands from the test manager IHS, the simulator serially injects faults into the selected fault injection points. The test manager IHS stores results for respective fault injections at the selected injection points. If a machine checkstop or silent data corruption error occurs as a result of an injected fault, the DUT IC model may return to a stored checkpoint and resume operation from the stored checkpoint.
    Type: Application
    Filed: January 30, 2008
    Publication date: July 30, 2009
    Applicant: IBM Corporation
    Inventors: Jeffrey William Kellington, Prabhakar Nandavar Kudva, Naoko Pia Sanda, John Andrew Schumann
  • Publication number: 20090187946
    Abstract: Enhancing a stream layer transmission for a MediaFLO™ mobile multimedia multicast system comprising a transmitter and a receiver. Code word (CW) computations are performed on a current channel being accessed by the receiver. A favorite channel that a user is statistically mostly likely to switch to on the receiver at any particular time is anticipated. The Overhead Information Symbols (OIS) for each favorite channel is periodically monitored. The receiver remains in a sleep mode while data bursts are received from non-favorite channels, and then wakes up during data bursts of the favorite channel. The same CW computations are performed on the favorite channel as were being performed on the current channel. A cyclic redundancy check (CRC) is performed once the CW computations are performed upon selecting the favorite channel.
    Type: Application
    Filed: January 23, 2008
    Publication date: July 23, 2009
    Applicant: Newport Media, Inc.
    Inventor: Nabil Yousef
  • Publication number: 20090187791
    Abstract: A failure identification routine uses a two pass stack trace analysis in conjunction with a list of called types. As each method is called, a call list is generated with the called type, method, and various metadata. During the first pass stack trace analysis, each stack frame is analyzed to determine if the failed type is included in the stack frame. If so, the method associated with the frame is flagged as suspect. If the failed type is not found in the first stack trace, a second pass stack trace analysis is performed and an assembly associated with the method associated with the stack frame is analyzed to determine a set of types. The set of types are analyzed to find at least one match with the called types. If a match exists, the methods associated with the matched types are flagged as suspect.
    Type: Application
    Filed: January 22, 2008
    Publication date: July 23, 2009
    Applicant: MICROSOFT CORPORATION
    Inventors: Rafael Goodman Dowling, Ryan Randal Elliott, Israel Hilerio
  • Publication number: 20090187787
    Abstract: Method, computer program product, and system for transferring data from positional data sources to partitioned databases are provided. A record is read from a positional data source. The record is to be written to one of a plurality of partitions of a database. A position of the record in the positional data source is obtained. A transaction is initiated to write the record to the one partition and to store the position of the record in the database. The transaction is committed after the record is successfully written to the one partition and the position of the record is successfully stored in the database.
    Type: Application
    Filed: January 17, 2008
    Publication date: July 23, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jing-Song JANG, James Michael Mcardle, Michael John Elvery Spicer
  • Publication number: 20090187798
    Abstract: A nonvolatile memory having a non-power of two memory capacity is disclosed. The nonvolatile memory device includes at least one plane. The plane includes a plurality of blocks with each of the blocks divided into a number of pages and each of the blocks defined along a first dimension by a first number of memory cells for storing data, and along a second dimension of by a second number of memory cells for storing data. The nonvolatile memory has a non-power of two capacity proportionally related to a total number of memory cells in said plane. The nonvolatile memory also includes a plurality of row decoders. An at least substantially one-to-one relationship exists, in the memory device, for number of row decoders to number of pages. Each of the row decoders is configured to facilitate a read operation on an associated page of the memory device.
    Type: Application
    Filed: March 5, 2008
    Publication date: July 23, 2009
    Applicant: MOSAID Technologies Incorporated
    Inventor: Jin-Ki KIM
  • Publication number: 20090187807
    Abstract: A method of determining optimal FEC configuration parameters, a communications controller, a communications link and a communications node is disclosed. In one embodiment, the communications controller, includes: (1) a processor, (2) a communications system information collector configured to receive operational information from a communications system having a block encoder, a block decoder and a decision feedback equalizer, (3) a code determiner configured to employ the operational information to select, from a set of candidate codes, a random error correction code or a burst error correction code that has a least error correction capability and satisfies a target performance specification for the communications system and (4) a parameter selector configured to select configuration parameters associated with the selected random error correction code or the selected burst error correction code and send the selected configuration parameters to the block encoder and the block decoder.
    Type: Application
    Filed: January 23, 2009
    Publication date: July 23, 2009
    Applicant: Texas Instruments Incorporated
    Inventors: Rajan L. Narasimha, Nirmal C. Warke
  • Publication number: 20090183028
    Abstract: Computer implemented method, system and computer usable program code for configuring a computing system. A determination is made whether there are any errors in the model, and responsive to determining that there is at least one error in the model, a determination is made whether there is at least one resolution for correcting the at least one error. Responsive to determining that there is at least one resolution for correcting the at least one error, at least one resolution among the at least one resolution for correcting the at least one error is selected to form at least one selected resolution to correct the at least one error. The at least one selected resolution is applied to the model to form a transformed model, and the transformed model is output to a user.
    Type: Application
    Filed: January 15, 2008
    Publication date: July 16, 2009
    Inventors: William Carlisle Arnold, Daniel Christopher Berg, Brad Lee Blancett, Tamar Eilam, Chad M. Holliday, Michael Husayn Kalantar, Alexander V. Konstantinou, Narinder Markin, Edward Charles Snible, John Eric Swanke, Andrew Neil Trossman, Paul Darius Vytas, Alice Tse Yun Yeung, MICHAEL D. ELDER
  • Publication number: 20090183021
    Abstract: Computer implemented method, system and computer usable program code for configuring a computing system. A system for configuring a computing system includes a mechanism for creating a model of a computing system, a validator for determining whether there are any errors in the model, and a resolver, responsive to determining that there is at least one error in the model, for determining whether there is at least one resolution for correcting the at least one error. A selector, responsive to determining that there is at least one resolution for correcting the at least one error, selects at least one resolution among the at least one resolution for correcting the at least one error to form at least one selected resolution to correct the at least one error, and applies the at least one selected resolution to the model to form a transformed model. An output outputs the transformed model to a user.
    Type: Application
    Filed: January 15, 2008
    Publication date: July 16, 2009
    Inventors: William Carlisle Arnold, Daniel Christopher Berg, Brad Lee Blancett, Tamar Eilam, Chad M. Holliday, Michael Husayn Kalantar, Alexander V. Konstantinou, Narinder Makin, Edward Charles Snible, John Eric Swanke, Andrew Neil Trossman, Paul Darius Vytas, Alice Tse Yeung
  • Publication number: 20090177931
    Abstract: Memory devices and/or error control codes (ECC) decoding methods may be provided. A memory device may include a memory cell array, and a decoder to perform hard decision decoding of first data read from the memory cell array by a first read scheme, and to generate output data and error information of the output data. The memory device may also include and a control unit to determine an error rate of the output data based on the error information, and to determine whether to transmit an additional read command for soft decision decoding to the memory cell array based on the error rate. An ECC decoding time may be reduced through such a memory device.
    Type: Application
    Filed: May 14, 2008
    Publication date: July 9, 2009
    Inventors: Seung-Hwan Song, Jun Jin Kong, Jae Hong Kim, Kyoung Lae Cho, Sung Chung Park
  • Publication number: 20090172507
    Abstract: According to one embodiment, an information processing system is coupled to a number of sensors for receiving information generated by the sensors. The information processing system generates records from the received information and binds the records in a multi-dimensional structure including a temporal dimension and another dimension including other records that share a common criterion. The information processing system compares a particular record against other records to detect an abnormality of the particular record.
    Type: Application
    Filed: March 5, 2009
    Publication date: July 2, 2009
    Applicant: Raytheon Company
    Inventor: Howard C. Choe
  • Publication number: 20090172493
    Abstract: An apparatus for decoding a Low Density Parity Check (LDPC) is provided.
    Type: Application
    Filed: December 23, 2008
    Publication date: July 2, 2009
    Applicants: SAMSUNG ELECTRONICS CO. LTD., BEIJING SAMSUNG TELECOM R & D CENTER
    Inventors: Beom-Jin PARK, Congchong RU, Dan WANG, Lijun WEI, Sung-Jin PARK
  • Publication number: 20090172506
    Abstract: A semiconductor device including a first processing unit processing an input signal based on a plurality of image compression standards, a signal generation unit outputting a switching signal to the first processing unit, a first calculation unit performing an operation on the input signal in accordance with a first coefficient that is based on the switching signal, a second calculation unit performing an operation on an output of the first calculation unit in accordance with a second coefficient that is based on the switching signal, a selection unit selecting one of the output of the first calculation unit and an output of the second calculation unit based on the switching signal, and a third calculation unit selecting one or both of the input signal and the output of the first calculation unit based on the switching signal and performing a predetermined calculation on the selected signal.
    Type: Application
    Filed: December 24, 2008
    Publication date: July 2, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Noboru YONEOKA, Hirofumi Nagaoka
  • Publication number: 20090172494
    Abstract: In order to correctly perform error analysis, test, or the like, a 64B/66B converter of a PCS processing unit of a transmitter conforming to 10 GBASE-R PHY performs 64B/66B conversion on data on a block basis that is transmitted over four lanes, the block being formed of two columns. In the conversion, when a control signal inputted via a control signal input terminal indicates a normal operation mode, if an error code in a block to be converted is detected by an error detector, error expansion that replaces all 8 bytes of data in the block with an error code /E/ is performed. In contrast, when the control signal indicates an analysis mode, the error expansion is not performed even if an error code is detected by the error detector.
    Type: Application
    Filed: December 24, 2008
    Publication date: July 2, 2009
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Tomofumi IIMA
  • Publication number: 20090172461
    Abstract: Conditionally performing delegated actions based on runtime conditions of the environment. A component of an Information Technology environment conditionally performs an action, such as its own recovery, based on whether the component can have such action delegated to it and/or whether that component is currently being shared by multiple business applications of the environment.
    Type: Application
    Filed: December 28, 2007
    Publication date: July 2, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mythili K. BOBAK, Tim A. McConnell, Michael D. Swanson
  • Publication number: 20090164852
    Abstract: Methods, apparatus, and products are disclosed for preemptive thermal management for a computing system based on cache performance, the computing system having a processor, cached computer memory operatively coupled to the processor, and a processor cache operatively coupled to the processor, the processor cache capable of storing a subset of memory contents of the cached computer memory, that include: attempting, by the processor, to retrieve portions of the memory contents of the cached computer memory from the processor cache, resulting in cache misses for the processor cache; tracking, by the processor, cache miss statistics for the processor cache in the computing system, the cache miss statistics describing the cache misses for the processor cache; and administering a thermal management device for the computing system in dependence upon the cache miss statistics, the thermal management device operatively coupled to the processor and capable of managing temperature for the computing system.
    Type: Application
    Filed: December 19, 2007
    Publication date: June 25, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Challis L. Purrington, Michael L. Scollard, Victor A. Stankevich, Ivan R. Zapata
  • Publication number: 20090164835
    Abstract: A system and method for retaining routes in a control plane learned by an inter-domain routing protocol in the event of a connectivity failure between routers. Routers are classified as either route reflectors or originators. A determination is made whether the connectivity failure occurred between a route reflector and an originator, two originators, or two route reflectors. A determination is then made whether to propagate a withdrawal of learned routes based on whether the connectivity failure occurred between a route reflector and an originator, two originators, or two route reflectors. A withdrawal of learned routes is propagated to neighboring routers if the connectivity failure occurred between two originators, or between a route reflector and an originator that is inaccessible via an intra-domain routing protocol.
    Type: Application
    Filed: December 19, 2007
    Publication date: June 25, 2009
    Inventor: James Uttaro
  • Publication number: 20090164872
    Abstract: A method for predicting and preventing uncorrectable errors that may occur while accessing memory in a computer system. The method involves detecting two or more correctable errors from two or more different physical addresses on each of two or more different bit positions from the same DIMM within a specified period of time, with all of the correctable errors occurring within the same checkword. The method also involves detecting two or more correctable errors from two or more different physical addresses on each of three or more different outputs from the same DRAM within a specified period of time, as long as the three outputs do not all correspond to the same relative bit position in their respective checkwords. This allows a computer system which encounters correctable errors to continue to reliably operate without the unnecessary replacement of functioning memory systems.
    Type: Application
    Filed: December 21, 2007
    Publication date: June 25, 2009
    Applicant: Sun Microsystems, Inc.
    Inventors: Stephen A. Chessin, Louis Tsien
  • Publication number: 20090164868
    Abstract: A method and apparatus for buffering an encoded signal having a plurality of codewords for a turbo decoder is provided. The method comprises de-interleaving each sub-block of the codeword received at the turbo-decoder; and storing LLRs of the de-interleaved codeword LLRs into an input buffer. Thereafter, each of punctured locations, if any, in the de-interleaved codeword is indicated to a read logic for enabling the latter to fill in each of those locations with a pre-determined LLR value as and when a read request corresponding to one of those locations arrives. This method obviates the need for storing the pre-determined LLRs at the punctured locations into the input buffer and thereby cuts down the input latency of turbo decoder significantly for higher code rates.
    Type: Application
    Filed: December 21, 2007
    Publication date: June 25, 2009
    Inventors: Amit Anand, Hariprasad Gangadharan, Prasoon Kumar
  • Publication number: 20090164846
    Abstract: Fault injection in dynamic random access memory (‘DRAM’) modules for performing built-in self-tests (‘BISTs’) including establishing, in the mode registers of the DRAM modules by the memory controller through the shared address bus, an injection of a fault into one or more signal lines of a DRAM module, the fault characterized by a fault type; writing data by the memory controller through a data bus to the DRAM modules, the data identifying a particular DRAM module; and responsive to receiving the data, injecting, by the particular DRAM module, the fault characterized by the fault type into the one or more signal lines of the particular DRAM module.
    Type: Application
    Filed: December 19, 2007
    Publication date: June 25, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jimmy G. Foster, SR., Nickolaus J. Gruendler, Suzanne M. Michelich, Jacques B. Taylor
  • Publication number: 20090158127
    Abstract: Disclosed herein is a decoding apparatus that performs soft-decision decoding on a linear block code, the apparatus including a hard-decision decoder configured to perform hard-decision decoding on a received word using a hard-decision decoding algorithm; and a soft-decision decoder configured to perform, using a soft-decision algorithm, soft-decision decoding merely on a received word for which the hard-decision decoder has failed in the hard-decision decoding.
    Type: Application
    Filed: December 16, 2008
    Publication date: June 18, 2009
    Inventors: Toshiyuki MIYAUCHI, Masayuki Hattori, Takashi Yokokawa
  • Publication number: 20090158116
    Abstract: A method for generating a Low Density Parity Check (LDPC) code is provided. The method includes generating subsets each including a same number of check nodes, connecting each of variable nodes to the check nodes of the subsets so that the each of subsets is equal in degree or a difference in degree between the subsets becomes a maximum of 1, setting elements corresponding to check nodes connected to each of the variable nodes, to a non-zero value, and generating a parity check matrix H having rows corresponding to the check nodes and columns corresponding to the variable nodes.
    Type: Application
    Filed: December 11, 2008
    Publication date: June 18, 2009
    Applicant: Samsung Electronics Co. LTD.
    Inventor: Sung-Hwan Kim
  • Publication number: 20090158128
    Abstract: A decoding device for a linear code on a ring R, the decoding device including: a plurality of storage media; and a processing section; wherein the processing section uses a part of reliability of all symbols at a previous time to update reliability of each symbol in a process of iterative decoding for increasing the reliability of each symbol, and further retains a part used to update retained reliability information and a part unused to update the retained reliability information on two separate storage media.
    Type: Application
    Filed: December 16, 2008
    Publication date: June 18, 2009
    Inventors: Takashi Yokokawa, Makiko Yamamoto
  • Publication number: 20090158084
    Abstract: Techniques for coding and decoding redundant coding for column defects cartography. Defective cell groups identified in a memory array are redundantly encoded with a different bit pattern than the bit pattern used for functional cell groups. The identified defective cell groups are repaired using redundant cell groups in the memory array. The defective cell groups are later re-identified by checking the redundant bit pattern encoded in the cell groups. If new defective cell groups are identified, the memory array is identified as failing. If no new defective cell groups are identified, the memory array is identified as passing, and the identified defective cell groups are repaired.
    Type: Application
    Filed: December 17, 2007
    Publication date: June 18, 2009
    Applicant: ATMEL CORPORATION
    Inventors: Marc Merandat, Yves Fusella
  • Publication number: 20090158115
    Abstract: A method and apparatus for decoding a signal in a communication system. The method and apparatus includes receiving a punctured codeword including information bit nodes and unpunctured parity bit nodes; analyzing the unpunctured parity bit nodes, and detecting at least one first block including the unpunctured parity bit nodes among a plurality of blocks each including parity bit nodes having the same importance among all parity bit nodes; and recovering said all parity bit nodes by serial-decoding parity bit nodes included in the first block according to decoding priorities of parity bit nodes, determined by reflecting the first block in a predetermined decoding priority determining algorithm.
    Type: Application
    Filed: December 12, 2008
    Publication date: June 18, 2009
    Applicant: Samsung Electronics Co., Ltd
    Inventor: Seul-Ki Bae
  • Publication number: 20090158120
    Abstract: A hierarchical cyclic redundancy check (CRC) is provided that enables CRC appending and detection. A message that includes a first message portion and a second message portion is transmitted to two or more receivers. The receivers are not aware of the first message portion. One of the receivers can be aware of the second message portion of the message. Each portion of the message can be encoded with a CRC in order to provide protection. The receiver that is aware of the second message portion is provided a higher level of cyclic redundancy check (CRC) protection than the receivers that are not aware of the second message portions.
    Type: Application
    Filed: September 30, 2008
    Publication date: June 18, 2009
    Applicant: QUALCOMM Incorporated
    Inventors: Ravi Palanki, Naga Bhushan
  • Publication number: 20090158108
    Abstract: Illustrative embodiments provide a computer implemented method, an apparatus, and a computer program product for error detection and recovery using an asynchronous transaction journal. In an illustrative embodiment the computer implemented method receives a request message from a requester, stores the request message in the asynchronous transaction journal and determines whether a sequence number contained within the request message is equal to a predetermined number. When the sequence number is equal, the computer implemented method performs a request in the request message to obtain a result and returns the result to the requester; otherwise the computer implemented method detects an error. The computer implemented method then attempts recovery from the error; otherwise the computer implemented method notifies the requestee.
    Type: Application
    Filed: December 12, 2007
    Publication date: June 18, 2009
    Inventors: David Franklin Manning, David James Shepherd
  • Publication number: 20090158091
    Abstract: A method, apparatus, and program product utilize intelligent job functionality to diagnose an error in a computer. After detecting an error in a first job processing a task, and in response to another attempt to perform the task, a job selection algorithm selects a predetermined job in which to perform the task and diagnose the error. The predetermined job can be the first job or a new job associated with a signature that corresponds to the task that experienced the error. The predetermined job can be used to diagnose the error in a debugging session. Alternately, the first job may enter a debug session immediately after experiencing an error.
    Type: Application
    Filed: December 13, 2007
    Publication date: June 18, 2009
    Inventors: Paul Reuben Day, Roger Alan Mittelstadt, Brian Robert Muras, Anne Marie Ryg
  • Publication number: 20090150713
    Abstract: Embodiments include a system, a device, and a method. A computing system includes a synchronous circuit. The synchronous circuit includes a first subcircuit powered by a first power plane having a first power plane voltage and a second subcircuit powered by a second power plane having a second power plane voltage. The system also includes an error detector operable to detect an incidence of a computational error occurring in the first subcircuit. The system further includes a controller operable to change the first power plane voltage based upon the detected incidence of a computational error. The system may include a power supply operable to provide a selected one of at least two voltages to the first power plane in response to the controller.
    Type: Application
    Filed: January 13, 2009
    Publication date: June 11, 2009
    Inventor: William Henry Mangione-Smith
  • Publication number: 20090150745
    Abstract: Trapping set decoding for transmission frames is disclosed. In one aspect, a trapping set decoder includes a decoder that performs decoding operations on an encoded codeword in received data, and a detector coupled to the decoder for detecting the presence of any one of a group of possible trapping sets in the decoding operations on the encoded codeword. A selection processor is also included, coupled to the decoder, for providing a decoded codeword by selecting one trapping set of the group of possible trapping sets, the selected trapping set being present in the decoding operations of the codeword, and by using the selected trapping set to produce the decoded codeword.
    Type: Application
    Filed: December 5, 2008
    Publication date: June 11, 2009
    Applicant: AQUANTIA CORPORATION
    Inventors: PAUL LANGNER, RAMIN SHIRANI
  • Publication number: 20090150742
    Abstract: The subject matter disclosed herein provides an outer coding framework for reducing the correlation between packet errors in a wireless network. In one aspect, there is provided a method. The method may include receiving a packet including information. The received packet may be encoded using a forward error correction code to provide at least one, but no more than two, codewords. At least a portion of each codeword may be inserted into a transport packet for transmission to a client station, wherein the transport packet comprises information from at least one, but no more than two, of the codewords. The transport packet may be sent. Related systems, apparatus, methods, and/or articles are also described.
    Type: Application
    Filed: August 29, 2008
    Publication date: June 11, 2009
    Inventor: Yoav Nebat
  • Publication number: 20090150746
    Abstract: Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D2) precoder of the HR RLL encoder may be split into two serial, 1/(1+D) precoders. One 1/(1+D) precoder may be pulled outside of the HR RLL encoder and used in conjunction with the iterative decoder. This may allow for a 1/(1+D) precoder that may be used with the iterative decoder while maintaining the RLL constraints imposed upon the encoded information by the HR RLL encoder.
    Type: Application
    Filed: December 6, 2008
    Publication date: June 11, 2009
    Inventors: Panu Chaichanavong, Nedeljko Varnica, Nitin Nangare, Gregory Burd, Zining Wu
  • Publication number: 20090144597
    Abstract: When retransmitting lost packets of data to multiple devices in a wireless network, the original sequence of packets containing all the lost packets may be encoded into a smaller number of packets for the retransmission. These encoded packets may be collectively addressed to all the intended receiving devices through broadcast or multicast addressing. These encoded packets may then be selectively decoded by the receiving devices, using the successfully received previous packets as part of the decoding process. Repetitive exclusive OR algorithms may be used for encoding and decoding.
    Type: Application
    Filed: December 4, 2007
    Publication date: June 4, 2009
    Inventors: FENG XUE, XUE YANG
  • Publication number: 20090144120
    Abstract: A system, a method, computer-readable medium for conveying software, or business methods for gradually automating a workflow in a configuration change management system by providing a first workflow template having a relatively low level of automation and complexity in which at least a plurality of tasks require manual input, manual response, or manual approval, operating the first workflow by a workflow automation system engine, monitoring a measurement of the maturity level of the process during the operation the first workflow, and responsive to detecting the maturity level meeting pre-determined benchmark, automatically selecting, engaging, and operating a second workflow template which increases automation by automating one or more subprocesses, adding one or more subprocesses, or eliminating one or more subprocesses.
    Type: Application
    Filed: November 1, 2007
    Publication date: June 4, 2009
    Inventor: P.G. Ramachandran
  • Publication number: 20090138785
    Abstract: A communication device that transmits and receives LDPC-encoded information by using MIMO technology. The communication device includes a transmission sorting unit that sorts LDPC-encoded bits constituting the LDPC-encoded information in a descending order of column degree of a check matrix used for generating the LDPC-encoded bits; and a signal transmitting unit that transmits the LDPC-encoded bits sorted by the transmission sorting unit by allocating the LDPC-encoded bits from a transmission line having a lower noise level in sorted order.
    Type: Application
    Filed: March 15, 2007
    Publication date: May 28, 2009
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Lui Sakai, Wataru Matsumoto, Hideo Yoshida
  • Publication number: 20090132887
    Abstract: A communication apparatus includes a storage unit, a row processing unit, and a column processing unit. The row processing unit repeatedly performs row processing to calculate a column-processing LLR for each column and each row in a check matrix. The column processing unit calculates a row-processing LLR for each column and each row of the check matrix, and repeatedly performs column processing to store in the storage unit the minimum value k of absolute values of the row-processing LLR. The row processing unit and the column processing unit alternately performs their processing. The row processing unit performs calculation using an approximate minimum value while the column processing unit cyclically updates the minimum k value of each row.
    Type: Application
    Filed: July 12, 2006
    Publication date: May 21, 2009
    Applicant: Mitsubishi Electric Corporation
    Inventors: Wataru Matsumoto, Rui Sakai, Hideo Yoshida, Yoshikuni Miyata
  • Publication number: 20090132954
    Abstract: A human-machine interface (HMI) application can be separated into a framework component and one or more view components. The framework component could be responsible for generating a window with components common across multiple ones of the view components. The framework component could also select one of the view components from a pool. Content can be loaded into the selected view component and presented in a display area of the window using the selected view component. The framework component can also detect a problem associated with the content presented to the user and/or the selected view component, such as an execution error. In addition, the framework component may take corrective action to resolve the problem, such as by reloading the selected view component (which could be done automatically). In this way, errors associated with the selected view component may not cause termination of or other difficulties with the framework component.
    Type: Application
    Filed: November 20, 2007
    Publication date: May 21, 2009
    Applicant: Honeywell International Inc.
    Inventor: David J. Cupitt
  • Publication number: 20090132889
    Abstract: Apparatus and methods store data in a non-volatile solid state memory device according to a rate-compatible code, such as a rate-compatible convolutional code (RPCC). An example of such a memory device is a flash memory device. Data can initially be block encoded for error correction and detection. The block-coded data can be further convolutionally encoded. Convolutional-coded data can be punctured and stored in the memory device. The puncturing decreases the amount of memory used to store the data. Depending on conditions, the amount of puncturing can vary from no puncturing to a relatively high amount of puncturing to vary the amount of additional error correction provided and memory used. The punctured data can be decoded when data is to be read from the memory device.
    Type: Application
    Filed: November 21, 2007
    Publication date: May 21, 2009
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: William H. Radke
  • Publication number: 20090132848
    Abstract: A system receives a program, allocates the program to a first software unit of execution (UE) and a second software UE, executes a first portion of the program with the first and second software UEs in parallel, and determines whether an error is detected during execution of the first portion of the program by the first and second software UEs. The system also sends a signal, between the first and second software UEs, to execute a second portion of the program when the error is detected in the first portion of the program, executes the second portion of the program with the first and second software UEs when the error is detected, and provides for display information associated with execution of the first portion and the second portion of the program by the first and second software UEs.
    Type: Application
    Filed: November 20, 2007
    Publication date: May 21, 2009
    Applicant: THE MATHWORKS, INC.
    Inventor: Jocelyn Luke Martin
  • Publication number: 20090132328
    Abstract: Methods, systems, and computer program products are provided for managing the trouble tickets of a network. One or more problems within the network along a plurality of lines of the network may be identified and trouble tickets may be opened for the problems. Each trouble ticket may be for dispatching a technician to the field to address the problem that is the subject of the trouble ticket. A certain amount of time may elapse from when the trouble ticket is opened and when the technician is dispatched. During that time the underlining problem may be resolved for various reasons. To detect the resolution of the problem before the dispatching of the technician, the line may be tested at a predetermined interval. If a test indicates that the problem has been resolved the trouble ticket is closed reducing the likelihood that a technician is dispatched for an already resolved problem.
    Type: Application
    Filed: November 19, 2007
    Publication date: May 21, 2009
    Applicant: Verizon Services Corp.
    Inventors: Sanal Kishore, Nagesha Saligrama, Nilesh Shroff, Kishorraju Budharaju
  • Publication number: 20090125786
    Abstract: According to one embodiment a computer system is disclosed. The computer system includes memory. The memory includes two or more rows, where each row has a plurality of memory devices. The computer system also includes a chipset. The chipset includes a detection/correction circuit to detect single and double symbol errors and correct single symbol errors for each memory row, and markers to maintain a log of errors within each memory row.
    Type: Application
    Filed: January 15, 2009
    Publication date: May 14, 2009
    Inventors: James W. Alexander, Thomas J. Holman, Mark A. Heap, Stanley S. Kulick
  • Publication number: 20090125791
    Abstract: Even when erroneous encoded data is inputted to a decoding device, the decoding device is recovered during one video frame period including a video frame time of the inputted data to enable decoding processing on a next video frame. The decoding device includes: a receiving section (1) for receiving encoded data (11) to output the encoded data corresponding to a video frame, outputting encoded data of a next frame in response to a decoding completion signal (14) to be received, and for transmitting an error signal (15) when the decoding completion signal is not received during a predetermined time; an image decoder (2) for decoding the encoded data (12) from the receiving section (1), transmitting the decoding completion signal (14) to the receiving section (1) when decoding is completed, and for stopping decoding processing in response to a reset signal (16) to be received; and an error recovery section (3) for outputting the reset signal (16) to the image decoder (2) when the error signal (15) is received.
    Type: Application
    Filed: September 13, 2005
    Publication date: May 14, 2009
    Inventors: Yoshiaki Katou, Koutarou Asai, Tokumichi Murakami
  • Publication number: 20090125787
    Abstract: An operation method of a MRAM of the present invention stores in memory arrays, error correction codes, each of which comprises of symbols, each of which comprises bits, and to which an error correction is possible in units of symbols. In the operation method, the symbols are read by using the reference cells different from each other. Moreover, when a correctable error is detected in a read data of the error correction code from data cells corresponding to an input address, (A) a data in the data cell corresponding to an error bit is corrected, for a first error symbol as an error pattern of one bit, and (B) a data in the reference cell that is used to read a second error symbol is corrected for a second error symbol as en error pattern of the bits.
    Type: Application
    Filed: October 17, 2006
    Publication date: May 14, 2009
    Inventors: Noboru Sakimura, Takeshi Honda, Tadahiko Sugibayashi
  • Publication number: 20090119541
    Abstract: The information processing device which recovers a domain developing a fault caused by added application and device driver while maintaining security and reliability includes a plurality of processors, wherein the plurality of processors form a plurality of domains according to processing contents to be executed, and the processors in different domains communicate with each other through a communication unit, and which further includes a recovery unit for executing, for a domain developing a fault, failure recovery processing based on a failure recovery request notified by the domain and a recovery condition set in advance for each domain.
    Type: Application
    Filed: February 23, 2006
    Publication date: May 7, 2009
    Applicant: NEC CORPORATION
    Inventors: Hiroaki Inoue, Junji Sakai, Tsuyoshi Abe, Masaki Uekubo, Noriaki Suzuki, Masato Edahiro
  • Publication number: 20090119452
    Abstract: Systems and methods for sharable tape devices are presented. More particularly, embodiments of a virtual tape server may automatically create a virtual tape device for an identified host such that hosts may interact with corresponding virtual tape devices. Thus, rather than having multiple hosts share a limited number of virtual tape devices, each host may interact with a virtual tape device corresponding only to that host (or a limited number of hosts), allowing substantially simultaneous interactions to take place between multiple hosts and multiple virtual tape devices and substantially alleviating the need of an application on a particular host to take into account other hosts or other applications when scheduling operations.
    Type: Application
    Filed: November 2, 2007
    Publication date: May 7, 2009
    Applicant: Crossroads Systems, Inc.
    Inventor: Brian J. Bianchi