Abstract: A computer implemented method, computer program product, and data processing system for predicting a future status of a memory leak. A first set of data including memory consumption data is received at a software bundle. The software bundle is operating in an open services gateway initiative environment. Responsive to a determination that a memory leak exists, the first set of data is analyzed to predict a future status of the memory leak. The future status is stored, as stored data, in a storage device.

Abstract: Technologies, systems and methods for code path analysis of an executable including: generating call graphs and control flow graphs of selected functions in the executable, and instrumenting the selected functions to provide for logging of path trace information for the selected functions upon execution of the instrumented executable, the path trace information usable for efficient system crash analysis and debugging. A stack trace from a crash dump may be utilized in the selection of the functions to analyze.

Abstract: The subject invention relates to systems and methods for automatic recovery from errors in a computing environment. A system is provided to facilitate failure recovery in the computing system. The system includes at least one driver component that enumerates at least one layer of a driver stack. A module associated with the driver component requests re-enumeration of the driver stack upon detection of an error in the computing system. When an error is detected by a driver or operating system component, a protocol can be established whereby a new copy of the driver's stack or system resources is re-enumerated in parallel to existing resources that may be in an unknown or error state. The new copy of the stack may allow the driver to become operational in lieu of the previous stack which can be reclaimed for other system uses over time.

Abstract: In a computing system comprising plural processor modules possessing plural processors, plural I/O devices serving as an interface of communication between the plural processor modules and external equipment, and a connection mechanism possessing plural switching units to which the plural processor modules and the plural I/O devices are coupled, the plural switching units possessed by the connection mechanism are managed as a network. In particular, the management information which defines each of plural paths by a line of two or more switching units among the plural switching units is acquired, the path status on the plural paths is grasped by analyzing the acquired management information, and the path status information on the grasped path status is created and outputted.

Abstract: In an application system of a liquid crystal display, for protecting transmissions between a master terminal and a slave terminal, effects caused by an unstable power source of the slave terminal have to be reduced to a lowest degree. When the application system is reset or under normal operations with the power source having a suddenly-decreased or suddenly-unstable voltage level, the transmission between the master terminal and the slave terminal have to be terminated, and related data of the terminated transmission is temporarily stored. When the voltage of the slave terminal is confirmed to reach to a stable voltage over a predetermined duration, the transmission may be restored by the stored data.

Abstract: A system module includes a plurality of processors, and a system controller that is connected to the processors via a first transmission line and relays a packet from each of the processors to another system module via a second transmission line in a multiprocessor system. The system controller includes a data transmission controller that, when part of packets constituting a series of data is not received normally from a processor due to a fault in the processor or the first transmission line, generates a supplement packet for a packet that has not been received normally and outputs the supplement packet to the second transmission line.

Abstract: A method is designed for controlling a total mixing system including a first mixing system and a second mixing system, which are operated in a linked manner. In the method, the first mixing system stores first scene data specifying contents of a mixing process matching a scene. The second mixing system stores second scene data specifying contents of a mixing process matching a scene. The first mixing system transmits a scene recall request to the second mixing system when a recall event of the first scene data occurs. The second mixing system transmits back a recall enabling response to the first mixing system after receipt of the scene recall request. The first mixing system reconstructs the contents of the mixing process on the basis of the first scene data after the reception of the recall enabling response. The second mixing system reconstructs the contents of the mixing process on the basis of the second scene data after the transmission of the recall enabling response.

Abstract: A device that is communicably connected to each of three or more nodes constituting a cluster system holds resource information, which is information relating to a resource used by an application, in relation to each of the three or more nodes. The device receives resource condition information indicating variation in the condition of the resource from each node, updates the resource information on the basis of the received resource condition information, determines a following active node on the basis of the updated resource information, and notifies at least one of the three or more nodes of the determined following active node.

Abstract: A system and method of recovering from errors in a data processing system. The data processing system includes one or more processor cores coupled to one or more memory controllers. The one or more memory controllers include at least a first memory interface coupled to a first memory and at least a second memory interface coupled to a second memory. In response to determining an error has been detected in the first memory, access to the first memory via the first memory interface is inhibited. Also, the first memory interface is locally restarted without restarting the second memory interface.

Abstract: A method for computer-assisted conversion of mathematical statements from one data format to another and an apparatus for carrying out the method are particularly useful for computer recognition of visual images of mathematical statements. There are difficulties in converting a mathematical statement perfectly from, say, a hand-written document into a mathematical computer code, especially if scanning and recognition software is used. Errors may also occur where electronic documents are transmitted over noisy communications channels.

Abstract: An apparatus includes a memory including a controller for initializing the memory, the controller storing a first data including a first code for correcting a first error of the first data, to the memory when initializing, and a memory controller controlling a data transmission to the memory, the memory controller being connected to the memory. The memory controller includes a code generation circuit storing a second data including a second code, to the memory after the initializing, the second code including an address parity for detecting an address causing a second error of the second data in said memory.

Abstract: A failure recovery framework to be used in cooperative data stream processing is provided that can be used in a large-scale stream data analysis environment. Failure recovery supports a plurality of independent distributed sites, each having its own local administration and goals. The distributed sites cooperate in an inter-site back-up mechanism to provide for system recovery from a variety of failures within the system. Failure recovery is both automatic and timely through cooperation among sites. Back-up sites associated with a given primary site are identified. These sites are used to identify failures within the primary site including failures of applications running on the nodes of the primary site. The failed applications are reinstated on one or more nodes within the back-up sites using job management instances local to the back-up sites in combination with previously stored state information and data values for the failed applications.

Abstract: In a printer connected to a network, email appended with link information is prepared for enabling an administrator to access information about the printer network terminal. The email is transmitted to the administrator terminal at a predetermined timing. Then, the administrator terminal accesses the information based on the link information appended to the email. As such, when a problem occurs in the printer, operations for resolving the problem can be quickly undertaken by the administrator.

Abstract: A convolutional encoder and the encoding method thereof, wherein the encoding method includes steps of: generating convolutional code according to the predefined criteria and with reference to the encoder's predefined convolutional encoding rate and constraint length; processing the data to be transmitted by using the convolutional code so that the coded data are suitable for propagation in multipath fading channel with Rayleigh fading, wherein the predefined criteria is to maximize the sum of Euclidean distance between each branch along the shortest error event path and each corresponding branch along the correct decoding path, and the shortest error event path is the decoding path having the minimum branches of non-zero Euclidean distance compared with the correct decoding path.

Abstract: An apparatus includes at least one load, a control circuit, and a power supplying apparatus including a control-use power supply part, at least one load-use power supply part, and a power supply control part. The control-use power supply part supplies first electric power to the control circuit, and stops supplying the first electric power and outputs a first detection signal when detecting a first abnormal operation state. The at least one load-use power supply part supplies second electric power to the respective at least one load, and stops supplying the second electric power and outputs a second detection signal when detecting a second abnormal operation state. The power supply control part causes the control-use power supply part to stop supplying the first electric power according to the first detection signal, and causes the at least one load-use power supply part to stop supplying the second electric power according to the second detection signal.

Abstract: The present invention relates to the architecture and operation of computer hardware memory logic, and in particular to a method and respective system for verifying hardware memory logic, wherein an Error Correction Code (ECC) is used for correcting single-bit or multi-bit errors when the ECC-bits cannot be accessed directly for a read or write process. The system and process employs the selection of data patterns that produce check bits that are all ones to ferret out errors in the ECC circuitry.

Abstract: The present invention is related to a method and apparatus for ECC (error code correction). The method of ECC includes a first directional first decoding, a first directional second decoding, a second directional first decoding, a second directional second decoding, wherein the error tolerant ability of first directional second decoding is greater than that of the first directional first decoding, and the error tolerant ability of second directional second decoding is greater than that of the second directional first decoding.

Abstract: In a DR system, from the viewpoint of device cost, when search is not carried out, a physical application where log recovery is available by inexpensive DB appliance server is adopted. Further, a local mirror operation at a secondary site is not carried out. Furthermore, from the viewpoint of operation, by a log apply function unit, the tendencies of a log application and operations are monitored, and a search process is accepted according to the progress conditions of the log application. When the log application does not catch up sufficiently, the search is not accepted. Moreover, when a consistency guarantee of a secondary DB is made, not transactions in process at the moment of search instruction are undone (rolled back), but only transactions in process at the moment of a search instruction are redone (rolled forward).

Abstract: An approach to dividing syndrome calculations into two steps and serially processing them requires a long time for the syndrome calculations with respect to an entire decoding process. Therefore, there is disclosed an error correction decoding circuit for a playing signal having a code sequence having a decoding unit generating first decoded signal and second decoded signal based on the code sequence and an error correction unit performing error correction for the second signal in response to the first signal.

Abstract: A few inexpensive hardware facilities are incorporated in a tightly synchronized cross checked design. These facilities allow initialization software to quickly bring the two processors to the same state by rapid, repeated resets and execution of the initialization software. The resets are done in a way as to be transparent to the rest of the system and to the end user.

Abstract: Provided is a hybrid flash memory device, a memory system, and a method of controlling errors. The hybrid flash memory device includes a data storage block with first and second data storage regions of flash memory cells, and error control block implementing first and second error control schemes, such that a data access operation directed to data stored in the first data storage region selects the first error control scheme, and a data access operation directed to data stored in the second data storage region selects the second error control scheme.

Abstract: The updating of only some memory locations in a multiple computer environment in which at least one applications program (50) executes simultaneously on a plurality of computers M1, M2 . . . Mn each of which has a local memory, is disclosed. Memory locations (A, B, D, E, X) in said local memory are categorized into two groups. The first group of memory locations (X1, X2, . . . Xn, A1, A2, . . . An) are each present in other computers. The second group of memory locations (B, E) are each present only in the computer having the local memory including the memory location. Changes to the contents of memory locations in the first group only are transmitted to all other computers. A computer failure detection mechanism is disclosed to prevent updating of any first group memory locations of any failed computer.

Abstract: At a stage of compiling of a source code, range information of a variable that a pointer points and information for a failure recovering are installed into the pointer variable. Since failure recovering information can also be acquired when an illegal pointer access is detected based on range information, a recovering processing suitable for data that has caused the failure is performed according to the failure recovering information. By relating the range information and the failure recovering information with the data address, a data type of a memory area at the failure location can be specified using the failure recovering information (UPPER, LOWER, and FIXED).

Abstract: A method includes receiving payload data from a data source at error correction code (ECC) logic, where the ECC logic is adapted to process a block of data of a particular size via a plurality of stages. The ECC logic is initialized to a selected stage of the plurality of stages. The selected stage includes an initial value and an initial number of cycles. The initial value and the initial number of cycles are related to a number of symbols of padding data corresponding to a difference in size between the payload data and the block of data. The selected stage is related to a state of the ECC logic as if the number of symbols of padding data had already been processed by the ECC logic. The payload data is processed via the ECC logic beginning with the selected stage to produce parity data related to the payload data.

Abstract: A method for detecting fault in a next generation network includes: establishing a tool set and a corresponding command set for detecting whether the network is connective and detecting a range of network fault; creating dynamically in a PROXY an address mapping table storing a correspondence relationship between a user identifier userid and address information of a user terminal; and upon occurrence of a fault in the network, obtaining the address information of the user terminal from the address mapping table according to the userid of the user terminal probed currently, executing the set of command according to the address information, and probing connectivity of the network between the PROXY and the user terminal. The problem that the network address transform (NAT) device and the firewall cannot be traversed may be avoided, and the fault point or range may be detected accurately in the NGN where a fault occurs.

Abstract: Whether the comparison value of temporarily stored data which is read out from a flash memory by a host system exceeds a threshold value related to a bit error or not is checked, and if the comparison value exceeds the threshold value, the temporarily stored data which is read out is rewritten into the flash memory. If the temporarily stored data has an error, the error is corrected by an error correction part and then the data is rewritten. The threshold value includes, e.g., the number of readouts, the number of bit errors and the number of accumulated occurrences of bit errors. The present invention is suitable for prevention of bit errors due to read disturb and can recover the bit data which changes with time, and therefore makes it possible to improve the reliability of the flash memory by preventing occurrence of bit errors.

Abstract: Method, apparatus and system for isolating input/output adapter error domains in a data processing system. Errors occurring in one input/output adapter are isolated from other input/output adapters of the data processing system by functionality in a host bridge that connects the input/output adapters to a system bus of the data processing system, thus permitting the use of low cost, industry standard switches and bridges external to the host bridge.

Abstract: An input/output (I/O) device fault processing method for executing, without contradiction, fault recovery processing of a physical I/O device which is commonly used or shared by a plurality of virtual computers in such a way that no influence is exerted on a virtual computer which does not presently use the shared I/O device is disclosed. A hypervisor performs fault monitoring of the physical I/O device. Upon occurrence of an operation failure, this failure is detected and notified to a virtual management computer. In responding to receipt of the notice, the virtual management computer performs the fault recovery processing of the physical I/O device.

Abstract: Methods and apparatus to configure process control system inputs and outputs are disclosed. A disclosed example method comprises obtaining a tag of a process control device from the input/output device, and associating the process control device with a process control module based on the obtained tag.

Abstract: A method and apparatus for fault recovery of on a parallel computer system from a soft failure without ending an executing job on a partition of nodes. In preferred embodiments a failed hardware recovery mechanism on a service node uses a heartbeat monitor to determine when a node failure occurs. Where possible, the failed node is reset and re-loaded with software without ending the software job being executed by the partition containing the failed node.

Abstract: Error correction coding is provided for codeword headers in a data tape format, such as a Linear Tape-Open, Generation 4 (LTO-4) data tape format. The data tape format defines a codeword quad as having first and second codeword headers interleaved with first and second codeword pairs, each codeword header comprising N bytes Ck=C0, C1, . . . , CN?2, CN?1 wherein K bytes C0-CK?1 of the first and second headers in a codeword quad differ such that if one is known the other can be inferred. Each header byte Ck of a codeword quad is redefined as comprising two interleaved (M/2)-bit nibbles, ek, ok. For each header, nibbles ek-eN?1 and nibbles ok-oN?1 are generated as a function of nibbles, e0-EK?1 and o0-oK?1, respectively. A codeword is assembled with the redefined headers the codeword quad is then recorded onto a recording medium.

Abstract: A system for managing a cluster of nodes, the cluster comprising a plurality of groups of nodes, each node being associated with a vote, the system further comprising an arbitration device, the arbitration device being associated with a number of votes dependent on the number of nodes in the cluster, each node further being associated with a cluster manager, one of the cluster managers for each group being operable: if the group is in communication with the arbitration device, to determine whether the group has the greatest number of votes, including the votes of the arbitration device; if the arbitration device is operative, but the group is not in communication with the arbitration device, to determine whether the group meets the quorum without adjusting the quorum; and if the arbitration device is not operative, to determine whether the group meets the quorum after adjusting the quorum.

Abstract: In one aspect, the present invention features techniques for generating a repair solution for a memory having a set of IOs including a plurality of main IOs and a plurality of redundant IOs. For example, techniques are provided for selecting a mapping between input/output ports of the memory and a subset of the memory's IOs. In particular, techniques are provided for configuring a plurality of multiplexors to implement the selected mapping by establishing electrical connections between the subset of IOs and the memory input/output ports. The subset of IOs may include one or more of the plurality of redundant IOs which effectively replace one or more defective ones of the main IOs. The plurality of multiplexors may be configured by generating one or more thermometer codes which encode the identities of any defective main IOs and which serve as selection inputs to the plurality of multiplexors.

Abstract: A method or device handles memory management faults in a device having a digital signal processor (“DSP”) and a microprocessor. The DSP includes a memory management unit (“DSP MMU”) to manage memory access by the DSP, and the DSP and the microprocessor access shared physical memory. Upon the DSP executing an instruction attempting to access a virtual address wherein the virtual address is invalid, a page fault interrupt is generated by the DSP MMU. A microprocessor interrupt handler in the microprocessor is activated in direct response to the page fault interrupt. Thereafter in the microprocessor, a translation lookaside buffer (“TLB”) entry is created in the DSP MMU, which includes a valid mapping between the virtual address and a page of physical memory. After creating the TLB entry, the microprocessor indicates to the DSP that the access by the DSP of the virtual address is completed.

Abstract: An image forming apparatus includes a process execution unit which processes data input to a storage area by using the attribute of a process set in the storage area, an error event generation unit which generates an error event to execute an error process when an error is detected during execution of the process by the process execution unit, and an error process execution unit which executes an error process associated with the storage area in accordance with the error event generated by the error event generation unit.

Abstract: A troubleshooting support device includes a keyword file storage unit in which keyword files holding keywords constituted with character strings contained in logs related to trouble that occurs in the substrate processing apparatus stored in advance, are stored. A keyword to be used for log search, selected from a keyword file specified based upon input information provided via an input unit, is set and also, a category-specific log file to be used for log analysis is set based upon input information provided via the input unit. Logs in the category-specific log file having been set are extracted and incorporated, and an analysis log file is created by sorting the extracted logs in time sequence. When the logs in the analysis log file are displayed at a display unit, a log containing the keyword having been set is located by searching through the analysis log file and is displayed in a highlighted display.

Abstract: A method of providing a power failure warning in a storage system includes partitioning early power off warning (EPOW) control logic of a storage enclosure to be symmetric with a power distribution network power domain. A power failure warning system for a storage system having a plurality of storage enclosures includes a power system control module coupled to a power supply for control and management of input power to the storage system. An output stage of the power supply is dedicated to a first virtual storage enclosure within one of the plurality of storage enclosures.

Abstract: A respective agent platform in network elements and producer-specific agents that are installed directly on platform or by way of agent proxies of agent providers are disclosed. The agents then receive raw information on arising operating errors by way of a defined interface of the agent platform, and, together with producer-specific information on the respective terminals or types of terminal that are known only to the respective producer, form corresponding compressed decision information for evaluating cases of error and/or for optimising reconfiguration decisions. The agents then provide the information for the network element or the network operator and/or the agent provider or the terminal producer, via the defined interface. This leads to a higher reliability of the interoperability of terminals and network elements in mobile radio networks including reconfigurable terminals.

Abstract: Security peer failure, in a network, is reduced by detecting peer liveness after a session has been established between a first and a second peer utilizing a protocol for setting up a security association. A protocol for detecting faults establishes a session between the first and second peer and the fault detecting session is associated with the security association session. Alternatively the security association may be registered with the fault detecting session. The purpose of registering the fault detecting session and the security association session is to determine liveness of the security association peer and when the fault detecting session fails, the peer is notified to take corrective action.

Abstract: A memory includes an array of memory cells and an error correction code circuit. The error correction code circuit is configured to receive a first portion of a first data word from an external circuit and a second portion of the first data word from the array of memory cells, combine the first portion and the second portion to provide the first data word, and encode the first data word for writing to the array of memory cells.

Abstract: A signal control circuit and a signal control apparatus that can reduce processing time and can send or receive correct data with reliability. When a data generation block outputs data, a data judgment block judges the number of changed bits by comparing each bit of the data output in the preceding session with the corresponding bit of the data to be sent in the current session and outputs position information indicating the position of each changed bit and the number of changed bits when the number of changed bits has reached a predetermined level. An output control block keeps a time period for stabilizing the change in value of the bit corresponding to the position information when the data is output, and directs a data storage block to send the value of the bit corresponding to the position information to an external circuit after the kept period has passed.

Abstract: An information processing apparatus according to the present invention includes a controller for dividing data into a plurality of divided-data; a plurality of storage units for storing the plurality of divided-data, respectively; a plurality of storage controllers for writing the divided-data into the corresponding storage unit or reading out the divided-data from the respective storage units; a plurality of history storage units for storing histories of the operation of the corresponding storage controllers, respectively; an error detector for detecting an error in the divided-data; an error correction controller for controlling correction of the error; and a plurality of history controller for controlling update of the histories in the corresponding history storage units, respectively upon correction of the error.

Abstract: The quality of data stored in a memory system is assessed by different methods, and the memory system is operated according to the assessed quality. The data quality can be assessed during read operations. Subsequent use of an Error Correction Code can utilize the quality indications to detect and reconstruct the data with improved effectiveness. Alternatively, a statistics of data quality can be constructed and digital data values can be associated in a modified manner to prevent data corruption. In both cases the corrective actions can be implemented specifically on the poor quality data, according to suitably chosen schedules, and with improved effectiveness because of the knowledge provided by the quality indications. These methods can be especially useful in high-density memory systems constructed of multi-level storage memory cells.

Abstract: Various methods and systems for implementing Reed Solomon multiplication sections from exclusive-OR (XOR) logic are disclosed. For example, a system includes a Reed Solomon multiplication section, which includes XOR-based logic. The XOR-based logic includes an input, an output, and one or more XOR gates. A symbol X is received at the input of the XOR-based logic. The one or more XOR gates are coupled to generate a product of a power of ? and X at the output, wherein ? is a root of a primitive polynomial of a Reed Solomon code. Such a Reed Solomon multiplication section, which can include one or more multipliers implemented using XOR-based logic, can be included in a Reed Solomon encoder or decoder.

Abstract: An exclusive OR (XOR) of user data (sector) 0, user data (sector) 1 and user data (sector) 2 is performed to provide virtual user data, thereby giving rise to a correlation of the sectors 0 to 2, and the virtual user data is appended with a second error correcting code C2 having a greater error correction capability than a first error correcting code C1, whereby an error uncorrectable with C1 is correctable with C2.

Abstract: An optical storage medium recording apparatus is provided a data preparing and ECC encoding circuit that both prepares the data by combining different categories of data into data sequences in accordance with a data layout on the optical storage medium and encodes the combined data. The encoded data is temporarily stored in a data buffer, and subsequently successively read out by a recording circuit for recording onto the optical storage medium according to the data layout. For a Blu-ray disc recording apparatus, the data preparing and ECC encoding circuit includes a LDC/BIS encoder for generating long distance error correction codes (LDC) and burst indicator subcodes (BIS) from the combined data to form LDC and BIS encoded data, which is temporarily stored in the data buffer. The recording circuit includes an interleave circuit for interleaving the LDC and BIS data to form physical clusters for recording on the disc.

Abstract: A digital broadcasting system including a transmitting system and a receiving system, and a method of processing data are disclosed. A method of processing data of a transmitting system includes sequentially grouping N number of columns (Kc) configured of A number of enhanced data bytes having information included therein, thereby creating a frame having a size of N (rows)*Kc (columns), wherein N and A are integers, encoding the created frame, and multiplexing and transmitting enhanced data included in the encoded frame and main data.

Abstract: In general, the disclosure describes techniques for detecting and correcting single or multiple occurrences of data error patterns. This disclosure discusses the generation and application of high-rate error-pattern-correcting codes to correct single instances of targeted error patterns in codewords, and to further correct a significant portion of multiple instances of targeted error patterns, with the least redundancy. In accordance with the techniques, a lowest-degree generator polynomial may be constructed that targets a set of dominant error patterns that make up a very large percentage of all observed occurrences of errors. The lowest-degree generator polynomial produces distinct, non-overlapping syndrome sets for the target error patterns.

Abstract: In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >=2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit. In another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.

Abstract: A fault-tolerant computer uses multiple commercial processors operating synchronously, i.e., in lock-step. In an exemplary embodiment, redundancy logic isolates the outputs of the processors from other computer components, so that the other components see only majority vote outputs of the processors. Processor resynchronization, initiated at predetermined time, milestones, and/or in response to processor faults, protects the computer from single event upsets. During resynchronization, processor state data is flushed and an instance of these data in accordance with processor majority vote is stored. Processor caches are flushed to update computer memory with more recent data stored in the caches. The caches are invalidated and disabled, and snooping is disabled. A controller is notified that snooping has been disabled. In response to the notification, the controller performs a hardware reset of the processors. The processors are loaded with the stored state data, and snooping and caches are enabled.