Abstract: A front-end compiler compiles source code into intermediate code, that may later be compiled into binary code. The source code defines an execution scope and includes a contract. When a contract is encountered at runtime of an execution scope, further execution of that execution scope is conditioned on whether a predicate associated with the contract is true. The front-end compiler operates so as to preserve the contract so that the contract continues to be semantically structured such that the predicate may be removed from the intermediate language code. The contract may thus continue to be understood by semantic analysis of the contract. Thus, the predicate may be understood by static analysis tools that operate on the intermediate code.

Abstract: In an embodiment, an address watch is established on a memory address while the execution of a first thread of a program is halted. In response to a second thread modifying memory contents at the memory address, encountering the address watch and halting, a determination is made whether a first variable in the program that represents the memory address is displayed on a user interface for the first thread. If the first variable in the program that represents the memory address is displayed on the user interface for the first thread, the value of the first variable is read and displayed on the user interface of the first thread.

Abstract: A method, computer program product and system for workload management for an Extract, Transform, and Load (ETL) system. A priority of each workload in a set of workloads is determined using a priority rule. In response to determining that the priority of a workload to be checked has a highest priority, it is indicated that the workload has the highest priority. It is determined whether at least one logical resource representing an ETL metric is available for executing the workload. In response to determining that the workload has the highest priority and that the at least one logical resource is available, it is determined that the workload is runnable.

Abstract: In developing applications for a plurality of node types, a meta-data definition of the application can be captured into an application definition module. The meta-data definition can describe the application for the plurality of node types. A code generation module can then automatically generate the application code for the plurality of node types. The code can be compiled per node type and the packaging necessary to deploy the application to the plurality of node types can also be automatically generated.

Abstract: The popularity of various application features is tracked, and applications are compiled or otherwise configured for optimization based on the use of the more popular features. More specifically, application features are mapped to corresponding sections of underlying code, and compiler directives are generated to direct a compiler to optimize the application for the performance of specific, application features, based on their popularity. This way, the application is compiled for use at an application feature level, rather than for size or speed generally. In another embodiment, the optimization is performed after compile time, by rearranging object code pages of an executable image, based on corresponding application feature popularity.

Abstract: A method for speculative object shapes comprises obtaining values for objects of a first and second shape, determining, by a processor and during runtime, a first speculative type for the first value and a second speculative type for the second value, generating, based on the first speculative type and the second speculative type, a shape tree comprising a first subtree for the first shape and a second subtree for the second shape, marking, by the processor, the first subtree as obsolete based on a determination that the first speculative type is incorrect and that the second shape is a super shape of the first shape, and transforming, in response to marking, the first object from the first shape to the second shape by: merging the first subtree into the second subtree.

Abstract: A method for allocating registers within a processing unit. A compiler assigns a plurality of instructions to a plurality of processing clusters. Each instruction is configured to access a first virtual register within a live range. The compiler determines which processing cluster in the plurality of processing clusters is an owner cluster for the first virtual register within the live range. The compiler configures a first instruction included in the plurality of instructions to access a first global virtual register.

Abstract: One aspect is a method for compiling optimization of an application and a compiler thereof. The method includes determining could-be-constant variables in source code of the application. Constant variables designated as final constant variables and values of the constant variables are obtained using the could-be-constant variables. The application is compiled using the constant variables and the values of the constant variables.

Abstract: A data processing apparatus and method are provided for handling exceptions, including processing circuitry configured to perform data processing operations in response to program code, said circuitry including exception control circuitry. A plurality of registers are provided including a first and second subsets of registers, and a data store. The data store includes a secure region and a less secure region, wherein the secure region is for storing data accessible by the processing circuitry when operating in a secure domain and not accessible by the processing circuitry when operating in a less secure domain. The exception control circuitry performs state saving of data from the first subset of registers before triggering the processing circuitry to perform an exception handling routine corresponding to the exception. Where background processing was performed by the processing circuitry in the secure domain, the exception control circuitry performs additional state saving of the data.

Abstract: Methods, devices, and systems for automatically determining how an application program may be partitioned and offloaded for execution by a general purpose applications processor and an auxiliary processor (e.g., a DSP, GPU, etc.) within a mobile device. The mobile device may determine the portions of the application code that are best suited for execution on the auxiliary processor based on pattern-matching of directed acyclic graphs (DAGS). In particular, the mobile device may identify one or more patterns in the code, particularly in a data flow graph of the code, comparing each identified code pattern to predefined graph patterns known to have a certain benefit when executed on the auxiliary processor (e.g., a DSP). The mobile device may determine the costs and/or benefits of executing the portions of code on the auxiliary processor, and may offload portions that have low costs and/or high benefits related to the auxiliary processor.

Abstract: A method and a device for migrating a source system configuration item: collecting through a telnet/ssh protocol channel established with a source system and a predefined shell script corresponding to the source system, a source system configuration item corresponding to a system configuration item identifier, wherein the system configuration item identifier is a predefined system configuration item identifier corresponding to the source system; comparing the collected source system configuration item with a preset default system configuration item to obtain a non-default system configuration item, wherein the non-default system configuration item is regarded as a system configuration item that needs to be migrated; querying a mapping relationship among a pre-system: the system configuration item and a key parameter value to obtain a destination system configuration item and the key parameter value; and performing migration configuration on a destination system through the telnet/ssh protocol channel establis

Abstract: A method and system are described for generating reference tables in object code which specify the addresses of branches, routines called, and data references used by routines in the code. In a suitably equipped processing system, the reference tables can be passed to a memory management processor which can open the appropriate memory pages to expedite the retrieval of data referenced in the execution pipeline. The disclosed method and system create such reference tables at the beginning of each routine so that the table can be passed to the memory management processor in a suitably equipped processor. Resulting object code also allows processors lacking a suitable memory management processor to skip the reference table, preserving upward compatibility.

Abstract: The present invention relates to a method and system for searching for parts of a computer program which affects a given symbol.

Abstract: Some embodiments of the present invention provide a system that implements a safepoint for a thread, which includes a compiler and a runtime environment. During compilation of an application to be executed by the thread, the compiler obtains a register to be associated with the thread and inserts safepoint code into the application, wherein the safepoint code includes an indirect load from a memory location stored in the register to the register. During execution of the application by the thread, the runtime environment writes a thread-specific value for the thread to the register, wherein the thread-specific value corresponds to an enabled value, a triggered value, or a disabled value. In these embodiments, executing the indirect load by the thread causes the thread to trap if the thread-specific value corresponds to the triggered value.

Abstract: Apparatus, systems, and methods for a compiler are described. One such compiler converts source code into an automaton comprising states and transitions between the states, wherein the states in the automaton include a special purpose state that corresponds to a special purpose hardware element. The compiler converts the automaton into a netlist, and places and routes the netlist to provide machine code for configuring a target device.

Abstract: A method is provided for controlling content playback by a terminal in a content delivery system. The method includes receiving streaming content from a service provider, the streaming content including zone information of each zone and an associated identifier of each zone for identifying a terminal's operation mode, determining the terminal's operation mode depending on the identifier, and controlling playback of the streaming content in a zone corresponding to the zone information according to the determined operation mode.

Abstract: A visualization tool that provides visibility of the functionality implemented with each system used by an institution(s) at code unit granularity can be used to overcome a variety of challenges that can occur in an environment with disparate systems. The visualization tool discovers and graphically displays functions/procedures/methods (“code units”) that satisfy a set of one or more criteria, as well as attributes of the discovered code units. Furthermore, the visualization tool can automatically provide visual annotations to identify targets for asset maintenance, targets to leverage for other systems, etc.

Abstract: A method for selecting a performance optimization level for program code segments (e.g., JavaScript code) embedded in interactive webpages according to the origin (e.g., domain) of the webpages is disclosed. The information on historic usage behavior on webpages from the same origin is collected. The historic usage behavior can be specific to the current user or an average or aggregated behavior across many users who have visited webpages from the same origin. The historic usage information is used to select an appropriate level of optimization to achieve the maximum performance improvement for the least amount of compilation cost. The selected optimization level can be adjusted over time based on a measure of actual performance improvement resulted from the different levels of optimization that had been carried out during prior visits.

Abstract: A method for transmitting data between a sender queue of a sender intermediate layer of a protocol stack and a receiver queue of a receiver intermediate layer of the protocol stack. The method includes receiving a data message from a sender messaging layer. The method also includes tagging the data message with a unique identifier. The method further includes writing the data message as a data window in the sender queue of the sender intermediate layer. The method additionally includes transmitting a front data window of the sender queue of the sender intermediate layer to the receiver queue of the receiver intermediate layer. The method also includes receiving a single receipt-acknowledgement message after a receiver transport layer of the protocol stack has received all of the front data window. The method further includes receiving a commit-acknowledgement message.

Abstract: A consistency assessment system for assessment of consistency of a software product includes a mapping module to obtain a plurality of configuration elements associated with the software product being developed, where each of the plurality of configuration elements influence software product development. Each of the plurality of configuration elements pertains to one of a plurality of element categories influencing software product development. The mapping module further identifies based on one or more identifiers, association of at least one configuration element from among the plurality of configuration elements with at least one another configuration element from among the plurality of configuration elements. Upon identification, an assessing module determines a requirement consistency index (RCI) for assessment of consistency of the software product. The RCI indicates an overall consistency of the software product.

Abstract: A method and apparatus to maintain a plurality of executables for a task in a device are described. Each executable may be capable of performing the task in response to a change in an operating environment of the device. Each executable may be executed to perform a test run of the task. Each execution can consume an amount of power under the changed operating environment in the device. One of the executables may be selected to perform the task in the future based on the amounts of power consumed for the test runs of the task. The selected one executable may require no more power than each of remaining ones of the executables.

Abstract: Processing circuitry can operate in a secure domain and a less secure domain. In response to an initial exception from background processing performed by the processing circuitry, state saving of data from a first subset of registers is performed by exception control circuitry before triggering an exception handling routine, while the exception handling routine has responsibility for performing state saving of data from a second subset of registers. In response to a first exception causing a transition from the secure domain from a less secure domain, where the background processing was in the less secure domain, the exception control circuitry performs additional state saving of data from the second set of registers before triggering the exception handling routine. In response to a tail-chained exception causing a transition from the secure domain to the less secure domain, the exception handling routine is triggered without performing an additional state saving.

Abstract: Systems and methods comprising a context analyzer configured to associate one or more Hypertext Transfer Protocol (HTTP) transactions, an extensible document parser configured to parse a document included in the one or more HTTP transactions; and a library of parser additions used by the context analyzer to generate context-full replay instructions.

Abstract: Embodiments provide call stacks for asynchronous programming. A set of all asynchronous call stacks is found by first identifying all threads and all outstanding tasks that have not yet been completed. Optionally, all outstanding continuation-delegates or lambdas that are in the windows queue waiting to be scheduled and/or all outstanding delegates or lambdas in a language-specific queue are also identified. Next, for each thread, identify whether it was invoked by a continuation-callback and, if so, find the corresponding task/promise. Next, given a task/promise, identify the logical parent task/promise. Optionally, given a delegate or lambda, identify its logical parent task/promise. The sequence of logical tasks/promises constitutes an asynchronous call stack in a program. Further information may optionally be retrieved to make the asynchronous call stack more useful. Finally, given a task/promise, identify the corresponding line number and location in source code.

Abstract: Disclosed are various embodiments for executing multiple Java applications in a single Java virtual machine. Each Java application is stored in a Java distribution and includes a plurality of classes. The executing includes translating an access to a non-shareable static field within one of the classes into an access to mapping data associated with the non-shareable static field. The executing further includes executing an initializer associated with the non-shareable static field when the mapping data is created.

Abstract: Automatic verification of determinism in structured parallel programs includes sequentially establishing whether code for each of a plurality of tasks of the structured parallel program is independent, outputting sequential proofs corresponding to the independence of the code for each of the plurality of tasks and determining whether all memory locations accessed by parallel tasks of the plurality of tasks are independent based on the sequential proofs.

Abstract: An optimizing compiler includes a vectorization mechanism that optimizes a computer program by substituting code that includes one or more vector instructions (vectorized code) for one or more scalar instructions. The cost of the vectorized code is compared to the cost of the code with only scalar instructions. When the cost of the vectorized code is less than the cost of the code with only scalar instructions, the vectorization mechanism determines whether the vectorized code will likely result in processor stalls. If not, the vectorization mechanism substitutes the vectorized code for the code with only scalar instructions. When the vectorized code will likely result in processor stalls, the vectorization mechanism does not substitute the vectorized code, and the code with only scalar instructions remains in the computer program.

Abstract: A method and apparatus for unified concurrency control in a Software Transactional Memory (STM) is herein described. A transaction record associated with a memory address referenced by a transactional memory access operation includes optimistic and pessimistic concurrency control fields. Access barriers and other transactional operations/functions are utilized to maintain both fields of the transaction record, appropriately. Consequently, concurrent execution of optimistic and pessimistic transactions is enabled.

Abstract: In one embodiment, an optimization hint may be included in a business process flow. An executable process may be generated from the business process flow where the optimization hint is included in the executable process. While executing the executable process, the runtime engine encounters an optimization hint and determines an optimization to perform. The optimization hint may be related to an aspect of a business process being orchestrated by the business process flow. The optimization is then performed while executing the executable process. For example, the runtime engine may start pre-processing the branch while the condition is being evaluated. If the condition evaluates such that the pre-processed branch should be executed, then the runtime engine has already started processing of that branch. The processing is thus optimized in that the runtime engine is not sitting idle while waiting for the condition to be evaluated.

Abstract: In one embodiment of the invention, a method is disclosed for modifying a pre-existing application program for multi-processing and/or distributed parallel processing. The method includes searching an application program for a computational loop; analyzing the computational loop to determine independence of the computational transactions of the computational loop; and replacing the computational loop with master code and slave code to provide master-slave execution of the computational loop in response to analyzing the computational loop to determine independence of the computational transactions of the computational loop. Multiple instances of the modified application program are executed to provide multi-processing and/or distributed parallel processing.

Abstract: The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.

Abstract: Techniques for implementing identification and management of unsafe optimizations are disclosed. A method of the disclosure includes receiving, by a managed runtime environment (MRE) executed by a processing device, a notice of misprediction of optimized code, the misprediction occurring during a runtime of the optimized code, determining, by the MRE, whether a local misprediction counter (LMC) associated with a code region of the optimized code causing the misprediction exceeds a local misprediction threshold (LMT) value, and when the LMC exceeds the LMT value, compiling, by the MRE, native code of the optimized code to generate a new version of the optimized code, wherein the code region in the new version of the optimized code is not optimized.

Abstract: In one embodiment, a machine-implemented method programs a heterogeneous multi-processor computer system to run a plurality of program modules, wherein each program module is to be run on one of the processors The system includes a plurality of processors of two or more different processor types. According to the recited method, machine-implemented offline processing is performed using a plurality of SIET tools of a scheduling information extracting toolkit (SIET) and a plurality of SBT tools of a schedule building toolkit (SBT). A program module applicability analyzer (PMAA) determines whether a first processor of a first processor type is capable of running a first program module without compiling the first program module. Machine-implemented online processing is performed using realtime data to test the scheduling software and the selected schedule solution.

Abstract: A method of generating an executable that operates as a compiler includes: receiving a unified input description containing syntax rules for both regular and context-free expressions and interspersed code; generating a common internal representation from the unified input description; checking regular expressions in the common internal representation; checking context-free expressions in the common representation; checking the interspersed code; and outputting the executable.

Abstract: Systems and methods are disclosed for optimizing applications per user. In one exemplary implementation, there is provided a method for optimizing an application by monitoring performance indicators of the application. Users are classified based on the performance indicators into sets. Behavior patterns are identified among user sets. Moreover, illustrative methods may include modifying configurable tuning variables of the application based on the behavior patterns.

Abstract: Partitioning programs between a general purpose core and one or more accelerators is provided. A compiler front end is provided for converting a program source code in a corresponding high level programming language into an intermediate code representation. This intermediate code representation is provided to an interprocedural optimizer which determines which core processor or accelerator each portion of the program should execute on and partitions the program into sub-programs based on this set of decisions. The interprocedural optimizer may further add instructions to the partitions to coordinate and synchronize the sub-programs as required. Each sub-program is compiled on an appropriate compiler backend for the instruction set architecture of the particular core processor or accelerator selected to execute the sub-program. The compiled sub-programs and then linked to thereby generate an executable program.

Abstract: During compilation, the interval bounds for a programmable culling unit are calculated if possible. For each variable, interval bounds are calculated during the compilation, and the bounds together with other metadata are used to generate an optimized culling program. If not possible, then an assumption may be made and the assumption used to compile the code. If the assumption proves to be invalid, a new assumption could be made and the code may be recompiled in some embodiments.

Abstract: State recovery methods and apparatus for computing platforms are disclosed. An example method includes inserting a first instruction into optimized code to cause a first portion of a register in a first state to be saved to memory before execution of a region of the optimized code; and maintaining a value indicative of a manner in which a second portion of the register in the first state is to be restored in connection with a state recovery from the optimized code.

Abstract: A device receives program code, generated via a technical computing environment (TCE) and including code that requires further processing to execute, and identifies one or more function calls or one or more object method calls in the program code. The device creates a control flow graph, for the program code, based on the one or more function calls or the one or more object method calls. The device transforms the control flow graph into a data flow graph. The data flow graph includes a representation for each of the one or more function calls or the one or more object method calls. The device generates hardware code based on the data flow graph, the hardware code including code that does not require further processing to execute.

Abstract: A method, computer, and computer program for speculatively optimizing a code. The method includes speculatively optimizing the code characterized by searching in a predetermined order in at least one dictionary; extracting a value associated with a symbol name from a dictionary using the symbol name as a key; performing optimization to replace a symbol in the code with the value; compiling the code to be compiled including some or all of the optimized code; comparing, in response to detection of a change related to one dictionary among at least one dictionary, an order m in the predetermined order of the dictionary with the detected change to an order n of the dictionary with the extracted value; and invalidating the optimized code in the compiled code associated with the dictionary having the detected change in response to the results from the orders comparison and the type of change.

Abstract: In one example, a device includes one or more processors configured to determine an allocated time for execution of an optimization pass for optimizing code for a software program, execute at least some instructions of the optimization pass on the code, and, in response to determining that an actual time for execution of the optimization pass has exceeded the allocated time for execution, preventing execution of subsequent instructions of the optimization pass.

Abstract: A method and an apparatus to execute a code with value profiling are described. The code may include an access to an untyped variable. During the execution, runtime values of the untyped variable may be randomly inspected. A value profile may be established to predict one or more expected types of future runtime values for the untyped variable. The code may be recompiled according to the value profile to optimize the access of the untyped variable for the future runtime values.

Abstract: The technologies provided herein relate to protecting the integrity of original code that has been optimized. For example, a processor may perform a fetch operation to obtain specified code from a memory. During execution, the code may be optimized and stored in a portion of the memory. The processor may obtain the optimized code from the portion of the memory. An entry of a first table may be modified to indicate a relationship between the particular code and the optimized code. One or more entries of a second table may be modified to specify the one or more physical memory locations. Each of the one or more entries of the second table may correspond to the entry of the first table. The processor may execute the optimized code when each of the one or more entries of the second table are valid.

Abstract: Methods and systems for optimizing generation of natively executable code from non-native binary code are disclosed. One method includes receiving a source file including binary code configured for execution according to a non-native instruction set architecture. The method also includes translating one or more code blocks included in the executable binary code to source code, and applying an optimizing algorithm to instructions in the one or more code blocks. The optimizing algorithm is selected to reduce a number of memory address translations performed when translating the source code to native executable binary code, thereby resulting in one or more optimized code blocks. The method further includes compiling the source code to generate an output file comprising natively executable binary code including the one or more optimized code blocks.

Abstract: Methods and systems for determining memory usage ratings for system processes and providing for display are described. An example method may include determining, by a processor, a memory usage value for a process configured to run on a computing device over a time period, and the memory usage value is indicative of an amount of memory of the computing device that the process uses while running. The method may also include determining a memory usage rating for the process based on the memory usage value and a run time for the process. The memory usage rating for the process indicates an amount of memory the process uses over the time period and the run time indicates how long the process runs during the time period. The method may also include providing for display, by the processor, a representation of the memory usage rating of the process over the time period.

Abstract: A system and method for optimization of code with non-adjacent loops. A compiler builds a node tree, which is not a control flow graph, that represents parent-child relationships of nodes of a computer program. Each node represents a control flow statement or a straight-line block of statements of the computer program. If a non-adjacent loop pair of nodes satisfy predetermined conditions, the compiler may perform legal code transformations on the computer program and corresponding node transformations on the node tree. These transformations may make adjacent this pair of loop nodes. The compiler may be configured to perform legal code transformations, such as head and tail duplication, code motion, and if-merging, in order to make adjacent these two loop nodes. Then loop fusion may be performed on this loop pair in order to increase instruction level parallelism (ILP) within an optimized version of the original source code.

Abstract: Methods and apparatuses associated with vectorization of scalar callee functions are disclosed herein. In various embodiments, compiling a first program may include generating one or more vectorized versions of a scalar callee function of the first program, based at least in part on vectorization annotations of the first program. Additionally, compiling may include generating one or more vectorized function signatures respectively associated with the one or more vectorized versions of the scalar callee function. The one or more vectorized function signatures may enable an appropriate vectorized version of the scalar callee function to be matched and invoked for a generic call from a caller function of a second program to a vectorized version of the scalar callee function.

Abstract: A device generates code with a technical computing environment (TCE) based on a model and information associated with a target processor, registers an algorithm with the TCE, automatically sets optimization parameters applied during generation of the code based on the algorithm, executes the generated code, receives feedback based on execution of the generated code, and uses the feedback to automatically update the optimization parameters and to automatically regenerate the code with the TCE until an optimal code is achieved for the target processor.

Abstract: One embodiment of the present invention sets forth a technique for extracting a memory address offset from a 64-bit type-conversion expression included in high-level source code of a computer program. The technique involves receiving the 64-bit type-conversion expression, where the 64-bit type-conversion expression includes one or more 32-bit expressions, determining a range for each of the one or more 32-bit expressions, calculating a total range by summing the ranges of the 32-bit expressions, determining that the total range is a subset of a range for a 32-bit unsigned integer, calculating the memory address offset based on the ranges for the one or more 32-bit expressions, and generating at least one assembly-level instruction that references the memory address offset.

Abstract: Methods to improve optimization of compilation are presented. In one embodiment, a method includes identifying one or more optimization speculations with respect to a code region and speculatively performing transformation on an intermediate representation of the code region in accordance with an optimization speculation. The method includes generating an advice message corresponding to the optimization speculation and displaying the advice message if the optimization speculation results in an improved compilation result.