Abstract: In one embodiment, input code is received having a plurality of functional elements that process data elements. At least one criterion for generated code is also received. A first intermediate representation of the input code is built that has a plurality of nodes that represent the functional elements. Block sizes are assigned to two or more nodes of a first intermediate representation. The first intermediate representation is modified to create a second intermediate representation that satisfies the at least one criterion, and organizes at least some of the nodes of the first intermediate representation based on the block sizes.

Abstract: A system and method for using inline stacks to improve the performance of application binaries is included. While executing a first application binary, profile data may be collected about the application that includes which callee functions are called from the application's callsites and the number of times each inline stack is executed. A context summary map may be created from the collected profile data which shows a summary of the total execution count of all instructions in the callee function for each callsite inlined in the application's normal binary. Using the context summary map, each function callsite's execution count may be compared with a predetermined threshold to determine if the function should be inlined. Then the application's profile may be annotated and a second application binary, an optimized binary, may be generated using the annotated profile.

Abstract: Approaches for replacing software components executing in a runtime environment with corresponding known-good software components are disclosed. In some implementations, at least a first event indicating that at least a first software component executing in the runtime environment should be replaced may be determined. The first event may be determined without respect to whether the first software component has been compromised or potentially compromised. At least a second software component corresponding to the first software component may be obtained from a component repository that is separate from the runtime environment. The first software component may be replaced with the second software component based on the first event such that the second software component is available for use in the runtime environment after the first event and the first software component is no longer available for use in the runtime environment after the first event.

Abstract: A method and an apparatus that modify pointer values pointing to typed data with type information are described. The type information can be automatically checked against the typed data leveraging hardware based safety check mechanisms when performing memory access operations to the typed data via the modified pointer values. As a result, hardware built in logic can be used for a broad class of programming language safety check when executing software codes using modified pointers that are subject to the safety check without executing compare and branch instructions in the software codes.

Abstract: A computer implemented method entails identifying code regions in an application from which offloadable tasks can be generated by a compiler for heterogenous computing system with processor and accelerator memory, including adding relaxed semantics to a directive based language in the heterogenous computing for allowing a suggesting rather than specifying a parallel code region as an offloadable candidate, and identifying one or more offloadable tasks in a neighborhood of code region marked by the directive.

Abstract: A computer-implemented method for generating one or more build system build files using a unified build system configuration file includes: receiving the unified build system configuration file in a computer system, the unified build system configuration file comprising at least one platform-independent build system configuration; generating, using the computer system, at least one platform-specific build system configuration from the at least one platform-independent build system configuration; selecting at least one template for the unified build system configuration file, the template selected from among templates corresponding to each of multiple platforms; generating the one or more build system build files for at least one of the multiple platforms using the platform-specific build system configuration and the selected template; and providing the generated one or more build system build files in response to the unified build system configuration file.

Abstract: An apparatus having a transactional memory enabling exclusive control to execute a transaction. The apparatus includes: a first code generating unit configured to interpret a program, and generate first code in which a begin instruction to begin a transaction and an end instruction to commit the transaction are inserted before and after an instruction sequence including multiple instructions to execute designated processing in the program; a second code generating unit configured to generate second code at a predetermined timing by using the multiple instructions according to the designated processing; and a code write unit configured to overwrite the instruction sequence of the first code with the second code or to write the second code to a part of the first code in the transaction.

Abstract: Partitioned global address space (PGAS) programming language source code is retrieved by an executed PGAS compiler. At least one shared memory array access indexed by an affine expression that includes a distinct thread identifier that is constant and different for each of a group of program execution threads targeted to execute the PGAS source code is identified within the PGAS source code. It is determined whether the at least one shared memory array access results in a local shared memory access by all of the group of program execution threads for all references to the at least one shared memory array access during execution of a compiled executable of the PGAS source code. A direct memory access executable code is generated for each shared memory array access determined to result in the local shared memory access by all of the group of program execution threads.

Abstract: Embodiments include systems and methods for reducing instruction cache miss penalties during application execution. Application code is profiled to determine “hot” code regions likely to experience instruction cache miss penalties. The application code can be linearized into a set of traces that include the hot code regions. Embodiments traverse the traces in reverse, keeping track of instruction scheduling information, to determine where an accumulated instruction latency covered by the code blocks exceeds an amount of latency that can be covered by prefetching. Each time the accumulated latency exceeds the amount of latency that can be covered by prefetching, a prefetch instruction can be scheduled in the application code. Some embodiments insert additional prefetches, merge prefetches, and/or adjust placement of prefetches to account for scenarios, such as loops, merging or forking branches, edge confidence values, etc.

Abstract: Processes in a message passing system may be launched when messages having data patterns match a function on a receiving process. The function may be identified by an execution pointer within the process. When the match occurs, the process may be added to a runnable queue, and in some embodiments, may be raised to the top of a runnable queue. When a match does not occur, the process may remain in a blocked or non-executing state. In some embodiments, a blocked process may be placed in an idle queue and may not be executed until a process scheduler determines that a message has been received that fulfills a function waiting for input. When the message fulfills the function, the process may be moved to a runnable queue.

Abstract: Different numbers of delay slots are assigned by a compiler/scheduler to each different type of jump operation in a pipelined processor system. The number of delay slots is variable and kept to the minimum needed by each type of jump operation. A compatible processor uses a corresponding number of branch delay slots to exploit the difference in predictability of different types of branch or jump operations. Different types of jump operations resolved their target addresses in different numbers of delay slots. As a result, the compiler/scheduler is able to generate more efficient code than for a processor with a fixed number of delay slots for all jump types, resulting in better processor performance.

Abstract: Embodiments are directed to implementing a generic SIMD data type in software code. In an embodiment, a computer system accesses a portion of software code that includes an algorithm with a generic SIMD data type that includes a variable number of elements. The algorithm with the generic SIMD data type is to be processed by a specific processor that includes various specific hardware features. The computer system determines at runtime a portion of customized processor-specific code that is to be used with the specified processor based on the generic SIMD data type, wherein the runtime determination resolves the number of elements that are to be used with the specified processor. The computer system also processes the software code including the algorithm with the generic SIMD data type using the determined, customized processor-specific code.

Abstract: Various arrangements for reducing a size of a Business Process Execution Language (BPEL) data blob for storage may be presented. One or more dehydration points within compiled BPEL code may be identified. A liveness analysis for the one or more dehydration points may be performed. At each of the one or more dehydration points, one or more live variables from a set of variables may be identified. An optimization data structure may be created for each dehydration point identifies the one or more live variables.

Abstract: A static branch prediction method and code execution method for a pipeline processor, and a code compiling method for static branch prediction, are provided herein. The static branch prediction method includes predicting a conditional branch code as taken or not-taken, adding the prediction information, converting the conditional branch code into a jump target address setting (JTS) code including target address information, branch time information, and a test code, and scheduling codes in a block. The code may be scheduled into a last slot of the block, and the JTS code may be scheduled into an empty slot after all the other codes in the block are scheduled. When the conditional branch code is predicted as taken in the prediction operation, a target address indicated by the target address information may be fetched at a cycle time indicated by the branch time information.

Abstract: The present invention relates to application program logs. In particular, the invention relates to a method and a system in which an original log method of an application program is optimized and newly injected to the application program. According to one aspect of the present invention, there is provided a method for optimizing an application program log record, comprising: identifying an original log method of an application program; separating a character string parameter in the original log method into a constant part and a variable part; establishing a correspondence flag between the constant part and the variable part; constituting an optimized log method by the constant part, the variable part and the correspondence flag; and replacing the original log method with the optimized log method through a code injection. With the above method, the hard disk storage amount of the log record and the IO operation frequency can be reduced.

Abstract: A method and system for parallelization of sequential computer program code are described. In one embodiment, an automatic parallelization system includes a syntactic analyzer to analyze the structure of the sequential computer program code to identify the positions to insert SPI to the sequential computer code; a profiler for profiling the sequential computer program code by preparing call graph to determine dependency of each line of the sequential computer program code and the time required for the execution of each function of the sequential computer program code; an analyzer to determine parallelizability of the sequential computer program code from the information obtained by analyzing and profiling of the sequential computer program code; and a code generator to insert SPI to the sequential computer program code upon determination of parallelizability to obtain parallel computer program code, which is further outputted to a parallel computing environment for execution and the method thereof.

Abstract: A system comprises a plurality of computation units interconnected by an interconnection network.

Abstract: A device receives, via a technical computing environment, a program that includes a parallel construct and a command to be executed by graphical processing units, and analyzes the program. The device also creates, based on the parallel construct and the analysis, one or more instances of the command to be executed in parallel by the graphical processing units, and transforms, via the technical computing environment, the one or more command instances into one or more command instances that are executable by the graphical processing units. The device further allocates the one or more transformed command instances to the graphical processing units for parallel execution, and receives, from the graphical processing units, one or more results associated with parallel execution of the one or more transformed command instances by the graphical processing units.

Abstract: Techniques for optimizing data stream processing are provided. The techniques include employing a pattern, wherein the pattern facilitates splitting of one or more incoming streams and distributing processing across one or more operators, obtaining one or mote operators, wherein the one or more operators support at least one group-independent aggregation and join operation on one or more streams, generating code, wherein the code facilitates mapping of the application onto a computational infrastructure to enable workload partitioning, using the one or more operators to decompose each of the application into one or more granular components, and using the code to reassemble the one or more granular components into one or more deployable blocks to map the application to a computational infrastructure, wherein reassembling the one or more granular components to map the application to the computational infrastructure optimizes data stream processing of the application.

Abstract: Aspects of the disclosure provide a method for code compilation. The method includes receiving instructions of a loop code for compiling, allocating one or more registers to variables before compiling the instructions into a loop body for the loop code, and compiling the instructions into the loop body based on the allocated registers.

Abstract: In one embodiment, a decision tree is evaluated in interpreted mode while statistics are collected. The decision tree is then represented as source code, and each decision in the decision tree is annotated with instructions determined based on the collected statistics. The source code is compiled into machine code, and the machine code is optimized based on the instructions annotating each decision in the decision tree.

Abstract: A technique for compiling and running high-level program on heterogeneous computers may include partitioning a program code into two or more logical units, and compiling each of the logical units into one or more executable entities. At least some of the logical units are compiled into two or more executable entities, the two or more executable entities being different compilations of the same logical unit. The two or more executable entities are compatible to run on respective two or more platforms that have different architecture.

Abstract: A dynamic compiler program product, method, and device for sequentially compiling a partial computer program in a computer. The program product causes the computer to: acquire respective values of one or more pieces of current execution status information; read, from the shared pool, a list of the conditions associated with an executable instruction stream generated by compiling a partial program that is the same as a partial program to be compiled, and determine whether respective values of corresponding pieces of current execution status information satisfy the conditions. The program product causes the computer to further generate an executable instruction stream by compiling the partial program to be compiled on the condition that a result of determination made is negative.

Abstract: In general, techniques are described for performing a form of inline dead code elimination. An apparatus comprising a storage unit and a processor may implement these techniques. The storage unit stores two source files and a destination file. The processor copies a first one of the source files to the destination file. This first source file includes a reference to a portion of a second one of the source files. The processor then evaluates the destination file to determine whether the portion of the second source file referenced in the first source file is used by the destination file. Based on the determination that the portion of the second source file referenced in the first source file is used by the destination file, the processor selectively copies the portion of the second source file to the destination file to generate an updated destination file.

Abstract: A device initiates a technical computing environment (TCE), and receives, via the TCE, a program command that permits the TCE to access a graphical processing unit that is remote to the device, where the program command permits the TCE to seamlessly transfer data to the remote GPU. The device transforms, via the TCE, the program command into a program command that is executable by the remote GPU, and provides the transformed program command to the remote GPU for execution. The device also receives, from the remote GPU, one or more results associated with execution of the transformed program command by the remote GPU, and utilizes the one or more results via the TCE.

Abstract: Methods, apparatus and computer software product for source code optimization are provided. In an exemplary embodiment, a first custom computing apparatus is used to optimize the execution of source code on a second computing apparatus. In this embodiment, the first custom computing apparatus contains a memory, a storage medium and at least one processor with at least one multi-stage execution unit. The second computing apparatus contains at least two multi-stage execution units that allow for parallel execution of tasks. The first custom computing apparatus optimizes the code for parallelism, locality of operations and contiguity of memory accesses on the second computing apparatus. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.

Abstract: The present invention performs manipulations on the assembly file level. As a compiler outputs an assembly file, the assembly file may be inspected and modified before it is sent to the assembler. One or more of the following modifications may be made to the assembly file: rewrite certain symbols, scramble program symbols, reorganize declarations of global variables so that their layout and default values are known prior to linking, and identify initializer and de-initializer functions in order to make them callable through central initialization and de-initialization functions, respectively.

Abstract: A compiler generated static analysis of potential aliasing violations in a portion of code that is not in the current program view of the analysis. Source code in a current program view of the program code is processed to collect symbol definitions. The possible destinations of each symbol definition are computed. The set of symbol definitions in the current program view of the code that are accessible to the portion of the program code outside the current program view is evaluated. Each symbol definition is diagnosed based on the type of the symbol defined and the symbols which may be pointed-to by the symbol definitions.

Abstract: A software-to-hardware compiler is provided that generates hardware constructs in programmable logic resources. The programmable logic resources may be optimized in terms of being configured to make additional copies of regions on memory devices other than on the programmable logic resources (e.g., RAM). This facilitates multiple reads during a single clock cycle. Symbol set analysis is used to minimize the size of regions to allow for more efficient use of hardware resources.

Abstract: The present invention relates to a field of evaluating the performance of a Structure Query Language (SQL) in information system. In particular, the invention proposes system and method of integration of a tool in Software Development Life Cycle (SDLC) which assures performance of SQL by estimating an execution time and remote installation of the same in a cloud based testing services. So, it can be used to detect the queries which may not perform well in the production environment.

Abstract: Systems and methods for replacing inferior code segments with optimal code segments. Systems and methods for making such replacements for programming languages using Message Passing Interface (MPI) are provided. For example, at the compiler level, point-to-point code segments may be identified and replaced with all-to-all code segments. Programming code may include X10, Chapel and other programming languages that support parallel for loop.

Abstract: A system and method for compiling includes, for a parallelizable code portion of an application stored on a computer readable storage medium, determining one or more variables that are to be transferred to and/or from a coprocessor if the parallelizable code portion were to be offloaded. A start location and an end location are determined for at least one of the one or more variables as a size in memory. The parallelizable code portion is transformed by inserting an offload construct around the parallelizable code portion and passing the one or more variables and the size as arguments of the offload construct such that the parallelizable code portion is offloaded to a coprocessor at runtime.

Abstract: A method and an apparatus for receiving a first source code having a code block to update the first source code with multiple copies of the code block to protect against correlation attacks are described. The code block can perform one or more operations for execution based on the first source code. The operations can be performed via a random one of the copies of the code block. A second source code based on the updated first source code can be generated to be executed by a processor to produce an identical result as the first source code.

Abstract: In one embodiment, a decision tree is evaluated in interpreted mode while statistics are collected. The decision tree is then represented as source code, and each decision in the decision tree is annotated with instructions determined based on the collected statistics. The source code is compiled into machine code, and the machine code is optimized based on the instructions annotating each decision in the decision tree.

Abstract: The present invention provides a method and system for optimization of an intermediate representation in a graphical modeling environment. A first intermediate representation is provided. At least one optimization technique is applied to the first intermediate representation. A second intermediate representation is generated responsive to the application of the at least one optimization technique to the first intermediate representation.

Abstract: Exemplary embodiments of the present invention disclose a method and system for replacing an unevaluated input that is constant at runtime to a group of instructions that calculates an output and can not modify the unevaluated input with invocation code that calls evaluation code. In a step, an exemplary embodiment identifies a group of instructions with an unevaluated input that is constant at runtime that calculates an output and can not modify the unevaluated input. In another step, an exemplary embodiment identifies an unevaluated input to the group of instructions that is constant at runtime. In another step, an exemplary embodiment generates an evaluation code that evaluates the unevaluated input. In another step, an exemplary embodiment replaces the unevaluated input with an invocation code that invokes the evaluation code.

Abstract: Described is predicting cache locality in a multicore/multithreaded processing environment including when threads share cache data in a non-uniform interleaving manner. Thread execution traces are analyzed to compute a set of per-thread parameters that can then be used to predict cache miss rates for other cache sizes. In one aspect, a model is based upon a probability that the cache reuse distance will increase because of accesses by other threads, and another probability that the reuse distance will decrease because of intercept accesses by other threads to shared data blocks. Estimates of the number of shared data blocks, possibly shared data blocks and private data blocks are used in the computations.

Abstract: Source code is generated that includes one or more iterator-based expressions such as declarative queries. The source code is translated into an intermediate language that classifies operators making up the iterator-based expressions into classes based on whether the operators are aggregating, element-wise, or sink operators. The intermediate language, including the identified classes, is processed using an automaton to replace the iterator-based expressions with one or more equivalent non-iterator-based expressions. Where an iterator-based expression is nested, the nested expression is processed using an equivalent number of nested automatons. The resulting optimized source code may be compiled and executed using fewer virtual function calls than the equivalent non-optimized source code.

Abstract: A method for performing a neighbor-flipping transformation is provided. In one embodiment, a graph analysis program for computing a function relating to nodes in a directed graph is obtained and analyzed for neighborhood iterating operations, in which a function is computed over sets of nodes in the graph. For any detected neighborhood iterating operation, the method transforms the iterating operation by reversing the neighbor node relationship between the nodes in the operation. The transformed operation computes the same value for the function as the operation prior to transformation. The method alters the neighbor node relationship automatically, so that a user does not have to recode the graph analysis program. In some cases, the method includes construction of edges in the reverse direction while retaining the original edges in addition to performing the transformation.

Abstract: In one embodiment, a method includes identifying a byte swap operation, building a domain including the byte swap operation and other expressions, identifying domain entries and domain exits associated with the domain, determining that a benefit will be obtained by performing a swap of the domain, and responsive to the determination performing the swap of the domain, and storing the swapped domain in a storage medium. Other embodiments are described and claimed.

Abstract: In an embodiment, a system includes a processor including at least one core to execute operations of a loop that includes S stages. The system also includes stage insertion means for adding a delay stage to the loop to increase a lifetime of a corresponding register associated with a first variable of the loop and to delay storage of contents of the register. The system also includes a dynamic random access memory (DRAM). Other embodiments are described and claimed.

Abstract: An illustrative embodiment provides a computer-implemented method for an alternate type system for optimizing the evaluation and use of meta-template instantiations. The computer-implemented method obtains a source code, instantiates an element of the source code to form an instantiated element and identifies a meta-template within the instantiated element to form an identified meta-template. The computer-implemented method creates an entry for the identified meta-template in a first data structure, wherein the entry comprises a set of mapped entries, creates an associated entry in a second data structure linked to the entry comprising the set of mapped entries, wherein the associated entry represents the set of mapped entries, and uses the associated entry of the second data structure in combination with the entry of the first data structure.

Abstract: A method, system, and computer usable program product for on-demand monitoring of memory usage are provided in the illustrative embodiments. An indication of a memory leak in an application is detected where the application is operating in a data processing system and using a memory associated with the data processing system. An instruction to begin monitoring a memory usage of the application is received responsive to the detection. Responsive to receiving the instruction to begin, the memory usage of the application is monitored. An instruction to dump a data related to the monitoring is received and the data is dumped. An instruction to end the monitoring is received and the monitoring is ended. The detecting, the beginning, the dumping, and the ending may occur while the application remains in operation and while the application uses the memory. The memory leak is confirmed using the data.

Abstract: Embodiments of the invention may provide for collecting specified data each time that a call to a given method occurs, wherein a given call to the given method is associated with a set of arguments comprising one or more particular argument values for the given method, and the collected data includes an element uniquely identifying each of the particular argument values. The process may further include storing the collected data at a selected location, and selecting a call threshold for the given method, wherein the call threshold comprises a specified number of occurrences of the given call to the given method, when the program is running. The collected data may be selectively analyzed at the storage location, to determine whether an occurrence of the given call to the given method has exceeded the call threshold.

Abstract: Processing a dataflow program by a program development tool includes detecting a pair of actors defined by dataflow program instructions, wherein the pair of actors include a producer actor and a consumer actor, the producer actor supplying a data structure to the consumer actor via a path that comprises at least one connection and possibly also intervening other actors. An analysis is performed including analyzing one or more operations of the producer actor that involve the data structure and/or analyzing one or more operations of the consumer actor that involve the data structure. A result of the analysis is used as a basis for selecting a minimal amount of information from among a plurality of data handling possibilities concerning the data structure. A transformed program is produced in which the selected minimal amount of information is caused to be passed from the producer actor to the consumer actor.

Abstract: The present invention relates to a formal technique-based verification apparatus and method for verifying software-defined networking. In accordance with an embodiment, a formal verification apparatus for Software-Defined Networking (SDN), includes a formal language creation unit for collecting flow table information for an entire network topology in response to a request of a SDN control unit, and creating description code in a predefined formal language based on the collected flow table information. A Symbolic Transition Graph (STG) generation unit generates a symbolic transition graph using the created description code in the formal language. A verification execution unit performs verification by applying formal verification technology to the symbolic transition graph.

Abstract: There are provided methods and computer program products for generating code for an architecture encoding an extended register specification. A method for generating code for a fixed-width instruction set includes identifying a non-contiguous register specifier. The method further includes generating a fixed-width instruction word that includes the non-contiguous register specifier.

Abstract: There are provided methods and computer program products for generating code for an architecture encoding an extended register specification. A method for generating code for a fixed-width instruction set includes identifying a non-contiguous register specifier. The method further includes generating a fixed-width instruction word that includes the non-contiguous register specifier.

Abstract: Methods and systems for asynchronous offload to many-core coprocessors include splitting a loop in an input source code into a sampling sub-part, a many integrated core (MIC) sub-part, and a central processing unit (CPU) sub-part; executing the sampling sub-part with a processor to determine loop characteristics including memory- and processor-operations executed by the loop; identifying optimal split boundaries based on the loop characteristics such that the MIC sub-part will complete in a same amount of time when executed on a MIC processor as the CPU sub-part will take when executed on a CPU; and modifying the input source code to split the loop at the identified boundaries, such that the MIC sub-part is executed on a MIC processor and the CPU sub-part is concurrently executed on a CPU.

Abstract: Processing a dataflow program by a program development tool includes analyzing an actor defined by the dataflow program to identify original sequences of actions that can be reformulated to achieve greater execution parallelism while maintaining the same functionality as the original sequences. A processed dataflow program is produced comprising processed dataflow program instructions and decision point program instructions. The processed dataflow program instructions comprise alternative sequences of reformulated actions that achieve greater execution parallelism while maintaining the same functionality as the identified one or more original sequences. The decision point program instructions direct processing equipment to select and execute one or more of the alternative sequences of reformulated actions, wherein selection is based on state and token information in existence at the time of selection.