Abstract: Treatment of carbon-containing low-k dielectric with UV radiation and a reducing agent enables process-induced damage repair. Also, treatment with a reducing agent and UV radiation is effective to clean a processed wafer surface by removal of metal oxide (e.g., copper oxide) and/or organic residue of CMP slurry from the planarized surface of a processed wafer with or without low-k dielectric. The methods of the invention are particularly applicable in the context of damascene processing to recover lost low-k property of a dielectric damaged during processing, either pre-metalization, post-planarization, or both, and/or provide effective post-planarization surface cleaning to improve adhesion of subsequently applied dielectric barrier and/or other layers.
Type:
Grant
Filed:
December 23, 2009
Date of Patent:
July 31, 2018
Assignee:
Novellus Systems, Inc.
Inventors:
Bhadri Varadarajan, George A. Antonelli, Bart van Schravendijk
Abstract: The amount of water and hydrogen contained in an oxide semiconductor film is reduced, and oxygen is supplied sufficiently from a base film to the oxide semiconductor film in order to reduce oxygen deficiencies. A stacked base film is formed, a first heat treatment is performed, an oxide semiconductor film is formed over and in contact with the stacked base film, and a second heat treatment is performed. In the stacked base film, a first base film and a second base film are stacked in this order. The first base film is an insulating oxide film from which oxygen is released by heating. The second base film is an insulating metal oxide film. An oxygen diffusion coefficient of the second base film is smaller than that of the first base film.
Type:
Grant
Filed:
December 26, 2014
Date of Patent:
June 26, 2018
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
Abstract: A method is for forming a nitride or oxide film by plasma-assisted cyclic deposition, one cycle of which includes: feeding a first reactant, a second reactant, and a precursor to a reaction space where a substrate is placed, wherein the second reactant flows at a first flow ratio wherein a flow ratio is defined as a ratio of a flow rate of the second reactant to a total flow rate of gases flowing in the reaction space; and stopping feeding the precursor while continuously feeding the first and second reactants at a flow ratio which is gradually reduced from the first flow ratio to a second flow ratio while applying RF power to the reaction space to expose the substrate to a plasma. The second reactant is constituted by a hydrogen-containing compound or oxygen-containing compound.
Abstract: The present invention provides an organic light emitting device, a manufacturing method thereof and a display device. In the organic light emitting device provided by the present invention, a first inorganic thin film entirely covers a pre-encapsulation layer and an organic light emitting unit, and the first inorganic thin film has a denser molecular structure compared with the pre-encapsulation layer, thereby more effectively preventing water and oxygen from invading the organic light emitting unit via the pre-encapsulation layer to influence the service life of the organic light emitting unit.
Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, an interfacial layer formed over the substrate, and an insertion layer formed over the interfacial layer. The semiconductor structure further includes a gate dielectric layer formed over the insertion layer and a gate structure formed over the gate dielectric layer. The insertion layer and the gate dielectric layer may be metal oxides where the insertion layer has an oxygen coordination number greater than the gate dielectric layer.
Abstract: A technique capable of suppressing the generation of foreign matter in a process container involves a method of manufacturing a semiconductor device including: (a) supplying a source gas to a substrate in a process container; (b) supplying an inert gas to an inner wall of an opening of the process container at a first flow rate while performing (a); (c) supplying a reactive gas to the substrate; and (d) supplying the inert gas to the inner wall at a second flow rate lower than the first flow rate while performing (c).
Abstract: The semiconductor device includes a substrate, an epi-layer, a first etch stop layer, an interlayer dielectric (ILD) layer, a second etch stop layer, a protective layer, a liner, a silicide cap and a contact plug. The substrate has a first portion and a second portion. The epi-layer is disposed in the first portion. The first etch stop layer is disposed on the second portion. The ILD layer is disposed on the first etch stop layer. The second etch stop layer is disposed on the ILD layer, in which the first etch stop layer, the ILD layer and the second etch stop layer form a sidewall surrounding the first portion. The protective layer is disposed on the sidewall. The liner is disposed on the protective layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the liner.
Abstract: A metal oxide film including a crystal part and having highly stable physical properties is provided. The size of the crystal part is less than or equal to 10 nm, which allows the observation of circumferentially arranged spots in a nanobeam electron diffraction pattern of the cross section of the metal oxide film when the measurement area is greater than or equal to 5 nm? and less than or equal to 10 nm?.
Type:
Grant
Filed:
April 16, 2015
Date of Patent:
January 16, 2018
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
Abstract: A method of manufacturing a semiconductor device includes forming a film on a substrate by performing a cycle a predetermined number of times. The cycle includes non-simultaneously performing: forming a first layer by supplying a precursor gas including a chemical bond of a first element and carbon and a first catalyst gas to the substrate; exhausting the precursor gas and the first catalyst gas through an exhaust system; forming a second layer by supplying a reaction gas including a second element and a second catalyst gas to the substrate to modify the first layer; and exhausting the reaction gas and the second catalyst gas through the exhaust system. At least in a specific cycle, the respective gases are supplied and confined in the process chamber while closing the exhaust system in at least one of the act of forming the first layer and the act of forming the second layer.
Abstract: Methods, devices, and systems associated with oxide based memory can include a method of forming a resistive switching region of a memory cell. Forming a resistive switching region of a memory cell can include forming a metal oxide material on an electrode and forming a metal material on the metal oxide material, wherein the metal material formation causes a reaction that results in a graded metal oxide portion of the memory cell.
Type:
Grant
Filed:
January 7, 2015
Date of Patent:
December 26, 2017
Assignee:
Micron Technology, Inc.
Inventors:
D. V. Nirmal Ramaswamy, Gurtej S. Sandhu
Abstract: An electrostatic chuck apparatus is disclosed which can be prevented from being damaged or fractured when the temperature abruptly increases or decreases when plasma is irradiated on a plate-like specimen, the heater is heated, or the like, and can also prevent corrosion when a corrosive gas or plasma is provided. The electrostatic chuck apparatus has an electrostatic chuck portion 2 having a mounting plate 11 made of a corrosion-resistant ceramic, a supporting plate 12 which is integrated with the mounting plate 11 so as to support the mounting plate 11 and is made of an insulating ceramic having a larger thermal conductivity than the thermal conductivity of the corrosion-resistant ceramic, and an internal electrode for electrostatic adsorption 13 provided between the mounting plate 11 and the supporting plate 12; and a temperature-controlling base portion 3 which adjusts the electrostatic chuck portion 2 to a desired temperature.
Abstract: Disclosed are a cleaning composition for photolithography and a method of forming a photoresist pattern using the same. The cleaning composition, necessary for forming a photoresist pattern having a high aspect ratio, includes water and a compound represented by Chemical Formula 1 below: wherein R is H or OH, x is an integer selected from 1 to 100, y is an integer selected from 0 to 100, and z is an integer selected from 0 to 100. This cleaning composition is useful for forming a pattern using any of a variety of light sources, and also, even when it is difficult to form a fine pattern as desired using a photoresist alone, a fine pattern can be realized at a desired level of fineness and production costs can be reduced.
Type:
Grant
Filed:
June 14, 2016
Date of Patent:
November 28, 2017
Assignee:
YOUNG CHANG CHEMICAL CO., LTD
Inventors:
Seung Hun Lee, Seung Hyun Lee, Sang Woong Yoon, Gyeong Guk Ham
Abstract: A metal oxide film including a crystal part and having highly stable physical properties is provided. The size of the crystal part is less than or equal to 10 nm, which allows the observation of circumferentially arranged spots in a nanobeam electron diffraction pattern of the cross section of the metal oxide film when the measurement area is greater than or equal to 5 nm? and less than or equal to 10 nm?.
Type:
Grant
Filed:
June 9, 2015
Date of Patent:
November 28, 2017
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
Abstract: According to the invention there is provided a method of filling one or more gaps created during manufacturing of a feature on a substrate by providing a deposition method comprising; introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant; introducing a second reactant to the substrate with a second dose. The first reactant is introduced with a subsaturating first dose reaching only a top area of the surface of the one or more gaps and the second reactant is introduced with a saturating second dose reaching a bottom area of the surface of the one or more gaps. A third reactant may be provided to the substrate in the reaction chamber with a third dose, the third reactant reacting with at least one of the first and second reactant.
Type:
Grant
Filed:
July 28, 2016
Date of Patent:
November 7, 2017
Assignee:
ASM IP Holding B.V.
Inventors:
Viljami Pore, Werner Knaepen, Bert Jongbloed, Dieter Pierreux, Steven R. A. Van Aerde, Suvi Haukka, Atsuki Fukuzawa, Hideaki Fukuda
Abstract: A spalling process can be employed to generate a fracture at a predetermined depth within a high quality crystalline nitride substrate, such as a bulk GaN substrate. A first crystalline conductive film layer can be separated, along the line of fracture, from the crystalline nitride substrate and subsequently bonded to a layered stack including a traditional lower-cost substrate. If the spalled surface of the first crystalline conductive film layer is exposed in the resulting structure, the structure can act as a substrate on which high quality GaN-based devices can be grown.
Abstract: A metal oxide film including a crystal part and having highly stable physical properties is provided. The size of the crystal part is less than or equal to 10 nm, which allows the observation of circumferentially arranged spots in a nanobeam electron diffraction pattern of the cross section of the metal oxide film when the measurement area is greater than or equal to 5 nm? and less than or equal to 10 nm?.
Type:
Grant
Filed:
April 16, 2015
Date of Patent:
September 5, 2017
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
Abstract: Methods and compositions for depositing rare earth metal-containing layers are described herein. In general, the disclosed methods deposit the precursor compounds comprising rare earth-containing compounds using deposition methods such as chemical vapor deposition or atomic layer deposition. The disclosed precursor compounds include a cyclopentadienyl ligand having at least one aliphatic group as a substituent and an amidine ligand.
Type:
Grant
Filed:
June 9, 2016
Date of Patent:
July 18, 2017
Assignee:
American Air Liquide, Inc.
Inventors:
Venkateswara R. Pallem, Christian Dussarrat, Wontae Noh
Abstract: A method for forming an on-chip capacitor with complementary metal oxide semiconductor (CMOS) devices includes forming a first capacitor electrode between gate structures in a capacitor region while forming contacts to source and drain (S/D) regions in a CMOS region. Gate structures are cut in the CMOS region and the capacitor region by etching a trench across the gate structures and filling the trench with a dielectric material. The gate structures and the dielectric material in the trench in the capacitor region are removed to form a position for an insulator and a second electrode. The insulator is deposited in the position. Gate metal is deposited to form gate conductors in the CMOS region and the second electrode in the capacitor region.
Type:
Grant
Filed:
September 23, 2016
Date of Patent:
July 11, 2017
Assignee:
International Business Machines Corporation
Abstract: The embodiments herein focus on plasma enhanced atomic layer deposition (PEALD) processes. Conventional PEALD techniques result in films having high quality at the bottom and top of a feature, but low quality on the sidewalls. The disclosed embodiments achieve more uniform film quality as evidenced by more uniform wet etch rates and electrical properties throughout the film. The disclosed embodiments may use one or more of a relatively high deposition temperature, a relatively high RF power for generating the plasma, and/or relatively long RF plasma exposure duration during each cycle of the PEALD reaction.
Abstract: Provided are a method of generating plasma and a method of fabricating a semiconductor device including the method, which may improve selectivity in an etching process and minimize damage to layers. The method of generating plasma includes generating first plasma by supplying at least one first process gas into a first remote plasma source (RPS) and applying first energy having a first power at a first duty ratio, and generating second plasma by supplying at least one second process gas into a second RPS and applying second energy having a second power at a second duty ratio.
Type:
Grant
Filed:
July 13, 2015
Date of Patent:
June 20, 2017
Assignee:
Samsung Electronics Co., Ltd.
Inventors:
Gon-jun Kim, Sam Hyungsam Kim, Sangheon Lee
Abstract: The amount of water and hydrogen contained in an oxide semiconductor film is reduced, and oxygen is supplied sufficiently from a base film to the oxide semiconductor film in order to reduce oxygen deficiencies. A stacked base film is formed, a first heat treatment is performed, an oxide semiconductor film is formed over and in contact with the stacked base film, and a second heat treatment is performed. In the stacked base film, a first base film and a second base film are stacked in this order. The first base film is an insulating oxide film from which oxygen is released by heating. The second base film is an insulating metal oxide film. An oxygen diffusion coefficient of the second base film is smaller than that of the first base film.
Type:
Grant
Filed:
December 26, 2014
Date of Patent:
June 6, 2017
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
Abstract: Provided are methods for the deposition of films comprising SiCN and SiCON. Certain methods involve exposing a substrate surface to a first and second precursor, the first precursor having a formula (XyH3-ySi)zCH4-z, (XyH3-ySi)(CH2)(SiXpH2-p)(CH2)(SiXyH3-y), or (XyH3-ySi)(CH2)n(SiXyH3-y), wherein X is a halogen, y has a value of between 1 and 3, and z has a value of between 1 and 3, p has a value of between 0 and 2, and n has a value between 2 and 5, and the second precursor comprising a reducing amine. Certain methods also comprise exposure of the substrate surface to an oxygen source to provide a film comprising SiCON.
Abstract: A method of surface functionalization for high-k deposition is provided in several embodiments. The method provides interface layer growth with low effective oxide thickness and good nucleation behavior for high-k deposition. The method includes providing a substrate that is at least substantially free of oxygen on a surface of the substrate, forming an interface layer on the surface of the substrate by exposing the surface of the substrate to one or more pulses of ozone gas, modifying the interface layer by exposing the interface layer to one or more pulses of a treatment gas containing a functional group to form a functionalized interface layer terminated with the functional group, and depositing a high-k film on the functionalized interface layer.
Abstract: A cleaning method includes performing a first cleaning process of supplying a fluorine-based gas from a first nozzle heated to a first temperature and a nitrogen oxide-based gas from a second nozzle heated to a first temperature into a process chamber heated to the first temperature in order to remove on surfaces of members in the process chamber by a thermochemical reaction, changing in internal temperature of the process chamber to a second temperature higher than the first temperature, and performing a second cleaning process of supplying a fluorine-based gas from the first nozzle heated to the second temperature into the process chamber heated to the second temperature in order to remove substances remaining on the surfaces of the members in the process chamber after removing the deposits by the thermochemical reaction and to remove deposits deposited in the first nozzle by the thermochemical reaction.
Abstract: Corrosion resistant substrate supports and methods of making corrosion resistant substrate supports are provided herein. In some embodiments, a method of making corrosion resistant substrate supports includes exposing the substrate support disposed within a substrate processing chamber to a process gas comprising an aluminum containing precursor; and depositing an aluminum containing layer atop surfaces of the substrate support.
Type:
Grant
Filed:
May 30, 2014
Date of Patent:
January 24, 2017
Assignee:
APPLIED MATERIALS, INC.
Inventors:
Mei Chang, Chien-Teh Kao, Juno Yu-Ting Huang
Abstract: Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module.
Abstract: Methods of depositing boron and carbon containing films are provided. In some embodiments, methods of depositing B,C films with desirable properties, such as conformality and etch rate, are provided. One or more boron and/or carbon containing precursors can be decomposed on a substrate at a temperature of less than about 400° C. In some embodiments methods of depositing silicon nitride films comprising B and C are provided. A silicon nitride film can be deposited by a deposition process including an ALD cycle that forms SiN and a CVD cycle that contributes B and C to the growing film.
Abstract: Some embodiments relate to a method for semiconductor processing. In this method, a semiconductor wafer is provided. A surface region of the semiconductor wafer is probed to determine whether excess charge is present on the surface region. Based on whether excess charge is present, selectively inducing a corona discharge to reduce the excess charge. Other techniques are also provided.
Abstract: A substrate processing method can remove a part of a processing target film formed on a surface of a substrate W under a normal pressure atmosphere while suppressing an influence upon the substrate. A source material of the processing target film, which is decomposed by irradiating an ultraviolet ray thereto under an oxygen-containing atmosphere, is coated on the substrate W, and the processing target film is formed by heating the source material coated on the substrate W. Then, the substrate W having thereon the processing target film is placed within a processing chamber under the oxygen-containing atmosphere where a gas flow velocity is equal to or smaller than 10 cm/sec, and the part of the processing target film is removed by irradiating the ultraviolet ray to the substrate W.
Type:
Grant
Filed:
June 19, 2015
Date of Patent:
December 6, 2016
Assignee:
TOKYO ELECTRON LIMITED
Inventors:
Masatoshi Kaneda, Yuzo Ohishi, Keisuke Yoshida
Abstract: An improvement is achieved in the performance of a semiconductor device including a memory element. Over a semiconductor substrate, a gate electrode for the memory element is formed via an insulating film as a gate insulating film for the memory element. The insulating film includes first, second, third, fourth, and fifth insulating films in order of being apart from the substrate. The second insulating film has a charge storing function. The band gap of each of the first and third insulating films is larger than a band gap of the second insulating film. The band gap of the fourth insulating film is smaller than the band gap of the third insulating film. The band gap of the fifth insulating film is smaller than the band gap of the fourth insulating film.
Abstract: Methods of forming an electronic device comprise: (a) providing a semiconductor substrate comprising a porous feature on a surface thereof; (b) applying a composition over the porous feature, wherein the composition comprises a polymer and a solvent, wherein the polymer comprises a repeat unit of the following general formula (I): wherein: Ar1, Ar2, Ar3 and Ar4 independently represent an optionally substituted divalent aromatic group; X1 and X2 independently represent a single bond, —O—, —C(O)—, —C(O)O—, —OC(O)—, —C(O)NR1—, —NR2C(O)—, —S—, —S(O)—, —SO2— or an optionally substituted C1-20 divalent hydrocarbon group, wherein R1 and R2 independently represent H or a C1-20 hydrocarbyl group; m is 0 or 1; n is 0 or 1; and o is 0 or 1; and (c) heating the composition; wherein the polymer is disposed in pores of the porous feature. The methods find particular applicability in the manufacture of semiconductor devices for forming low-k and ultra-low-k dielectric materials.
Type:
Grant
Filed:
December 17, 2015
Date of Patent:
November 29, 2016
Assignees:
Dow Global Technologies LLC, Rohm and Haas Electronic Materials LLC
Inventors:
Jong Keun Park, Phillip D. Hustad, Emad Aqad, Mingqi Li, Cheng-Bai Xu, Peter Trefonas, III, James W. Thackeray
Abstract: A wireless power transmission system is provided for high power applications. The power transmission system is comprised generally of a charging unit configured to generate an alternating electromagnetic field and a receive unit configured to receive the alternating electromagnetic field from the charging unit. The charging unit includes a power source; an input rectifier; an inverter; and a transmit coil. The transmit coil has a spirangle arrangement segmented into n coil segments with capacitors interconnecting adjacent coil segments. The receive unit includes a receive coil and an output rectifier. The receive coil also has a spirangle arrangement segmented into m coil segments with capacitors interconnecting adjacent coil segments.
Type:
Grant
Filed:
May 14, 2014
Date of Patent:
November 15, 2016
Assignee:
The Regents Of The University Of Michigan
Inventors:
Chris Mi, Siqi Li, Trong-Duy Nguyen, Junhua Wang, Jiangui Li, Weihan Li, Jun Xu
Abstract: Disclosed is a process of annealing through silicon vias (TSVs) or other deeply buried metallic interconnects using a back side laser annealing process. The process provides several advantages including sufficient grain growth and strain relief of the metal such that subsequent thermal processes do not cause further grain growth; shorter anneal times thereby reducing cycle time of 3D device fabrication; and reduced pattern sensitivity of laser absorption.
Type:
Grant
Filed:
December 17, 2015
Date of Patent:
September 27, 2016
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventors:
Oleg Gluschenkov, Andrew J. Martin, Joyeeta Nag
Abstract: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate.
Abstract: Provided is a method for manufacturing a semiconductor device, in which a degradation of characteristics of a thin film transistor can be suppressed by performing plasma oxidation treatment on a gate insulating film containing nitrogen. An embodiment of the present invention is a method for manufacturing a semiconductor device comprising a thin film transistor including a gate electrode, a gate insulating film containing nitrogen, and a channel region in microcrystalline semiconductor films. The method includes the steps of performing plasma treatment on the gate insulating film in an oxidizing gas atmosphere containing hydrogen and an oxidizing gas containing an oxygen atom, and forming the microcrystalline semiconductor film over the gate insulating film. Formula (1), a/b?2, and Formula (2), b>0, are satisfied, where the amount of hydrogen and the amount of the oxidizing gas in the oxidizing gas atmosphere are a and b, respectively.
Type:
Grant
Filed:
March 29, 2012
Date of Patent:
July 26, 2016
Assignees:
Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
Abstract: In a particular illustrative embodiment, a method of fabricating a semiconductor device is disclosed that includes forming a metal layer over a device substrate, forming a via in contact with the metal layer, and adding a dielectric layer above the via. The method further includes etching a portion of the dielectric layer to form a trench area, and depositing a perpendicular magnetic tunnel junction (MTJ) structure within the trench area.
Abstract: A method for forming a semiconductor device includes forming a first dielectric layer overlying a substrate, forming at least a first opening in the first dielectric layer, forming a conformal dense layer lining the at least first opening in the first dielectric layer, forming a barrier layer overlying the conformal dense layer, forming a conductive feature in the at least first opening, removing a portion of the first dielectric layer between any two adjacent conductive features to form a second opening, wherein the second opening exposes the conformal dense layer between the two adjacent conductive features, and depositing between the two adjacent conductive features a second dielectric layer having an air gap formed therein.
Abstract: A substrate processing apparatus for processing a substrate comprises: a plurality of chuck pins each having an accommodating groove for accommodating a portion of peripheral part of the substrate, holding the substrate at a hold position in a horizontal posture by pressing inner faces of the accommodating grooves toward portions of peripheral part of the substrate; and a plurality of guide members, being disposed on or above the respective plurality of chuck pins, guiding process liquid discharged from the substrate to a surrounding area of the substrate; wherein each of the plurality of guide member includes: an inner-edge guide disposed at a position inward and above the accommodating groove; and an outer-edge guide disposed at a position level with or below the inner-edge guide and outward the chuck pin.
Abstract: A method of manufacturing an organic light-emitting display apparatus includes preparing a deposition target in which an organic light-emitting portion is formed on a substrate, forming a pre-encapsulation layer for encapsulating the organic light-emitting portion by using a facing target sputtering apparatus, and forming an encapsulation layer by performing a plasma surface process on the pre-encapsulation layer by using the facing target sputtering apparatus. The facing target sputtering apparatus includes a chamber in which a mounting portion for accommodating the deposition target is provided, a gas supply portion facing the mounting portion and supplying gas to the chamber, a first target portion and a second target portion disposed in the chamber and facing each other, and an induced magnetic field coil surrounding the exterior of the chamber.
Abstract: Provided is a method of forming a silicon nitride film on a surface to be processed of a target object, which includes: repeating a first process a first predetermined number of times, the process including supplying a silicon source gas containing silicon toward the surface to be processed and supplying a decomposition accelerating gas containing a material for accelerating decomposition of the silicon source gas toward the surface to be processed; performing a second process of supplying a nitriding gas containing nitrogen toward the surface to be processed a second predetermine number of times; and performing one cycle a third predetermined number of times, the one cycle being a sequence including the repetition of the first process and the performance of the second process to form the silicon nitride film on the surface to be processed.
Abstract: A device includes a semiconductor fin over a substrate, a gate dielectric on sidewalls of the semiconductor fin, and a gate electrode over the gate dielectric. A source/drain region is on a side of the gate electrode. A dislocation plane is in the source/drain region.
Abstract: A thin film having a high resistance to HF and a low dielectric constant is formed with high productivity. A method of manufacturing a semiconductor device, includes performing a cycle a predetermined number of times, the cycle including: (a) supplying a source gas containing a predetermined element, carbon and a halogen element and having a chemical bond between the predetermined element and carbon to a substrate; and (b) supplying a reactive gas including a borazine compound to the substrate, wherein the cycle is performed under a condition where a borazine ring structure in the borazine compound and at least a portion of the chemical bond between the predetermined element and carbon in the source gas are preserved to form a thin film including the borazine ring structure and the chemical bond between the predetermined element and carbon on the substrate.
Abstract: A thin film formation method to form an amorphous silicon film containing an impurity on a surface of an object to be processed in a process chamber that allows vacuum exhaust includes supplying a silane-based gas composed of silicon and hydrogen into the process chamber in a state that the silane-based gas is adsorbed onto the surface of the object without supplying an impurity-containing gas, supplying the impurity-containing gas into the process chamber to form the amorphous silicon film containing the impurity without supplying the silane-based gas, and performing the supplying of the silane-based gas and the supplying of the impurity-containing gas alternately and repeatedly such that the impurity reacts with the silane-based gas.
Abstract: Embodiments provided herein describe systems and methods for forming semiconductor devices. A semiconductor substrate is provided. The semiconductor substrate is exposed to bromine radicals, hydrogen radicals, or a combination thereof. An oxide layer is formed above the semiconductor substrate. The semiconductor substrate is held within a controlled atmosphere at least from the completion of the exposing of the semiconductor substrate to bromine radicals, hydrogen radicals, or a combination thereof and the beginning of the forming of the oxide layer.
Abstract: In one embodiment, the method includes forming a conductive via structure in a base layer. The base layer has a first surface and a second surface, and the second surface is opposite the first surface. The method further includes removing the second surface of the base layer to expose the conductive via structure such that the conductive via structure protrudes from the second surface, and forming a first lower insulating layer over the second surface such that an end surface of the conductive via structure remains exposed by the first lower insulating layer.
Abstract: A method of forming a metal oxide hardmask on a template includes: providing a template constituted by a photoresist or amorphous carbon formed on a substrate; and depositing by atomic layer deposition (ALD) a metal oxide hardmask on the template constituted by a material having a formula SixM(1-x)Oy wherein M represents at least one metal element, x is less than one including zero, and y is approximately two or a stoichiometrically-determined number.
Abstract: Embodiments relate to using radicals to at different stages of deposition processes. The radicals may be generated by applying voltage across electrodes in a reactor remote from a substrate. The radicals are injected onto the substrate at different stages of molecular layer deposition (MLD), atomic layer deposition (ALD), and chemical vapor deposition (CVD) to improve characteristics of the deposited layer, enable depositing of material otherwise not feasible and/or increase the rate of deposition. Gas used for generating the radicals may include inert gas and other gases. The radicals may disassociate precursors, activate the surface of a deposited layer or cause cross-linking between deposited molecules.
Abstract: Provided is a method for manufacturing a semiconductor device, in which a degradation of characteristics of a thin film transistor can be suppressed by performing plasma oxidation treatment on a gate insulating film containing nitrogen. An embodiment of the present invention is a method for manufacturing a semiconductor device comprising a thin film transistor including a gate electrode, a gate insulating film containing nitrogen, and a channel region in microcrystalline semiconductor films. The method includes the steps of performing plasma treatment on the gate insulating film in an oxidizing gas atmosphere containing hydrogen and an oxidizing gas containing an oxygen atom, and forming the microcrystalline semiconductor film over the gate insulating film. Formula (1), a/b?2, and Formula (2), b>0, are satisfied, where the amount of hydrogen and the amount of the oxidizing gas in the oxidizing gas atmosphere are a and b, respectively.
Type:
Grant
Filed:
March 29, 2012
Date of Patent:
October 13, 2015
Assignees:
Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha