Abstract: Methods for depositing a material, such as a metal or a transition metal oxide, using an ALD (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ALD process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. The surface treatment may reactivate a surface of the substrate toward the blocking material, may restore the blocking material after degradation occurs during the ALD process, and/or may coat the blocking material to prevent further degradation during the ALD process. For example, the surface treatment may be applied after performing one or more ALD cycles. Accordingly, the presently disclosed methods enable in situ restoration of blocking materials in ALD process that are generally incompatible with the blocking material and also enables selective deposition in recessed structures.
Abstract: A deposition apparatus for performing a deposition process on a substrate includes: an injection unit including a plasma generating member which receives a raw material gas and converts the raw material gas to a deposition source material in a radical form; and a plasma processor disposed adjacent to the injection unit and facing a side of the injection unit, wherein the plasma processor performs a plasma process in a direction facing the substrate.
Type:
Application
Filed:
May 4, 2014
Publication date:
January 29, 2015
Applicant:
Samsung Display Co., Ltd.
Inventors:
Myung-Soo HUH, Suk-Won JUNG, Sung-Chul KIM, Sang-Hyuk HONG, Choel-Min JANG
Abstract: A semiconductor structure comprises a substrate including a III-V material, and a high-k interfacial layer overlaying the substrate. The interfacial layer includes a rare earth aluminate. The present disclosure also relates to an n-type FET device comprising the same, and a method for manufacturing the same.
Type:
Application
Filed:
July 25, 2014
Publication date:
January 29, 2015
Applicants:
KATHOLIEKE UNIVERSITEIT LEUVEN, KU LEUVEN R&D, IMEC VZW
Inventors:
Han Chung Lin, Laura Nyns, Tsvetan Ivanov, Dennis Van Dorp
Abstract: A method of making a Si containing gas distribution member for a semiconductor plasma processing chamber comprises forming a carbon member into an internal cavity structure of the Si containing gas distribution member. The method includes depositing Si containing material on the formed carbon member such that the Si containing material forms a shell around the formed carbon member. The Si containing shell is machined into the structure of the Si containing gas distribution member wherein the machining forms gas inlet and outlet holes exposing a portion of the formed carbon member in an interior region of the Si containing gas distribution member.
Abstract: Techniques disclosed herein may achieve crack free filling of structures. A flowable film may substantially fill gaps in a structure and extend over a base in an open area adjacent to the structure. The top surface of the flowable film in the open area may slope down and may be lower than top surfaces of the structure. A capping layer having compressive stress may be formed over the flowable film. The bottom surface of the capping layer in the open area adjacent to the structure is lower than the top surfaces of the lines and may be formed on the downward slope of the flowable film. The flowable film is cured after forming the capping layer, which increases tensile stress of the flowable film. The compressive stress of the capping layer counteracts the tensile stress of the flowable film, which may prevent a crack from forming in the base.
Abstract: A liquid treatment apparatus of continuously performing a plating process on multiple substrates includes a temperature controlling container for accommodating a plating liquid; a temperature controller for controlling a temperature of the plating liquid in the temperature controlling container; a holding unit for holding the substrates one by one at a preset position; a nozzle having a supply hole through which the temperature-controlled plating liquid in the temperature controlling container is discharged to a processing surface of the substrate; a pushing unit for pushing the temperature-controlled plating liquid in the temperature controlling container toward the supply hole of the nozzle; and a supply control unit for controlling a timing when the plating liquid is pushed by the pushing unit. The temperature controller controls the temperature of the plating liquid in the temperature controlling container based on the timing when the plating liquid is pushed by the pushing unit.
Abstract: A method for manufacturing a semiconductor device is disclosed. In one aspect the method includes forming a gate stack over a substrate. The method also includes forming a dummy sidewall spacer around the gate stack. The method also includes depositing a stress liner of diamond-like amorphous carbon (DLC) on the substrate, the gate stack and the dummy sidewall spacer. The method also includes annealing, so that a channel region in the substrate below the gate stack and the gate stack memorize stress in the stress liner. The method also includes removing the dummy sidewall spacer. The method also includes forming a sidewall spacer around the gate stack. In the method according to the disclosed technology, large stress in the liner of DLC is memorized and applied to the dummy gate stack and the channel region.
Type:
Grant
Filed:
April 30, 2014
Date of Patent:
January 20, 2015
Assignee:
Institute of Microelectronics, Chinese Academy of Sciences
Inventors:
Huaxiang Yin, Qingqing Liang, Xiaolong Ma
Abstract: A transistor includes a semiconductor substrate, at least a gate structure, at least a first tensile stress layer, a second tensile stress layer, a source region, and a drain region. The gate structure is disposed within a first transistor region of the semiconductor substrate. The first tensile stress layer includes a curved portion encompassing the gate structure, at least an extension portion with a curved top surface located on the semiconductor substrate at sides of the gate structure, and a transition portion between the curved portion and the extension portion. The first tensile stress layer has a thickness gradually thinning from the curved portion and the extension portion toward the transition portion. The second tensile stress layer is disposed on the first tensile stress layer. And the source/drain regions are separately located in the semiconductor substrate on two sides of the gate structure.
Abstract: An apparatus and method for combinatorial non-contact wet processing of a liquid material may include a source of a liquid material, a first reaction cell, a second reaction cell, a first plurality of gas jets disposed within an interior of the first reaction cell, the first plurality of gas jets configured to atomize the liquid material transferred to the interior of the first reaction cell, a second plurality of gas jets disposed within an interior of the second reaction cell, the second plurality of gas jets configured to atomize the liquid material transferred to the interior of the second reaction cell, a first vacuum element disposed along a periphery of the first reaction cell, and a second vacuum element disposed along a periphery of the at least a second reaction cell.
Abstract: Thermal oxidation treatment methods and processes used during fabrication of semiconductor devices are provided. One method includes, for instance: obtaining a device with at least one cavity etched into the device; performing a thermal oxidation treatment to the at least one cavity; and cleaning the at least one cavity. One process includes, for instance: providing a semiconductor device with a substrate, at least one layer over the substrate and at least one fin; forming at least one gate over the fin; doping at least one region below the fin; applying a spacer layer over the device; etching the spacer layer to expose at least a portion of the gate material; etching a cavity into the at least one fin; etching a shaped opening into the cavity; performing thermal oxidation processing on the at least one cavity; and growing at least one epitaxial layer on an interior surface of the cavity.
Type:
Application
Filed:
July 10, 2013
Publication date:
January 15, 2015
Inventors:
Wei Hua TONG, Hong YU, Jin Ping LIU, Hyucksoo YANG, Lun ZHAO, Chandra REDDY
Abstract: A spin-on dielectric of novel composition formed as a sol comprising an a source of silicon such as an orthosilicate ester, alone or in combination with an alkylated orthosilicate ester, a polar solvent, water, an acid catalyst, which may be a strong acid catalyst, and an amphiphilic block copolymer surfactant, optionally including an organic acid, a co-solvent and/or a reactive solvent. Also provided is a method of formulating the sol, a film made from the spin-on dielectric that has desirable electrical and mechanical properties, methods for treating the film described to optimize the film's electrical and mechanical performance, and methods for depositing the film onto silicon, steel or other surfaces.
Abstract: Nanoporous polymers with gyroid nanochannels can be fabricated from the self-assembly of degradable block copolymer, polystyrene-b-poly(L-lactide) (PS-PLLA), followed by the hydrolysis of PLLA blocks. A well-defined nanohybrid material with SiO2 gyroid nanostructure in a PS matrix can be obtained using the nanoporous PS as a template for the sol-gel reaction. After subsequent UV degradation of the PS matrix, a highly porous inorganic gyroid network remains, yielding a single-component material with an exceptionally low refractive index (as low as 1.1).
Abstract: An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.
Type:
Application
Filed:
September 18, 2014
Publication date:
January 1, 2015
Inventors:
Gilbert Dewey, Niloy Mukherjee, Matthew Metz, Jack T. Kavalieros, Nancy M. Zelick, Robert S. Chau
Abstract: A method includes holding bonded wafers by a wafer holding module. A gap between the bonded wafers along an edge is filled with a protection material.
Abstract: A method for treating a wafer is provided. The method includes at least the following steps. A plasma process is performed on a front surface of the wafer, and the wafer is cleaned. The wafer is cleaned by applying deionized water with dissolved CO2 to the front surface of the wafer and applying a chemical solution to a back surface, opposite to the front surface, of the wafer.
Abstract: A thin film having a low dielectric constant and a high resistance to HF at a low temperature range is formed with high productivity. A film containing a predetermined element, oxygen and at least one of carbon and nitrogen is formed on a substrate by performing, a predetermined number of times, a cycle comprising: (a) supplying a source gas containing the predetermined element to the substrate; and (b) supplying a reaction gas containing nitrogen, carbon and oxygen to the substrate.
Abstract: A method of forming a silicon-containing dielectric material. The method includes forming a plasma comprising nitrogen radicals, absorbing the nitrogen radicals onto a substrate, and exposing the substrate to a silicon-containing precursor in a non-plasma environment to form monolayers of a silicon-containing dielectric material on the substrate. Additional methods are also described, as are semiconductor device structures including the silicon-containing dielectric material and methods of forming the semiconductor device structures.
Abstract: Processes for preparation of an epitaxial graphene surface to make it suitable for deposition of high-? oxide-based dielectric compounds such as Al2O3, HfO2, TaO5, or TiO2 are provided. A first process combines ex situ wet chemistry conditioning of an epitaxially grown graphene sample with an in situ pulsing sequence in the ALD reactor. A second process combines ex situ dry chemistry conditioning of the epitaxially grown graphene sample with the in situ pulsing sequence.
Type:
Grant
Filed:
July 1, 2013
Date of Patent:
December 30, 2014
Assignee:
The United States of America, as represented by the Secretary of the Navy
Inventors:
Nelson Garces, Virginia D. Wheeler, David Kurt Gaskill, Charles R. Eddy, Jr., Glenn G. Jernigan
Abstract: A method for processing a high-k dielectric layer includes the following steps. A semiconductor substrate is provided, and a high-k dielectric layer is formed thereon. The high-k dielectric layer has a crystalline temperature. Subsequently, a first annealing process is performed, and a process temperature of the first annealing process is substantially smaller than the crystalline temperature. A second annealing process is performed, and a process temperature of the second annealing process is substantially larger than the crystalline temperature.
Abstract: An illustrative DSA formulation disclosed herein includes a block copolymer material, a casting solvent and at least one plasticizer agent. An illustrative method disclosed herein includes depositing a liquid DSA formulation on a guide layer, performing a spin-coating process to form a DSA-based material layer comprised of the liquid DSA formulation above the guide layer, wherein the DSA-based material layer includes at least one plasticizing agent and, after performing the spin-coating process, performing at least one heating process on the DSA-based material layer while at least some of the plasticizing agent remains in the DSA-based material layer so as to enable phase separation of block copolymer materials.
Type:
Application
Filed:
June 19, 2013
Publication date:
December 25, 2014
Inventors:
Gerard M. Schmid, Ji Xu, Richard A. Farrell
Abstract: A manufacturing method of a semiconductor device includes forming a first resist film above a substrate, placing a first photomask, that includes a first mask pattern, in a first position above the first resist film, transferring the first mask pattern to the first resist film to form a first resist pattern above the substrate, forming a second resist film above the substrate after forming the first resist pattern, placing the first photomask in a second position above the second resist film, and transferring the first mask pattern to the second resist film to form a second resist pattern above the substrate.
Abstract: A method for filling recesses of a substrate with an insulation film includes: (i) exposing surfaces of the recesses of the substrate to a pre-deposition gas in a reactive state in a reaction space to treat the surfaces with reactive hydrocarbons generated from the pre-deposition gas without filling the recesses; and (ii) depositing a flowable insulation film using a process gas other than the pre-deposition gas on a surface of the substrate to fill the recesses treated in step (i) therewith by plasma reaction. The pre-deposition gas has at least one hydrocarbon unit in its molecule.
Abstract: A method and apparatus for depositing a material layer, such as encapsulating film, onto a substrate is described. In one embodiment, an encapsulating film formation method includes delivering a gas mixture into a processing chamber, the gas mixture comprising a silicone-containing gas, a first nitrogen-containing gas, a second nitrogen-containing gas and hydrogen gas; energizing the gas mixture within the processing chamber by applying between about 0.350 watts/cm2 to about 0.903 watts/cm2 to a gas distribution plate assembly spaced about 800 mils to about 1800 mils above a substrate positioned within the processing chamber; maintaining the energized gas mixture within the processing chamber at a pressure of between about 0.5 Torr to about 3.0 Torr; and depositing an inorganic encapsulating film on the substrate in the presence of the energized gas mixture. In other embodiments, an organic dielectric layer is sandwiched between inorganic encapsulating layers.
Type:
Grant
Filed:
February 15, 2013
Date of Patent:
December 2, 2014
Assignee:
Applied Materials, Inc.
Inventors:
Jrjyan Jerry Chen, Tae K. Won, Beom Soo Park, Young Jin Choi, Soo Young Choi
Abstract: A method of depositing a film of forming a doped oxide film including a first oxide film containing a first element and doped with a second element on substrates mounted on a turntable including depositing the first oxide film onto the substrates by rotating the turntable predetermined turns while a first reaction gas containing the first element is supplied from a first gas supplying portion, an oxidation gas is supplied from a second gas supplying portion, and a separation gas is supplied from a separation gas supplying portion, and doping the first oxide film with the second element by rotating the turntable predetermined turns while a second reaction gas containing the second element is supplied from one of the first and second gas supplying portions, an inert gas is supplied from another one, and the separation gas is supplied from the separation gas supplying portion.
Abstract: To form an insulating film with extremely low concentration of impurities such as carbon, hydrogen, nitrogen, chlorine, etc in a film. There are provided the steps of forming a specific element-containing layer on a substrate by supplying source gas containing a specific element into a processing container in which the substrate is accommodated; changing the specific element-containing layer into a nitride layer, by activating and supplying gas containing nitrogen into the processing container; and changing the nitride layer into an oxide layer or an oxynitride layer, by activating and supplying gas containing oxygen into the processing container; with this cycle set as one cycle and performed for at least one or more times.
Abstract: A MOS solid-state imaging device is provided in which withstand voltage and 1/f noise of a MOS transistor are improved. In the MOS solid-state imaging device whose unit pixel has at least a photoelectric converting portion and a plurality of field effect transistors, the thickness of gate insulating film in a part of the field effect transistors is different from the thickness of gate insulating film in the other field effect transistors among the plurality of the field effect transistors.
Abstract: Fluorescent semiconductor nanocrystals and quantum dots having an inorganic coating on the outermost surface of the nanocrystal are described herein as well as methods for preparing and using such nanocrystals and quantum dots. Devices in which such nanocrystals and quantum dots are used are also described.
Abstract: A method of fabricating a synthetic diamond coated compound semiconductor substrate, the method comprising: loading a composite substrate into a chemical vapour deposition (CVD) reactor, the composite substrate comprising a single crystal carrier wafer, a layer of single crystal compound semiconductor epitaxially grown on the carrier wafer, and an interface layer disposed on the layer of compound semiconductor, the interface layer forming a growth surface suitable for growth of synthetic diamond material thereon via a CVD technique; and growing a layer of CVD diamond material on the growth surface of the interface layer, wherein during growth of CVD diamond material a temperature difference at the growth surface between an edge and a centre point thereof is maintained to be no more than 80° C., and wherein the carrier wafer has an aspect ratio, defined by a ratio of thickness to width, of no less than 0.25/100.
Abstract: A method of forming a dielectric layer is described. The method deposits a silicon-containing film by chemical vapor deposition using a local plasma. The silicon-containing film is flowable during deposition at low substrate temperature. A silicon precursor (e.g. a silylamine, higher order silane or halogenated silane) is delivered to the substrate processing region and excited in a local plasma. A second plasma vapor or gas is combined with the silicon precursor in the substrate processing region and may include ammonia, nitrogen (N2), argon, hydrogen (H2) and/or oxygen (O2). The equipment configurations disclosed herein in combination with these vapor/gas combinations have been found to result in flowable deposition at substrate temperatures below or about 200° C. when a local plasma is excited using relatively low power.
Type:
Grant
Filed:
November 5, 2012
Date of Patent:
November 18, 2014
Assignee:
Applied Materials, Inc.
Inventors:
Amit Chatterjee, Abhijit Basu Mallick, Nitin K. Ingle, Brian Underwood, Kiran V. Thadani, Xiaolin Chen, Abhishek Dube, Jingmei Liang
Abstract: A thin film containing boron and a borazine ring structure is formed on a substrate by performing a cycle a predetermined number of times under a condition where the borazine ring structure is preserved in a borazine compound. The cycle includes: supplying a source gas containing boron and a halogen element to the substrate; and supplying a reactive gas including a borazine compound to the substrate.
Abstract: The present invention relates to a magnesium oxide-based (MgO) inorganic coating intended to electrically insulate semiconductive substrates such as silicon carbide (SiC), and to a method for producing such an insulating coating. The method of the invention comprises the steps of preparing a treatment solution of at least one hydrolysable organomagnesium compound and/or of at least one hydrolysable magnesium salt, capable of forming a homogeneous polymer layer of magnesium oxyhydroxide by hydrolysis/condensation reaction with water; depositing the treatment solution of the hydrolysable organomagnesium compound or of the hydrolysable magnesium salt, onto a surface to form a magnesium oxide-based layer; and densifying the layer formed at a temperature of less than or equal to 1000° C.
Abstract: Methods and compositions for depositing rare earth metal-containing layers are described herein. In general, the disclosed methods deposit the precursor compounds comprising rare earth-containing compounds using deposition methods such as chemical vapor deposition or atomic layer deposition. The disclosed precursor compounds include a cyclopentadienyl ligand having at least one aliphatic group as a substituent and an amidine ligand.
Type:
Application
Filed:
July 16, 2014
Publication date:
November 13, 2014
Inventors:
Venkateswara R. PALLEM, Christian Dussarrat, Wontae Noh
Abstract: Carbon layers with reduced hydrogen content may be deposited by plasma-enhanced chemical vapor deposition by selecting processing parameters accordingly. Such carbon layers may be subjected to high temperature processing without showing excessive shrinking.
Type:
Application
Filed:
May 10, 2013
Publication date:
November 13, 2014
Inventors:
Guenter Denifl, Markus Kahn, Helmut Schoenherr, Daniel Maurer, Thomas Grille, Joachim Hirschler, Ursula Hedenig, Roland Moennich, Matthias Kuenle
Abstract: The present invention relates to a process and system for depositing a thin film onto a substrate. One aspect of the invention is depositing a thin film metal oxide layer using atomic layer deposition (ALD).
Type:
Grant
Filed:
May 6, 2011
Date of Patent:
November 4, 2014
Assignee:
ASM America, Inc.
Inventors:
Eric J. Shero, Petri I. Raisanen, Sung-Hoon Jung, Chang-Gong Wang
Abstract: A method for manufacturing a silicon carbide semiconductor device includes the following steps. A silicon carbide substrate is heated in an atmosphere containing oxygen, so as to form a gate insulating film on and in contact with the silicon carbide substrate. The silicon carbide substrate having the gate insulating film is heated at 1250° C. or more in an atmosphere containing nitrogen and nitrogen monoxide. A value obtained by dividing partial pressure of the nitrogen monoxide by a total of partial pressure of the nitrogen and the partial pressure of the nitrogen monoxide in the second heating step is more than 3% and less than 10%. Accordingly, there can be provided a method for manufacturing a silicon carbide semiconductor device having high mobility.
Abstract: A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the structure portion. A connection pad portion is arranged on the insulating film and connected to an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film made of an organic resin is provided on a part of the insulating film which surrounds the bump electrode. Side surfaces of the laminated structure portion are covered with the insulating film and/or the sealing film.
Abstract: The method of forming a silicon oxycarbonitride film on a base includes stacking a silicon carbonitride film and a silicon oxynitride film on the base to form the silicon oxycarbonitride film.
Type:
Grant
Filed:
December 26, 2012
Date of Patent:
October 28, 2014
Assignee:
Tokyo Electron Limited
Inventors:
Keisuke Suzuki, Kentaro Kadonaga, Byoung Hoon Lee, Eun Jo Lee, Sung Duk Son, Jae Hyuk Jang, Do Hyun Park
Abstract: A film deposition apparatus forming a thin film by after repeating cycles of sequentially supplying gases to a substrate on a turntable inside a vacuum chamber that includes a first supplying portion for causing the substrate to absorb a first gas containing silicon; a second supplying portion apart from the first supplying portion for supplying a second gas containing active species to produce a silicone dioxide; a separating area between the first and second supplying portions for preventing their mixture; a main heating mechanism for heating the substrate; and an auxiliary mechanism including a heat lamp above the turntable and having a wavelength range absorbable by the substrate to directly heat to be a processing temperature at which an ozone gas is thermally decomposed, wherein a maximum temperature is lower than the thermally decomposed temperature, at which, the first gas is absorbed and oxidized by the second gas.
Abstract: A method for flowable oxide deposition is provided. An oxygen source gas is increased as a function of time or film depth to change the flowable oxide properties such that the deposited film is optimized for gap fill near a substrate surface where high aspect ratio shapes are present. The oxygen gas flow rate increases as the film depth increases, such that the deposited film is optimized for planarization quality at the upper regions of the deposited film.
Abstract: Planarization methods and microelectronic structures formed therefrom are disclosed. The methods and structures use planarization materials comprising fluorinated compounds or acetoacetylated compounds. The materials are self-leveling and achieve planarization over topography without the use of etching, contact planarization, chemical mechanical polishing, or other conventional planarization techniques.
Abstract: A film forming method is disclosed in which a thin film comprising manganese is formed on an object to be processed which has, on a surface thereof, an insulating layer constituted of a low-k film and having a recess. The method comprises a hydrophilization step in which the surface of the insulating layer is hydrophilized to make the surface hydrophilic and a thin-film formation step in which a thin film containing manganese is formed on the surface of the hydrophilized insulating layer by performing a film forming process using a manganese-containing material gas on the surface of the hydrophilized insulating layer. Thus, a thin film comprising manganese, e.g., an MnOx film, is effectively formed on the surface of the insulating layer constituted of a low-k film, which has a low dielectric constant.
Type:
Grant
Filed:
June 16, 2010
Date of Patent:
October 21, 2014
Assignees:
Tokyo Electron Limited, National University Corporation Tohoku University
Abstract: A surface of a semiconductor-containing dielectric material/oxynitride/nitride is treated with a basic solution in order to provide hydroxyl group termination of the surface. A dielectric metal oxide is subsequently deposited by atomic layer deposition. The hydroxyl group termination provides a uniform surface condition that facilitates nucleation and deposition of the dielectric metal oxide, and reduces interfacial defects between the oxide and the dielectric metal oxide. Further, treatment with the basic solution removes more oxide from a surface of a silicon germanium alloy with a greater atomic concentration of germanium, thereby reducing a differential in the total thickness of the combination of the oxide and the dielectric metal oxide across surfaces with different germanium concentrations.
Type:
Application
Filed:
April 16, 2013
Publication date:
October 16, 2014
Applicant:
International Business Machines Corporation
Inventors:
Takashi Ando, Michael P. Chudzik, Min Dai, Martin M. Frank, David F. Hilscher, Rishikesh Krishnan, Barry P. Linder, Claude Ortolland, Joseph F. Shepard, JR.
Abstract: A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls. The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.
Type:
Grant
Filed:
June 29, 2007
Date of Patent:
October 14, 2014
Assignee:
Texas Instruments Incorporated
Inventors:
Mahalingam Nandakumar, Wayne Bather, Narendra Singh Mehta
Abstract: The present invention provides a system and method for manufacturing a semiconductor device including a substrate and a high-? dielectric layer on the substrate. The system comprises a modular track; a substrate-forming chamber connected with the modular track for forming the substrate; and an atomic layer deposition (ALD) chamber connected with the modular track for providing the high-? dielectric layer.
Abstract: Disclosed are apparatus and methods for processing a substrate. The substrate having a feature with a layer thereon is exposed to an inductively coupled plasma which forms a substantially conformal layer.
Type:
Application
Filed:
April 8, 2013
Publication date:
October 9, 2014
Inventors:
Heng Pan, Matthew Scott Rogers, Johanes F. Swenberg, Christopher S. Olsen, Wei Liu, David Chu, Malcolm J. Bevan
Abstract: According to an embodiment of present disclosure, a film formation method is provided. The film formation method includes supplying a first process gas as a source gas for obtaining a reaction product to a substrate while rotating a turntable and revolving the substrate, and supplying a second process gas as a gas for nitriding the first process gas adsorbed to the substrate to the substrate in a position spaced apart along a circumferential direction of the turntable from a position where the first process gas is supplied to the substrate. Further, the film formation method includes providing a separation region along the circumferential direction of the turntable between a first process gas supply position and a second process gas supply position, and irradiating ultraviolet rays on a molecular layer of the reaction product formed on the substrate placed on the turntable to control stresses generated in a thin film.
Abstract: A method of forming an oxide film on an object to be processed, includes: supplying a film-forming raw material gas into a processing chamber; performing at least one of exhausting the processing chamber and supplying a purge gas into the processing chamber to remove gas remaining in the processing chamber; supplying an oxidant gas into the processing chamber; and performing at least one of exhausting the processing chamber and supplying the purge gas into the processing chamber to remove gas remaining in the processing chamber, wherein supplying an oxidant gas includes: supplying a first oxidant gas into the processing chamber at a first concentration; and supplying a second oxidant gas into the processing chamber at a second concentration higher than the first concentration.
Abstract: A method includes forming a polymer layer over a passivation layer, wherein the passivation layer further comprises a portion over a metal pad. The polymer layer is patterned to form an opening in the polymer layer, wherein exposed surfaces of the polymer layer have a first roughness. A surface treatment is performed to increase a roughness of the polymer layer to a second roughness greater than the first roughness. A metallic feature is formed over the exposed surface of the polymer layer.
Abstract: Disclosed herein is a method for manufacturing a semiconductor device, the method including the step of forming a gate electrode that contains a metal over a semiconductor substrate with intermediary of a gate insulating film, the step including the sub-steps of, forming a first gate electrode layer that defines a work function of the gate electrode on the gate insulating film, forming a second gate electrode layer that has a barrier property for underlayers on the first gate electrode layer, and forming a third gate electrode layer of which resistance is lower than a resistance of the first gate electrode layer on the second gate electrode layer by chemical vapor deposition.
Abstract: A method of producing an inorganic multi-layered thin film structure includes providing a substrate. A patterned deposition inhibiting material layer is provided on the substrate. A first inorganic thin film material layer is selectively deposited on a region of the substrate where the deposition inhibiting material layer is not present using an atomic layer deposition process. A second inorganic thin film material layer is selectively deposited on the region of the substrate where the thin film deposition inhibiting material layer is not present using an atomic layer deposition process.
Type:
Grant
Filed:
August 31, 2012
Date of Patent:
September 30, 2014
Assignee:
Eastman Kodak Company
Inventors:
Carolyn R. Ellinger, David H. Levy, Shelby F. Nelson