Baffle plate for manufacturing semiconductor

- Tokyo Electron Limited
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Description

FIG. 1 is a front view of a baffle plate of the present invention.

FIG. 2 is a rear view of the baffle plate of FIG. 1.

FIG. 3 is a top plan view of the baffle plate of FIG. 1.

FIG. 4 is a bottom view of the baffle plate of FIG. 1.

FIG. 5 is a right side view of the baffle plate of FIG. 1.

FIG. 6 is a left view of the baffle plate of FIG. 1.

FIG. 7 is a first perspective view of the baffle plate of FIG. 1.

FIG. 8 is a second perspective view of the baffle plate of FIG. 1; and,

FIG. 9 is a view of the baffle plate of FIG. 1 in use, wherein, for example, in a plasma processing device, gas entering a chamber is ionized, and a wafer is treated by an etching process with ions, and gas is exhausted from the chamber.

The features shown in broken lines depict environmental subject matter only and form no part of the claimed design.

Claims

The ornamental design for a baffle plate for manufacturing semiconductor, as shown and described.

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Patent History
Patent number: D694790
Type: Grant
Filed: Mar 19, 2012
Date of Patent: Dec 3, 2013
Assignee: Tokyo Electron Limited (Tokyo)
Inventors: Naoki Matsumoto (Sendai), Jun Yoshikawa (Sendai)
Primary Examiner: Patricia Palasik
Application Number: 29/416,082