Power device package
Latest SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC Patents:
- Fabrication method for JFET with implant isolation
- Electronic device including a transistor and a shield electrode
- FABRICATION METHOD FOR JFET WITH IMPLANT ISOLATION
- HYBRID INDUCTOR CURRENT MONITORING FOR POWER SWITCH
- Electronic Device Including a Non-Volatile Memory Cell and a Process of Forming the Same
Description
The broken lines shown in the drawings represent portions of the power device package that form no part of the claimed design.
Claims
The ornamental design for a power device package, as shown and described.
Referenced Cited
U.S. Patent Documents
5408128 | April 18, 1995 | Furnival |
5410450 | April 25, 1995 | Iida |
D364383 | November 21, 1995 | Yamada |
D364384 | November 21, 1995 | Shimizu |
D364385 | November 21, 1995 | Shimizu |
6078501 | June 20, 2000 | Catrambone |
D441726 | May 8, 2001 | Sofue |
D441727 | May 8, 2001 | Sekimoto |
6521983 | February 18, 2003 | Yoshimatsu |
D476959 | July 8, 2003 | Yamada |
D525215 | July 18, 2006 | Hisaishi |
D539761 | April 3, 2007 | Takahashi |
D548202 | August 7, 2007 | Takahashi |
D548203 | August 7, 2007 | Takahashi |
D587662 | March 3, 2009 | Soutome |
D589012 | March 24, 2009 | Soyano |
D606951 | December 29, 2009 | Soyano |
D653633 | February 7, 2012 | Soyano |
D653634 | February 7, 2012 | Soyano |
D674760 | January 22, 2013 | Mochizuki |
D686174 | July 16, 2013 | Soyano |
D689446 | September 10, 2013 | Soyano |
8526199 | September 3, 2013 | Matsumoto |
D699693 | February 18, 2014 | Otsuka |
D703625 | April 29, 2014 | Lim |
D704670 | May 13, 2014 | Chen |
D704671 | May 13, 2014 | Chen |
D705184 | May 20, 2014 | Takahashi |
D706232 | June 3, 2014 | Nakamura |
D710317 | August 5, 2014 | Chen |
D710318 | August 5, 2014 | Chen |
D710319 | August 5, 2014 | Chen |
Patent History
Patent number: D755741
Type: Grant
Filed: Feb 18, 2015
Date of Patent: May 10, 2016
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (Phoenix, AZ)
Inventors: Atapol Prajuckamol (Klaeng), Chee Hiong Chew (Seremban), Yushuang Yao (Seremban)
Primary Examiner: Elizabeth J Oswecki
Application Number: 29/517,863
Type: Grant
Filed: Feb 18, 2015
Date of Patent: May 10, 2016
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (Phoenix, AZ)
Inventors: Atapol Prajuckamol (Klaeng), Chee Hiong Chew (Seremban), Yushuang Yao (Seremban)
Primary Examiner: Elizabeth J Oswecki
Application Number: 29/517,863
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)