Apparatus for evaluating semiconductor substrate
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The broken lines illustrate portions of the apparatus for evaluating semiconductor substrate that form no part of the claimed design. The hatching shown in
Claims
The ornamental design for an apparatus for evaluating semiconductor substrate, as shown and described.
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- U.S. Appl. No. 29/789,675, filed Oct. 13, 2021.
- U.S. Appl. No. 29/789,677, filed Oct. 13, 2021.
- United States Notice of Allowance issued in U.S. Appl. No. 29/789,675 dated Mar. 8, 2023 (nine (9) pages).
- United States Notice of Allowance issued in U.S. Appl. No. 29/789,677 dated Mar. 8, 2023 (nine (9) pages).
Type: Grant
Filed: Oct 13, 2021
Date of Patent: Jun 13, 2023
Assignee: Hitachi High-Tech Corporation (Tokyo)
Inventors: Masayuki Arakawa (Tokyo), Junpei Hokari (Tokyo), Akira Kojima (Tokyo), Masaki Mizuochi (Tokyo), Tomokazu Kobayashi (Tokyo), Takaaki Kikuchi (Tokyo)
Primary Examiner: Patricia A Palasik
Application Number: 29/789,674