Abstract: A wiring body includes a first conductor layer including a first conductor wire, a resin layer covering the first conductor layer, and a second conductor layer disposed on the first conductor layer through the resin layer and including a second conductor wire. The wiring body satisfies the formula |H1?H2|<T1/3 where H1 is a maximum height of the second conductor wire in a first region corresponding to the first conductor wire in a first predetermined sectional surface crossing the wiring body along the second conductor wire, H2 is a minimum height of the second conductor wire in a second region that is adjacent to the first region and has the same width as that of the first region in the first predetermined sectional surface, and T1 is a thickness of the first conductor wire in the first predetermined sectional surface.

Abstract: The present invention has disclosed a touch screen, comprising: a substrate; at least one first electrode formed on the substrate; at least one second electrode formed on the substrate, the first electrode and the second electrode having different extending directions, and there being an intersecting area between a vertical projection of the first electrode on the substrate and a vertical projection of the second electrode on the substrate; and a first protection layer formed at least at the intersecting area between the first electrode and the second electrode; wherein, the substrate is provided with a groove at the intersecting area between the first electrode and the second electrode so as to at least receive therein a portion of the first electrode located within the intersecting area. The present invention has also disclosed a display device and a method for manufacturing the touch screen.

Abstract: Contact structures for devices, where contacts in the contact structures may provide a sufficient normal force to provide a good electrical connection with corresponding contacts while consuming a minimal amount of surface area, depth, and volume in a device, and where the contact structures may prevent or limit the ingress of fluid or debris into the device. On example may provide a contact structure having a frame. The frame may be arranged to be placed in an opening in a device enclosure for an electronic device or the frame may be part of the electronic device. The frame may include a number of passages, each passage for a contact of the contact structure. Each contact may be held to the frame by a pliable membrane. Each contact may connect to a board in the electronic device via a compliant conductive path.

Abstract: According to one embodiment, a multilayer printed board includes an insulating substrate, a differential signal wiring, and anti-pad regions. Distances between peripheries of the pad and a constant potential layer in each of the wiring layers are set so that a capacitance between the constant potential layers and a signal via included in a signal line constituting the differential signal wiring, which has a longer route from a transmission end to a reception end, is smaller than a capacitance between the constant potential layers and another signal via included in the other signal line.

Abstract: A method of the present invention includes preparing a substrate having a surface on which a electrode pad is formed, forming a resist layer on the substrate, the resist layer having an opening on the electrode pad, filling conductive paste in the opening of the resist layer; sintering the conductive paste in the opening to form a conductive layer which covers a side wall of the resist layer and a surface of the electrode pad in the opening, a space on the conductive layer leading to the upper end of the opening being formed, filling solder in the space on the conductive layer and removing the resist layer.

Abstract: A memory card adaptor may include a plurality of card-side terminals arranged to contact terminals of a memory card, a plurality of socket-side terminals arranged in a first direction to contact terminals of a host socket and including at least two socket-side ground terminals, wiring lines configured to electrically connect the plurality of card-side terminals to the plurality of socket-side terminals in a one-to-one correspondence, a ground frame configured to electrically connect the at least two socket-side ground terminals to each other, and a housing that accommodates the plurality of card-side terminals, the plurality of socket-side terminals, and the wiring lines. The memory card adaptor may have good electrical characteristics, and thus may be able to stably operate even during fast data transmission.

Abstract: A multilayer wiring board with built-in electronic components includes a substrate including an insulating material and having multiple opening portions, a first conductor layer formed on a surface of the substrate and having an opening portion such that the substrate has the opening portions inside the opening portion of the first conductor layer, multiple electronic components positioned in the opening portions of the substrate, and an insulating layer formed on the substrate such that the insulating layer is formed on the electronic components and on the first conductor layer. The opening portions are formed in the substrate such that the opening portions include two opening portions and that the substrate has a partition wall formed between the two opening portions.

Abstract: Disclosed is a touch window including a substrate, and an electrode part provided on the substrate to detect a position. The electrode part includes a base including an electrode.

Abstract: A processor-implemented method and integrated circuit package are provided. According to an implementation, a method of producing a chip package includes de-populating solder balls at selected locations in a fine pitch package, and providing test pads at the de-populated solder ball locations. In an example implementation, the method comprises receiving and modifying a package design. In an implementation, a row of test pads in an integrated circuit package is provided in a plurality of concentric annular rows, the row of test pads being adjacent an outer row of via-connected solder balls and adjacent an inner row of via-connected solder balls. In an implementation, test pads are located on a PCB-facing surface of the package at a subset of locations opposing at least one via position on a package-facing surface of the PCB. The test pads maintain a large number of signal pins and do not interfere with the via.

Abstract: There are provided a printed circuit board including: an insulation layer in which a via hole is formed; vias formed in the via hole; first circuit patterns formed below the insulation layer and electrically connected to the vias; and second circuit patterns formed on the insulation layer to be bonded to the vias; wherein the via has a diameter smaller than that of the via hole, and a method of manufacturing a printed circuit board.

Abstract: Described are apparatuses for modular printed circuit boards (PCB) and methods for producing modular PCBs. An apparatus may include a first PCB module with a first pattern of routing structures on one or more layers of the first PCB module. The apparatus may further include a second PCB module with a second pattern of routing structures on one or more layers of the second PCB module. The second pattern of routing structures may be aligned with and electrically coupled to the first pattern of routing structures without connectors. Other embodiments may be described and/or claimed.

Abstract: An ink jet process is used to deposit a material layer to a desired thickness. Layout data is converted to per-cell grayscale values, each representing ink volume to be locally delivered. The grayscale values are used to generate a halftone pattern to deliver variable ink volume (and thickness) to the substrate. The halftoning provides for a relatively continuous layer (e.g., without unintended gaps or holes) while providing for variable volume and, thus, contributes to variable ink/material buildup to achieve desired thickness. The ink is jetted as liquid or aerosol that suspends material used to form the material layer, for example, an organic material used to form an encapsulation layer for a flat panel device. The deposited layer is then cured or otherwise finished to complete the process.

Abstract: Methods of forming microelectronic package structures are described. Those methods/structures may include forming a high density region on a board comprising a first plurality of conductive structures disposed on a dielectric material on the board, wherein the first plurality of conductive structures comprises a first pitch between individual ones of the first plurality of conductive structures. A low density region on the board comprises a second plurality of conductive structures disposed on the dielectric material, wherein the second plurality of conductive structures comprises a second pitch between individual ones of the second plurality of conductive structures, wherein the second pitch is more than about twice the magnitude of the first pitch.

Abstract: A capacitor component includes a capacitor including a plurality of internal electrodes, a capacitor body containing a piezoelectric material disposed in at least regions between the plurality of internal electrodes, and external electrodes connected to the plurality of internal electrodes; and an interposer disposed to be coupled to the capacitor and including a buffer substrate containing a buffer material having a degree of piezoelectricity lower than that of the piezoelectric material, and connection electrodes electrically connected to the external electrodes.

Abstract: One embodiment provides a circuit board having a substrate and an electrode portion which is provided on the substrate. The electrode portion includes: a quadrangular land which is provided on a front surface of the substrate; a solder layer which is laminated on the whole of a front surface of the land; and a pad which is joined to a front surface of the solder layer. When the electrode portion is seen from thereabove, an outer circumferential line of the pad touches each of four sides of the land. Exposed portions where the solder layer is exposed are formed individually at four corners of a front surface of the electrode portion. And, the exposed portions are formed to have the same shape.

Abstract: An interconnection substrate includes: a substrate having a first surface and a second surface opposite the first surface; and a transmission line including two parallel through-hole interconnections that are exposed to the first and second surfaces and are formed inside the substrate. Also, at least one of the two through-hole interconnections includes a narrow portion having a smaller diameter than a diameter of the through-hole interconnection in the first surface and a diameter of the through-hole interconnection in the second surface.

Abstract: An ink jet process is used to deposit a material layer to a desired thickness. Layout data is converted to per-cell grayscale values, each representing ink volume to be locally delivered. The grayscale values are used to generate a halftone pattern to deliver variable ink volume (and thickness) to the substrate. The halftoning provides for a relatively continuous layer (e.g., without unintended gaps or holes) while providing for variable volume and, thus, contributes to variable ink/material buildup to achieve desired thickness. The ink is jetted as liquid or aerosol that suspends material used to form the material layer, for example, an organic material used to form an encapsulation layer for a flat panel device. The deposited layer is then cured or otherwise finished to complete the process.

Abstract: A position detection sensor includes: a linear member; a conductive portion and an insulating portion provided in an outer periphery of the linear member and arranged side by side in a direction of an axis of the linear member; a support member having insulating properties and provided so as to be capable of being relatively advanced or retracted in the direction of the axis with respect to the conductive portion and the insulating portion; and a conductive contact member attached to the support member and configured such that a distal end of the contact member comes in contact with outer surfaces of the conductive portion and the insulating portion by a biasing force toward the outer surfaces of the conductive portion and the insulating portion.

Abstract: A computer module with double-sided memory including a module chassis and a motherboard having first and second sides mounted to the module chassis. A portion of the second side of the motherboard confronts a portion of the module chassis. A central processing unit is mounted to the first side and a first plurality of elongate memory sockets are mounted to the first side and spaced apart a first distance. A second plurality of elongate memory sockets is mounted to the second side of the motherboard and spaced apart by the first distance. The second plurality of elongate memory sockets is parallel to and laterally offset from the first plurality of elongate memory sockets by a second distance approximately half the first distance. One or more memory modules are mated with selected ones of the first and second plurality of memory sockets.

Abstract: Disclosed herein is a device comprising a first package having a first side with a plurality of connectors disposed thereon and a second package mounted on the first package by the connectors. A molding compound is disposed on the first side of the first package and between the first package and the second package. A plurality of stress relief structures (SRSs) are disposed in the molding compound, the plurality of SRSs each comprising a cavity free of metal in the molding compound and spaced apart from each of the plurality of connectors.

Abstract: A semiconductor device has a semiconductor die with a die pad layout. Signal pads in the die pad layout are located primarily near a perimeter of the semiconductor die, and power pads and ground pads are located primarily inboard from the signal pads. The signal pads are arranged in a peripheral row or in a peripheral array generally parallel to an edge of the semiconductor die. Bumps are formed over the signal pads, power pads, and ground pads. The bumps can have a fusible portion and non-fusible portion. Conductive traces with interconnect sites are formed over a substrate. The bumps are wider than the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

Abstract: An optimized ground (GND) network connection is provided between a Quad Small Form-factor Pluggable (QSFP) connector and a printed circuit board (PCB). The optimized GND network creates a “GND Island” around the signal pads by adding GND cage around the signal pads (at the empty corridor and in front of QSFP pads) and GND TH (ground through hole) vias from both sides of signal pads (at the empty corridor and in front of QSFP pads).

Abstract: Representative implementations of devices and techniques provide improved electrical access to components, such as chip dice, for example, disposed within layers of a multi-layer printed circuit board (PCB). One or more insulating layers may be located on either side of a spacer layer containing the components. The insulating layers may have apertures strategically located to provide electrical connectivity between the components and conductive layers of the PCB.

Abstract: A multilayer laminated substrate structure includes plural substrate layers stacked with each other, and a conductive via portion. One of the substrate layers is provided with a through hole. The conductive via portion includes a first signal conductive pad having a first rib, a second signal conductive pad having a second rib, and a conductive body which is disposed in the through hole and is electrically connected to the first rib and the second rib. The first signal conductive pad and the second signal conductive pad are disposed on two opposite surfaces of the substrate layer, and the first rib and the second rib are arranged in a staggered manner in relation to each other.

Abstract: A polyimide precursor including a structural unit represented by the following general formula (1) in a ratio of 50 mol % or more based on the total structural units. In the general formula (1), A is a tetravalent organic group represented by the following general formula (2a), a tetravalent organic group represented by the following general formula (2b), or a tetravalent organic group represented by the following general formula (2c), and B is a divalent organic group represented by the following general formula (3).

Abstract: A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.

Abstract: A curved display device is provided. The curved display device includes: a curved display panel configured to have short sides and long sides; a printed circuit board (PCB) configured to provide signals for driving the curved display panel; and a flexible wiring board including a first portion, which is connected to a first area, a second portion, which is connected to the PCB, and a third portion, which is disposed between the first portion and the second portion and has curved sides, wherein a curvature radius of a first side of the curved sides differs from a curvature radius of a second side of the curved sides.

Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a first metal pillar, a second metal pillar, and an insulating layer. The semiconductor layer includes a first surface, a second surface, and a light emitting layer. The first metal pillar is electrically connected to the second surface. The first metal pillar includes first and second metal layers. The first metal layer is provided between the second surface and at least a part of the second metal layer. The second metal pillar is arranged side by side with the first metal pillar, and electrically connected to the second surface. The second metal pillar includes third and fourth metal layers. The third metal layer is provided between the second surface and at least a part of the fourth metal layer. The insulating layer is provided between the first and second metal pillars.

Abstract: A contact ribbon configured to connect a cable to a substrate includes a plurality of signal contacts, a ground plane, and at least one ground contact extending from the ground plane. The plurality of signal contacts are connected by a support member, and the support member is removable after the plurality of signal contacts are connected to the cable.

Abstract: In a method of manufacturing an element chip for manufacturing a plurality of element chips by dividing a substrate, where the protruding portions, which are exposed element electrodes, are formed on element regions, protection films made of fluorocarbon film are formed on a second surface and side surfaces of the element chip, and a first surface in a gap by exposing the element chip to second plasma after the substrate is divided by etching. Next, the protection films formed on the second surface and the side surfaces of the element chip are removed while leaving at least a part of the protection film formed in the gap by exposing the element chip to third plasma. Therefore, creep-up of a conductive material in a mounting step is suppressed by the left protection film.

Abstract: Connector inserts and receptacles that provide signal paths having desired impedance characteristics. One example may provide a connector system having a connector insert and a connector receptacle. Contacts in the connector insert may form signal paths with corresponding contacts in the connector receptacle. Additional traces in the connector insert and receptacle may be part of these signal paths. The signal paths may have a target or a desired impedance along their lengths such that the power paths electrically appear as transmission lines. Constraints on physical dimensions of the connector insert and connector receptacle contacts may result in variations in impedance along the signal paths. Accordingly, embodiments of the present invention may provide structures to reduce these variations, to compensate for these variations, or a combination thereof.

Abstract: A universal substrate for assembling ball grid array (BGA) type integrated circuit packages has a non-conducting matrix, an array of conducting vias extending between top and bottom surfaces of the matrix, and one or more instances of each of two or more different types of fiducial pairs on the top surface of the matrix. Each instance of each different fiducial pair indicates a location of a different via sub-array of the substrate for a different BGA package of a particular package size. The same substrate can be used to assemble BGA packages of different size, thereby avoiding having to design a different substrate for each different BGA package size.

Abstract: An apparatus including a substrate; at least one conductive path extending over the substrate and including a first portion of indium tin oxide connected in electrical series to a second portion of a different conductor.

Abstract: A printed wiring board includes conductive layers laminated with insulator layers interposed. A land group including a plurality of lands arranged with intervals between each other, is formed in a rectangular region on a surface layer, among the plurality of conductive layers, when viewed in a direction perpendicular to the surface layer. The land group is arrayed in a triangular lattice manner. The land group is arranged so that a smallest angle, among angles formed between one side of the rectangular region and respective three sides of the triangular lattice, is 7° or more and 23° or less.

Abstract: A force-sensitive resistor (FSR) assembly includes first and second electrically insulative substrates. The first substrate includes a first top surface and a first bottom surface. The second substrate includes a second top surface and a second bottom surface. The first substrate is positioned such that the first bottom surface is disposed facing the second top surface. The FSR assembly also includes thermoset ink disposed between the first substrate and the second substrate.

Abstract: The electric part to be soldered to a metal pad mounted on a printed circuit board, includes a first surface facing the metal pad, a second surface extending from the first surface in a direction away from the metal pad, and a third surface outwardly extending from the second surface, the second surface and the third surface defining a space in which solder is stored.

Abstract: A semiconductor package may include a first substrate including a first connection portion disposed on a surface of the first substrate and a second substrate including a second connection portion disposed on a surface of the second substrate. The second substrate may be disposed over the first substrate and the second connection portion facing the first connection portion. A first connection loop portion may be provided to include an end connected to the first connection portion. A second connection loop portion may be provided to include one end connected to the second connection portion and the other end combined with the first connection loop portion.

Abstract: A printed circuit board is disclosed, comprising a plate body, a conductive pattern disposed on the plate body, a conductive metal plate, and a metal layer. The conductive metal plate has a first terminal and a second terminal, wherein the first terminal and the second terminal are fixed to the plate body. An accommodating space is between the conductive metal plate and the plate body. The metal layer covers the conductive metal plate and the conductive pattern, and is filled into the accommodating space. Therefore, a printed circuit board which has metal blocks with enough thickness is provided. The metal blocks can provide sufficiently low resistance to increase resistance efficiency of the printed circuit.

Abstract: An electronic component mounting structure includes a first land, a second land making a pair with the first land, an electronic component having a chip shape and including a first electrode connected to the first land and a second electrode connected to the second land, a first wiring pattern connected to the first land, and a second wiring pattern connected to the second land and including a first partial pattern overlapping a portion of a body of the electronic component in planar view, the portion being not covered with the pair of electrodes, a second partial pattern formed integral with the first partial pattern and overlapping the first electrode of the electronic component in planar view, and a third partial pattern formed integral with the second partial pattern and parallel to the first wiring pattern.

Abstract: To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.

Abstract: A window structure includes a window, a design layer structure on the window, a light shield layer on the design layer structure, and a light absorption layer. The design layer structure includes a first hole exposing a portion of the window. The light shield layer includes a second hole in fluid communication with the first hole. The light absorption layer covers at least a portion of the design layer structure exposed by the first and second holes, and includes a third hole exposing a portion of the window. By including the light absorption layer of a gray or black color to cover exposed portions of the design layer structure, a vignette about an image caused by the design layer structure is prevented.

Abstract: A printed circuit board includes: a core insulating layer including a glass fiber; a first insulating layer on an upper portion or a lower portion of the core insulating layer, the first insulating layer including a first circuit pattern groove; a first circuit pattern filling the first circuit pattern groove of the first insulating layer; a second insulating layer covering the first circuit pattern and including a second circuit pattern groove at a top surface thereof; and a second circuit pattern filling the second circuit pattern groove of the second insulating layer, wherein the first insulating layer includes a resin material and a filler distributed in the resin material. Accordingly, a total thickness of the PCB can be thinly formed while maintaining the stiffness by separately forming a thin insulating layer without a glass fiber for the buried pattern on the core insulating layer.

Abstract: A multi-chip module and method of fabricating a multi-chip module. The multi-chip module includes: a substrate having a top surface and a bottom surface and containing multiple wiring layers, first pads on the top surface of the substrate and second pads on the bottom surface of the substrate; a first active component attached to a first group of the first pads and a second active component attached to a second group of the first pads; wherein at least one pad of the second pads is a split pad having a first section and a non-contiguous second section separated by a gap, the first section connected by a first wire of the multiple wires to a pad of the first group of first pads and the second section is connected by a second wire of the multiple wires to a pad of the second group of first pads.

Abstract: An interconnect for an installation environment adapted for housing at least one electrical component having a number of first connectors each having a first configuration, wherein the installation environment has pre-installed wiring having a number of second connectors each having a second configuration. The interconnect includes a backplane component including a number of third connectors adapted to connect with the number of first connectors, and a number of fourth connectors adapted to connect with the number of second connectors, wherein each of the number of fourth connectors is coupled to a respective one of the number of third connectors in a manner that maps the second configuration to the first configuration, and includes a mechanical bracket component adapted to allow for the installation of at least one electrical component such that the first connectors are connected to the third connectors.

Abstract: A package includes a semiconductor chip. The semiconductor chip includes a test pad, and a plurality of microbump pads, wherein each microbump pad of the plurality of microbump pads is electrically connected to the test pad. The package further includes a substrate; and a plurality of microbumps configured to electrically connect the semiconductor chip to the substrate, wherein each microbump of the plurality of microbumps is electrically connected to a corresponding microbump pad of the plurality of microbump pads. The package further includes a package substrate, wherein the package substrate comprises a bump pad, wherein an area of the bump pad is greater than a combined area of the test pad and the plurality of microbump pads. The package further includes a bump configured to electrically connect the substrate to the package substrate.

Abstract: A microelectronic unit includes microelectronic elements having memory storage arrays. First terminals and second terminals at a surface of the microelectronic unit are configured for connection with corresponding first and second sets of circuit panel contacts which are coupled with conductors of a common signaling bus on the circuit panel. Front surfaces of first and second microelectronic elements define a plurality of first planes at a substantial angle to a second plane defined by the major surface of the circuit panel. Each of a plurality of delay elements within the microelectronic unit is electrically coupled with a signaling path of the common signaling bus between one of the first terminals and a corresponding second terminal. In such way, the delay elements may reduce adverse effects of additive signal energy reflected from the microelectronic packages back towards the common signaling bus.

Abstract: A package includes a device die, a molding material molding the device die therein, and a plurality of redistribution lines overlying the device die and the molding material. A laser mark pad is coplanar with one of the plurality of redistribution lines, wherein the laser mark pad and the one of the plurality of redistribution layers are formed of the same conductive material. A polymer layer is over the laser mark pad and the plurality of redistribution lines. A tape is attached over the polymer layer. A laser mark penetrates through the tape and the polymer layer. The laser mark extends to a top surface of the laser mark pad.

Abstract: In a multilayer substrate, a quasi-coaxial line is formed as a structure for transmitting a high-frequency signal generated by a mounted high-frequency device from an uppermost layer to a lowermost layer to externally output and for transmitting an externally input high-frequency signal from the lowermost layer to the high-frequency device. The quasi-coaxial line has: a central conductor being a vertical through hole via that connects between a metal pattern formed on an upper surface of the uppermost layer and a metal pattern formed on a lower surface of the lowermost layer; and outer conductors being a plurality of interlayer vias that are circularly arranged around the central conductor and connect between two or more layers. Whole or a part of the vertical through hole via is substituted by a capacitor structure formed of conductor pads facing each other without any via.

Abstract: The present description relates to the field of fabricating microelectronic devices, wherein a microelectronic device may have a hexagonal confirmation for signal nodes and ground nodes which utilizes the cross-talk reduction by cancellation property of geometrically symmetry and orthogonality to reduce signal node to ground node ratio for increasing signaling density.

Abstract: A method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is produced, which comprises a semiconductor chip with metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines. A substrate is provided which has elongated copper leads with first and second surfaces, the leads oriented at right angles to the lines. The first surface of each lead is connected to the corresponding bumps of alternating lines using solder elements. Finally, the assembly is encapsulated in molding compound so that the second lead surfaces remain un-encapsulated.