Abstract: Some embodiments of the present invention provide processes and apparatus for electrochemically fabricating multilayer structures (e.g. mesoscale or microscale structures) with improved endpoint detection and parallelism maintenance for materials (e.g. layers) that are planarized during the electrochemical fabrication process. Some methods involve the use of a fixture during planarization that ensures that planarized planes of material are parallel to other deposited planes within a given tolerance. Some methods involve the use of an endpoint detection fixture that ensures precise heights of deposited materials relative to an initial surface of a substrate, relative to a first deposited layer, or relative to some other layer formed during the fabrication process. In some embodiments planarization may occur via lapping while other embodiments may use a diamond fly cutting machine.
Type:
Application
Filed:
January 23, 2012
Publication date:
July 19, 2012
Inventors:
Uri Frodis, Adam L. Cohen, Michael S. Lockard
Abstract: One embodiment relates to a substrate carrier for use in electroplating a plurality of substrates. The substrate carrier includes a non-conductive carrier body on which the substrates are held, and conductive lines are embedded within the carrier body. A conductive bus bar is embedded into a top side of the carrier body and is conductively coupled to the conductive lines. A thermoplastic overmold covers a portion of the bus bar, and there is a plastic-to-plastic bond between the thermoplastic overmold and the non-conductive carrier body. Other embodiments, aspects and features are also disclosed.
Abstract: Methods for plating substrates are herein defined. One method includes providing a plating assembly having a plating source in a plating fluid and a plating facilitator in the plating fluid, and defining a plating meniscus between the plating source and the plating facilitator. The plating meniscus being contained in a path of the plating assembly. The method further includes traversing a substrate through the path of the plating assembly. The substrate being charged so that plating ions are attracted to a surface of the substrate when the plating meniscus is present on the surface of the substrate, wherein the substrate traversing through the path of the plating assembly enables plating across the surface of the substrate. And, inducing a uniform charge in the path where the plating meniscus is formed, such that charge from the plating source is substantially uniformly directed toward the plating facilitator as the substrate that is charged moves through the path of the plating assembly.
Type:
Grant
Filed:
October 6, 2010
Date of Patent:
July 17, 2012
Assignee:
Lam Research Corporation
Inventors:
Carl A. Woods, Yezdi N. Dordi, Jacob Wylie, Robert Maraschin
Abstract: One embodiment relates to a substrate carrier for use in electroplating a plurality of substrates. The carrier includes a non-conductive carrier body on which the substrates are placed and conductive lines embedded within the carrier body. A plurality of conductive clip attachment parts are attached in a permanent manner to the conductive lines embedded within the carrier body. A plurality of contact clips are attached in a removable manner to the clip attachment parts. The contact clips hold the substrates in place and conductively connecting the substrates with the conductive lines. Other embodiments, aspects and features are also disclosed.
Type:
Grant
Filed:
September 23, 2010
Date of Patent:
July 17, 2012
Assignee:
SunPower Corporation
Inventors:
Chen-An Chen, Emmanuel Chua Abas, Edmundo Anida Divino, Jake Randal G. Ermita, Jose Francisco S. Capulong, Arnold Villamor Castillo, Diana Xiaobing Ma
Abstract: A method of forming a metal feature on a workpiece with deposition is provided. The method includes providing an under bump metal layer for solder of an electronic device on the workpiece, depositing a substantially pure tin layer directly to the under bump metal layer, and depositing a tin silver alloy layer onto the substantially pure tin layer.
Type:
Application
Filed:
December 17, 2010
Publication date:
June 21, 2012
Applicant:
Nexx Systems, Inc.
Inventors:
Arthur Keigler, Johannes Chiu, Zhenqiu Liu, Daniel Goodman
Abstract: The present invention provides improved methods and devices for electroplating copper on a wafer. Some implementations of the present invention involve the pre-treatment of the wafer with a solution containing accelerator molecules. Preferably, the bath into which the wafer is subsequently placed for electroplating has a reduced concentration of accelerator molecules. The pre-treatment causes a reduction in roughness of the electroplated copper surface, particularly during the initial phases of copper growth.
Type:
Grant
Filed:
December 17, 2010
Date of Patent:
June 12, 2012
Assignee:
Novellus Systems, Inc.
Inventors:
Eric Webb, Jonathan D. Reid, Yuichi Takada, Timothy Archer
Abstract: A device and a method for metallic electrolytic coating of an object of electrically conductive material, wherein the object has at least two surface portions that are desired to be coated with layers of different thicknesses. The device includes an anode. The device is designed to receive the object in such a way that the object constitutes a cathode and that, upon receipt of the object, a space is formed for receiving a liquid-absorbing material and an electrolyte for coating the object. The body of the anode includes at least two surface portions) that have different electrical conductivity and that are arranged opposite to the surface portions of the received object.
Abstract: The present invention is related to a method for masked anodization of an anodizable layer on a substrate, for example an aluminum layer present on a sacrificial layer, wherein the sacrificial layer needs to be removed from a cavity comprising a Micro or Nano Electromechanical System (MEMS or NEMS). Anodization of an Al layer leads to the formation of elongate pores, through which the sacrificial layer can be removed. According to the method of the invention, the anodization of the Al layer is done with the help of a first mask which defines the area to be anodized, and a second mask which defines a second area to be anodized, said second area surrounding the first area. Anodization of the areas defined by the first and second mask leads to the formation of an anodized structure in the form of a closed ring around the first area, which forms a barrier against unwanted lateral anodization in the first area.
Abstract: A composition comprising at least one source of metal ions and at least one additive obtainable by reacting a poly-hydric alcohol comprising at least 5 hydroxyl functional groups with at least a first alkylene oxide and a second alkylene oxide from a mixture of the first alkylene oxide and the second alkylene oxide or a third alkylene oxide, a second alkylene oxide, and a first alkylene oxide in aforesaid sequence, the third alkylene oxide having a longer alkyl chain than the second alkylene oxide and the second alkylene oxide having a longer alkyl chain than the first alkylene oxide.
Type:
Application
Filed:
July 19, 2010
Publication date:
May 17, 2012
Applicant:
BASF SE
Inventors:
Cornelia Roeger-Goepfert, Roman Benedikt Raether, Dieter Mayer, Alexandra Haag, Charlotte Emnet
Abstract: A method of fluid sealing a workpiece is provided. The method includes providing a force to cause a ring to form a barrier to fluid entry with the workpiece and preventing fluid from crossing the barrier to fluid entry by forming a pressure differential across the barrier.
Type:
Grant
Filed:
May 28, 2010
Date of Patent:
May 1, 2012
Assignee:
NEXX Systems, Inc.
Inventors:
Arthur Keigler, Qunwei Wu, Zhenqiu Liu, John Harrell
Abstract: Disclosed is an electrochemical etching system with localized etching capability. The system allows multiple different porous semiconductor regions to be formed on a single semiconductor wafer. Localized etching is achieved through the use of one or more stationary and/or movable computer-controlled inner containers operating within an outer container. The outer container holds the electrolyte solution and acts as an electrolyte supply source for the inner container(s). The inner container(s) limit the size of the etched region of the semiconductor wafer by confining the electric field. Additionally, the current amount passing through each inner container during the electrochemical etching process can be selectively adjusted to achieve a desired result within the etched region. Localized etching of sub-regions within each etched region can also be achieved through the use of different stationary and/or moveable electrode structures and shields within each inner container.
Type:
Grant
Filed:
January 29, 2009
Date of Patent:
April 17, 2012
Assignees:
International Business Machines Corporation, Advanced Micro Devices, GlobalFoundries Inc.
Inventors:
Matthew J. Sendelbach, Alok Vaid, Shahin Zangooie
Abstract: A method for making a film having an array of cobalt selenide nanowires including: providing an aluminum substrate; anodizing the aluminum substrate to form anodized aluminum including an aluminum oxide layer having a plurality of pores therein on a surface of the aluminum substrate; preparing an electrodeposition composition including a source of cobalt ions and a source of selenite ions; contacting the anodized aluminum with the electrodeposition composition; and applying AC current to the anodized aluminum for a sufficient duration to electrodeposit cobalt selenide into the pores to form a film having an array of oriented cobalt selenide nanowires. According to a different aspect, a film has an aluminum substrate; an oxide layer having a plurality of pores therein on a surface of the aluminum substrate; and an array of cobalt selenide nanowires disposed in the pores.
Abstract: A method of manufacturing a nozzle plate has steps of: (e) covering a surface of a plate with a light-curable resin; (f) covering the resin with a light-shielding member having an annular light-shielding region which encloses an opening of a nozzle hole therein in a plan view; (g) curing a portion of the resin not overlapping the light-shielding region by applying light after the step of (f); (h) exposing the resin by removing the light-shielding member after the step of (g); (i) eliminating an uncured portion of the resin after the step of (h); (j) forming a water-repellent coat on surfaces of the plate using the cured resins as masks, after the steps of (d) and (i); and (k) eliminating the cured resins after the step of (j).
Abstract: Polycrystalline monolithic magnesium aluminate spinels are disclosed. The polycrystalline monolithic magnesium aluminate spinels have small grain sizes and may be deposited on substrates as thick one-piece deposits. The polycrystalline monolithic magnesium aluminate spinels may be prepared and deposited by chemical vapor deposition. Articles made with the polycrystalline monolithic magnesium aluminate spinels also are disclosed.
Abstract: A swage mount that includes a flange, having a first side and a second side, and a cylindrically shaped hub. The hub is primarily comprised of a metal (such as stainless steel), and extends from the second side of the flange, and has an inner surface and an outer surface. The surface of the swage mount is plated with one or more layers of metal, or a combination of metals, which provide a) increased retention torque, and b) increased part cleanliness. This invention may be used in conjunction with surface hardened swage mounts that contain surface protrusions. In this case the metal plating prevents separation of the protrusions from the swage mount, thereby preventing contamination.
Type:
Grant
Filed:
September 22, 2010
Date of Patent:
March 27, 2012
Assignee:
Intri-Plex Technologies, Inc.
Inventors:
Damon D. Brink, Ryan Schmidt, Kevin Hanrahan, Jack Bish
Abstract: A painting apparatus for applying a coating material to a member surface of a member comprises a housing, at least one slide rail, a rack assembly, a cross beam and a spraying device. The slide rail may be mountable within the housing and may have a plurality of rack positions. The rack assembly is mountable within the housing at one of the rack positions. The rack assembly is configured to support the member such that the member surface is exposed. The cross beam may be coupled to the slide rail. The cross beam is movable along the slide rail and is positionable at the rack positions. The spraying device is mountable on the cross beam and is configured to move along the cross beam while spraying the coating material onto the member surface.
Abstract: The steps of the present invention are as follows: (a) a detachable film is formed on both sides of a substrate, respectively; (b) a number of vias running through both sides of the detachable films are formed in the substrate; (c) the vias are filled with a conductive paste; (d) the detachable films are peeled off; (e) a metallic conductive layer is deposited on both sides of the substrate, respectively; (f) a specific mold pattern is formed on the metallic conductive layers, respectively, by a photolithographic process; (g) a metallic circuit layout layer is formed on the patterns, respectively, by an electrochemical process; and (h) the mold patterns and the metallic conductive layers are removed. As such, the substrate is not contaminated by the conductive paste. Further, by using deposition, metallic conductive layers are directly adhered to the substrate and, by using photolithography, layouts with small linewidth could be formed.
Type:
Application
Filed:
September 13, 2010
Publication date:
March 15, 2012
Inventors:
Shih-Long Wei, Sheng-Li Hsiao, Chien-Hung Ho, Hsiao-Chun Liu
Abstract: A manufacturing method of a substrate for a semiconductor package includes a resist layer forming step to form a resist layer on a surface of a conductive substrate; an exposure step to expose the resist layer using a glass mask with a mask pattern including a transmission area, a light shielding area, and an intermediate transmission area, wherein transmittance of the intermediate transmission area is lower than that of the transmission area and is higher than that of the light shielding area; a development step to form a resist pattern including a hollow with a side shape including a slope part decreasing in hollow circumference as the hollow circumference approaches the substrate; and a plating step to plate on an exposed area to form a metal layer with a side shape including a slope part decreasing in circumference as the circumference approaches the substrate.
Abstract: The invention relates to a method for producing at least one hydrophilic area on a hydrophobic substrate. The method consists in performing an electrochemical reduction of the surface under the following conditions: the reduction is performed in an electrochemical cell which contains an electrolytic solution containing a compound that is a precursor of a reducing agent, said compound having a standard potential of less than ?2.7 V relative to the saturated calomel electrode (SCE); the reducing electrode is placed relative to the substrate surface to be treated such that said surface is facing the surface of the electrode, which is the image of the area to be reduced; the reducing electrode is subjected to the formation potential of the reducing agent.
Type:
Grant
Filed:
June 6, 2006
Date of Patent:
March 13, 2012
Assignee:
Centre National de la Recherche Scientifique
Abstract: A method of surface printing and electric plating, it is to perform pre-plating to form a pre-plated layer firstly on a surface of a metallic or non-metallic article to be plated, thereby the metallic or non-metallic surface will not be oxidized, and to perform printing and then electric plating to make the plated layer higher than the electric printed layer, thus an effect of 3 dimensions can be resulted; and the printing oil ink is protected in the plated layer, thereby it is not subjected to being stripped off by abrasion.
Abstract: Transparent conductive coated devices (films, three dimensional objects and others) produced through coating with a nano metal containing emulsion which forms a conductive pattern with enhanced electrical, optical and other properties.
Type:
Grant
Filed:
June 9, 2006
Date of Patent:
January 31, 2012
Assignee:
Cima NanoTech Israel Ltd.
Inventors:
Arkady Garbar, Claudio Rottman, Fernando De La Vega, Jon Brodd
Abstract: Composition comprising a source of metal ions and at least one suppressing agent obtainable by reacting a) an amine compound comprising at least three active amino functional groups with b) a mixture of ethylene oxide and at least one compound selected from C3 and C4 alkylene oxides.
Type:
Application
Filed:
March 31, 2010
Publication date:
January 26, 2012
Applicant:
BASF SE
Inventors:
Cornelia Roeger-Goepfert, Roman Benedikt Raether, Charlotte Emnet, Alexandra Haag, Dieter Mayer
Abstract: A bumper molding is fabricated by disposing segmented anodes 31 and 32 on surfaces 22 and 24 of a base material 20, which are to be plated, and performing electroplating so as to form metal films on the surfaces 22 and 24, respectively. The curvature of a surface of a concave portion, which is formed in each part of the surfaces 22 and 24 so that the surface of the concave portion is away from the segmented anodes 31 and 32, respectively, is larger than those of other portions at a part serving as a border between the second plated surface 22 and the fourth plated surface 24. Accordingly, the distance from the part serving as the border between the second plated surface 22 and the fourth plated surface 24 to a metal case 50a corresponding to this part is set so as to be shorter than those from each of the other parts to the metal cases 50a and 50b respectively corresponding to the segmented anodes 31 and 32.
Abstract: A chemical treatment apparatus and a method for performing a chemical treatment of a wafer, etc., by supplying a chemical via a cell. The apparatus includes a cylindrical inner cell and a cylindrical outer cell with open ends disposed at an outer circumference of the inner cell. The outer cell is axially movable to vary the width of a slit formed between a bottom end of the outer cell and a top surface of the substrate-holding means by the axial movement, thereby adjusting the discharge rate of the chemical and varying the pressure of the chemical.
Abstract: Disclosed is a plating method including: performing plating on a plating surface of a plating substrate with a cathode electrode contacting an area in an outer circumferential section of the plating substrate where the cathode electrode is to be contacted, the plating substrate being provided with a dummy plating area between the area where the cathode electrode is to be contacted and a product area on the plating surface of the plating substrate, by supplying a plating solution to the plating surface of the plating substrate and applying electric current between the cathode electrode and an anode electrode via the plating solution.
Abstract: Numerous electrochemical fabrication methods and apparatus are provided for producing multi-layer structures (e.g. having meso-scale or micro-scale features) from a plurality of layers of deposited materials using adhered masks (e.g. formed from liquid photoresist or dry film), where two or more materials may be provided per layer where at least one of the materials is a structural material and one or more of any other materials may be a sacrificial material which will be removed after formation of the structure. Materials may comprise conductive materials that are electrodeposited or deposited in an electroless manner. In some embodiments special care is undertaken to ensure alignment between patterns formed on successive layers.
Type:
Application
Filed:
August 9, 2011
Publication date:
December 29, 2011
Inventors:
Adam L. Cohen, Jill R. Thomassian, Michael S. Lockard, Marvin M. Kilgo, III, Uri Frodis, Dennis R. Smalley
Abstract: Disclosed herein is a method of making a three dimensional mold comprising the steps of providing a mold substrate; exposing the substrate with an electromagnetic radiation source for a period of time sufficient to render the portion of the mold substrate susceptible to a developer to produce a modified mold substrate; and developing the modified mold with one or more developing reagents to remove the portion of the mold substrate rendered susceptible to the developer from the mold substrate, to produce the mold having a desired mold shape, wherein the electromagnetic radiation source has a fixed position, and wherein during the exposing step, the mold substrate is manipulated according to a manipulation algorithm in one or more dimensions relative to the electromagnetic radiation source; and wherein the manipulation algorithm is determined using stochastic optimization computations.
Type:
Grant
Filed:
March 31, 2009
Date of Patent:
December 13, 2011
Assignee:
The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
Abstract: Embodiments are directed to methods for forming multi-layer three-dimensional structures involving the joining of at least two structural elements, at least one of which is formed as a multi-layer three-dimensional structure, wherein the joining occurs via one of: (1) elastic deformation and elastic recovery and subsequent retention of elements relative to each other, (2) relative deformation of an initial portion of at least one element relative to another portion of the at least one element until the at least two elements are in a desired retention position after which the deformation is reduced or eliminated and a portion of at least one element is brought into position which in turn locks the at least two elements together via contact with one another including contact with the initial portion of at least one element, or (3) moving a retention region of one element into the retention region of the other element, without deformation of either element, along a path including a loading region of the other el
Type:
Grant
Filed:
December 29, 2008
Date of Patent:
December 6, 2011
Assignee:
Microfabrica Inc.
Inventors:
Adam L. Cohen, Vacit Arat, Michael S. Lockard, Dennis R. Smalley
Abstract: Methods for the preparation of long, dimensionally uniform, metallic nanowires that are removable from the surface on which they are synthesized. The methods include the selective electrodeposition of metal nanowires at step edges present on a stepped surface, such as graphite, from an aqueous solution containing a metal or metal oxide. Where a metal oxide is first deposited, the metal oxide nanowires are reduced via a gas phase reduction at elevated temperatures to metal nanowires. Alternatively, beaded or hybrid nanowires comprising a metal A into which nanoparticles of a metal B have been inserted may be prepared by first electrodepositing nanoparticles of metal B selectively along step edges of a stepped surface, capping these nanoparticles with a molecular layer of an organic ligand, selectively electrodepositing nanowire segments of metal A between nanoparticles of metal B and then heating the surface of the hybrid nanowire under reducing conditions to remove the ligand layer.
Type:
Grant
Filed:
April 30, 2007
Date of Patent:
December 6, 2011
Assignee:
The Regents of the University of California
Inventors:
Reginald Mark Penner, Michael Paul Zach, Fred Favier
Abstract: One inventive aspect relates to a method for forming hermetically sealed cavities, e.g. semiconductor cavities comprising fragile devices, MEMS or NEMS devices. The method allows forming hermetically sealed cavities at a controlled atmosphere and pressure and at low temperatures, for example, at temperatures not exceeding about 200° C. The method further allows forming sealed cavities with short release times, for example, release times of about a few minutes to 30 minutes. The method may, for example, be used for zero level packaging of MEMS or NEMS devices.
Type:
Grant
Filed:
March 28, 2007
Date of Patent:
November 22, 2011
Assignee:
IMEC
Inventors:
Ann Witvrouw, Raquel Hellin Rico, Jean-Pierre Celis
Abstract: A method includes forming a first substrate by (a) applying an electrodepositable dielectric coating onto a conductive surface; (b) curing the dielectric coating; (c) depositing an adhesion layer and a seed layer onto the dielectric coating; (d) applying a layer of a first removable material to the seed layer; (e) forming openings in the first removable material to expose areas of the seed layer; (f) electroplating a first conductive material to the exposed areas of the seed layer; (g) applying a layer of a second removable material; (h) forming openings in the second removable material to expose areas of the first conductive material; (i) plating a second conductive material to the exposed areas of the first conductive material; (j) removing the first and second removable materials; (k) removing unplated portions of the seed layer; repeating steps (a) through (k) to form a second substrate; and laminating the first and second substrates together with a layer of dielectric material between the first and secon
Abstract: Several techniques are described for reducing or mitigating the formation of seams and/or voids in electroplating the interior regions of microscopic recessed features. Cathodic polarization is used to mitigate the deleterious effects of introducing a substrate plated with a seed layer into an electroplating solution. Also described are diffusion-controlled electroplating techniques to provide for bottom-up filling of trenches and vias, avoiding thereby sidewalls growing together to create seams/voids. A preliminary plating step is also described that plates a thin film of conductor on the interior surfaces of features leading to adequate electrical conductivity to the feature bottom, facilitating bottom-up filling.
Type:
Grant
Filed:
September 16, 2005
Date of Patent:
November 1, 2011
Assignee:
Novellus Systems, Inc.
Inventors:
Steven T. Mayer, Vijay Bhaskaran, Evan E. Patton, Robert L. Jackson, Jonathan Reid
Abstract: A method is disclosed for depositing a copper seed layer onto a substrate surface. In one embodiment, the method includes providing a substrate having a barrier layer disposed on a substrate surface, wherein the barrier layer has a barrier surface comprising a material selected from the group consisting of cobalt, ruthenium, tungsten, titanium, and a compound of two or more thereof, and exposing the substrate to a non-complexed, acid electrochemical plating solution with a plating bias applied across the substrate surface to deposit a copper-containing seed layer directly on the barrier surface without intervening layer disposed therebetween.
Abstract: A method of patterning and an article having a patterned structure defined therein are provided. The method comprises the steps of providing a substrate having a patterned conductive metal film disposed thereon. The patterned conductive metal film has at least one raised feature. The patterned conductive metal film defines at least one recess therein that is adjacent to the at least one raised feature. A surface of the substrate is exposed in the at least one recess. The pattern is modified through electrolysis in an electrodeposition setup including an electrolyte and two electrodes. The patterned conductive metal film is one of the electrodes during electrolysis. The method is ideal for shrinking initial patterns having features that are on the magnitude of microscale dimensions to obtain a final pattern having features that are on the magnitude of nanoscale dimensions.
Abstract: Methods and structures for electroplating shield structures for perpendicular thin film write poles having ultra thin non-magnetic top gaps on the order of a few nanometers are disclosed. Ultra thin, conductive seed layers serve a dual purpose as both plating seed layer and non-magnetic top gap for the write pole. Due to reduced current carrying capacity of ultra thin seed layers, an additional thick seed layer is also employed to aid delivering plating current to regions near the pole.
Type:
Grant
Filed:
December 26, 2007
Date of Patent:
September 20, 2011
Assignee:
Hitachi Global Storage Technologies Netherlands B.V.
Inventors:
Christian Rene Bonhote, Quang Le, Xhavin Sinha
Abstract: This invention pertains generally to compositions and a method for making films, nanostructures and nanowires in templates and on substrates, including but not limited to metal-semiconductor nanostructures and semiconductor nanostructures on semiconductor substrates, and a device having the same. Particularly described are methods for making cobalt antimonide nanostructures on gold and Co—Sb substrates.
Type:
Application
Filed:
March 3, 2011
Publication date:
September 15, 2011
Inventors:
Ruxandra Vidu, Dat Quach, Pieter Stroeve
Abstract: Metal nanoparticles are assembled in interrupted metal strands or other structures of characteristic dimensions and orientation to generate a giant dielectric response through a modified GE effect. Careful selection and modification of the host material and synthesis also leads to low dielectric breakdown voltages. In addition, the high dielectric composite material is employed in material configurations that are more scalable for industrial and consumer applications.
Abstract: A method of forming three-dimensional structures includes forming a conductive layer on a substrate and patterning a resist layer over the conductive layer, the resist layer having contained therein a plurality of vias. An electrically conductive polymer is then electro-deposited in the vias. The electro-deposition operation is then stopped to form one or more of posts, posts having bulbous termini (i.e., mushrooms), or a layer atop the resist layer. The resist may be removed to yield the structure which may be further processed. For example, the structure may be pyrolyzed. In addition, biomolecules may also be adhered or otherwise affixed to the structure.
Abstract: A method and composition for electroplating Cu onto a substrate in the manufacture of a microelectronic device involving and electrolytic solution containing a source of Cu ions and a substituted pyridyl polymer compound for leveling.
Type:
Grant
Filed:
October 12, 2004
Date of Patent:
August 23, 2011
Assignee:
Enthone Inc.
Inventors:
Vincent Paneccasio, Xuan Lin, Paul Figura, Richard Hurtubise
Abstract: Disclosed herein are electrochemical fabrication platforms for making structures, arrays of structures and functional devices having selected nanosized and/or microsized physical dimensions, shapes and spatial orientations. Methods, systems and system components use an electrochemical stamping tool such as solid state polymeric electrolytes for generating patterns of relief and/or recessed features exhibiting excellent reproducibility, pattern fidelity and resolution on surfaces of solid state ionic conductors and in metal. Electrochemical stamping tools are capable high throughput patterning of large substrate areas, are compatible with commercially attractive manufacturing pathways to access a range of functional systems and devices including nano- and micro-electromechanical systems, sensors, energy storage devices, metal masks for printing, interconnects, and integrated electronic circuits.
Type:
Grant
Filed:
May 19, 2008
Date of Patent:
August 16, 2011
Assignee:
The Board of Trustees of the University of Illinois
Inventors:
Nicholas X. Fang, Placid M. Ferreira, Keng Hao Hsu, Peter Lee Schultz, Kyle E. Jacobs, Anil Kumar
Abstract: An electroplating method that includes: a) contacting a first substrate with a first article, which includes a substrate and a conformable mask disposed in a pattern on the substrate; b) electroplating a first metal from a source of metal ions onto the first substrate in a first pattern, the first pattern corresponding to the complement of the conformable mask pattern; and c) removing the first article from the first substrate, is disclosed. Electroplating articles and electroplating apparatus are also disclosed.
Abstract: A plating method can fill a plated metal into interconnect recesses at a higher rate without forming voids in the plated metal embedded in the interconnect recesses. The plating method includes: preparing a substrate having interconnect recesses in a surface; carrying out first pretreatment of the substrate by immersing the substrate in a first pretreatment solution containing an accelerator, a metal ion and an acid; carrying out second pretreatment of the substrate by immersing the substrate in a second pretreatment solution containing an additive which inhibits the effect of the accelerator contained in the first pretreatment solution, and not containing an accelerator; and then carrying out electroplating of the substrate surface by using a plating solution containing at least a metal ion, an acid and a suppressor, and not containing an accelerator, thereby filling the plated metal into the interconnect recesses.
Abstract: An electroplating method that includes: a) contacting a first substrate with a first article, which includes a substrate and a conformable mask disposed in a pattern on the substrate; b) electroplating a first metal from a source of metal ions onto the first substrate in a first pattern, the first pattern corresponding to the complement of the conformable mask pattern; and c) removing the first article from the first substrate, is disclosed. Electroplating articles and electroplating apparatus are also disclosed.
Abstract: Disclosed herein is a method of preparing a low resistance metal line, in which a wet plating technique is used instead of a vacuum film forming process in order to simplify the process and decrease the manufacturing cost. In addition, a self-assembled monolayer is formed that facilitates the increased adsorption density and strength of the metal catalyst resulting in the formation of a high-density metal catalyst layer, thereby obtaining a high-quality metal line. Also disclosed herein, are a patterned metal line structure, and a display device using the same.
Type:
Application
Filed:
July 26, 2010
Publication date:
July 14, 2011
Applicant:
SAMSUNG ELECTRONICS CO., LTD.
Inventors:
Sung Hen CHO, Ki Yong SONG, Sang Eun PARK
Abstract: Solutions for improving current spreading in organic substrates are disclosed. In one aspect, a packaging substrate is disclosed, the packaging substrate comprising: a substrate base having a first surface and a second surface; and a controlled collapse chip connect (C4) pad over a portion of the first surface, the C4 pad including: an electrolessly plated copper (Cu) layer over the first surface; an electrolytic nickel (Ni) portion over the first electrolytic Cu portion; and a first electrolytic Cu portion over the electrolytic Ni portion; wherein the electrolessly plated Cu layer has a portion extending in one direction away from the C4 pad.
Type:
Application
Filed:
January 7, 2010
Publication date:
July 7, 2011
Applicant:
INTERNATIONAL BUSINESS MACHINES CORPORATION
Abstract: An apparatus for forming a solder dam on each lead of an electronic device includes a mask having one or more slits; and forming means that forms the solder dam made of non-metal material on the lead of the electronic device through the slits of the mask.
Abstract: Multi-layer microscale or mesoscale structures are fabricated with adhered layers (e.g. layers that are bonded together upon deposition of successive layers to previous layers) and are then subjected to a heat treatment operation that enhances the interlayer adhesion significantly. The heat treatment operation is believed to result in diffusion of material across the layer boundaries and associated enhancement in adhesion (i.e. diffusion bonding). Interlayer adhesion and maybe intra-layer cohesion may be enhanced by heat treating in the presence of a reducing atmosphere that may help remove weaker oxides from surfaces or even from internal portions of layers.
Type:
Application
Filed:
February 7, 2011
Publication date:
June 30, 2011
Inventors:
Gang Zhang, Adam L. Cohen, Michael S. Lockard, Ananda H. Kumar, Ezekiel J. J. Kruglick, Kieun Kim
Abstract: Some embodiments of the invention are directed to electrochemical fabrication methods for forming structures or devices (e.g. microprobes for use in die level testing of semiconductor devices) from a core material and a shell or coating material that partially coats the surface of the structure. Other embodiments are directed to electrochemical fabrication methods for producing structures or devices (e.g. microprobes) from a core material and a shell or coating material that completely coats the surface of each layer from which the probe is formed including interlayer regions. Additional embodiments of the invention are directed to electrochemical fabrication methods for forming structures or devices (e.g. microprobes) from a core material and a shell or coating material wherein the coating material is located around each layer of the structure without locating the coating material in inter-layer regions.
Type:
Application
Filed:
October 18, 2010
Publication date:
June 9, 2011
Inventors:
Ming Ting Wu, Rulon Joseph Larsen, III, Young Kim, Kieun Kim, Adam L. Cohen, Ananda H. Kumar, Michael S. Lockard, Dennis R. Smalley
Abstract: A process to form devices may include forming a seed layer on and/or over a substrate, modifying a seed layer selectively, forming an image-wise mold layer on and/or over a substrate and/or electrodepositing a first material on and/or over an exposed conductive area. A process may include selectively applying a temporary patterned passivation layer on a conductive substrate, selectively forming an image-wise mold layer on and/or over a substrate, forming a first material on and/or over at least one of the exposed conductive areas and/or removing a temporary patterned passivation layer. A process may include forming a sacrificial image-wise mold layer on a substrate layer, selectively placing one or more first materials in one or more exposed portions of a substrate layer, forming one or more second materials on and/or over a substrate layer and/or removing a portion of a sacrificial image-wise mold layer.