Coating Selected Area Patents (Class 205/118)
  • Publication number: 20020157956
    Abstract: The invention provides a hole structure through which is formed a deep through-hole having microscopic open ends, and also provides a method of fabricating the same. The hole structure of the invention contains a through-hole having a first open end and a second open end larger in size than the first open end, wherein the size, d, of the second open end is not smaller than 2 &mgr;m and not larger than 50 &mgr;m, and the through-hole has a depth t larger than d but not larger than 15d.
    Type: Application
    Filed: November 13, 2001
    Publication date: October 31, 2002
    Inventor: Tomoo Ikeda
  • Patent number: 6471879
    Abstract: In devices such as flat panel displays, an aluminum oxide layer is provided between an aluminum layer and an ITO layer when such materials would otherwise be in contact to protect the ITO from optical and electrical defects sustained, for instance, during anodic bonding and other fabrication steps. This aluminum oxide barrier layer is preferably formed either by: (1) partially or completely anodizing an aluminum layer formed over the ITO layer, or (2) an in situ process forming aluminum oxide either over the ITO layer or over an aluminum layer formed on the ITO layer. After either of these processes, an aluminum layer is then formed over the aluminum oxide layer.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: October 29, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Robert J. Hanson, Won-Joo Kim, Mike E. Pugh
  • Publication number: 20020153257
    Abstract: The invention relates to sensors of physical quantities such as pressure or acceleration sensors and, more specifically, to the mounting of the active part of the sensor on a base (30) bearing connection pins (32).
    Type: Application
    Filed: April 8, 2002
    Publication date: October 24, 2002
    Inventors: Bertrand Leverrier, Marie-dominique Burni-Marchionni
  • Patent number: 6468806
    Abstract: Methods and apparatus are provided for the preparation of a substrate having an array of diverse materials, the materials being deposited at spatially addressable, predefined regions. In particular, potential masking systems are provided which generate spatially and temporally varying electric, magnetic and chemical potentials across a substrate. These varying potentials are used to deposit components of source materials onto a substrate in a combinatorial fashion, thus creating arrays of materials that differ slightly in chemical composition, concentration, stoichiometry, and/or thickness. The diverse materials may be organized in discrete arrays, or they may vary continuously over the surface of the substrate. The shape of the potential allows the determination of the composition of the resulting materials at all locations on the substrate.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: October 22, 2002
    Assignee: Symyx Technologies, Inc.
    Inventors: Eric McFarland, Earl Danielson, Martin Devenney, Christopher J. Warren
  • Patent number: 6464853
    Abstract: A method of producing a structure having narrow pores includes a first step of bringing pore-guiding members into contact with upper and lower surfaces of a member comprising aluminum as a principal ingredient and a second step of anodizing the member comprising aluminum as the principal ingredient to form narrow pores. The pore-guiding members contain the same material as a principal ingredient. The second step includes preferably a step of transforming the member comprising aluminum as the principal ingredient into a porous body comprising alumina having narrow pores oriented substantially parallel to the interfaces between the pore-guiding members and the member comprising aluminum as the principal ingredient.
    Type: Grant
    Filed: December 23, 1999
    Date of Patent: October 15, 2002
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tatsuya Iwasaki, Tohru Den
  • Publication number: 20020144908
    Abstract: The invention provides for a back-end metallisation process in which a recess is filled with copper and which includes the step of forming a plating base on the surfaces of the recess for the subsequent galvanic deposition of the said copper, and wherein subsequent to the formation of the plating base, but prior to the galvanic deposition of the copper, a modifying agent is introduced to the recess and which serves to absorb in the surface regions not covered by the plating base and to thereby modify the surface to promote copper growth thereon so as to effectively repair the initial plating base before the copper plating fill commences.
    Type: Application
    Filed: April 1, 2002
    Publication date: October 10, 2002
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Eric Alexander Meulenkamp, Maria Jeanne Schroevers
  • Publication number: 20020145826
    Abstract: A method is provided for the preparation of nanoscale particle arrays having highly uniform crystals of metal, semiconductor or insulator materials grown in nanopores in the surface of a substrate, wherein the method uses pulse-reverse electrodeposition of metals with a rectangular or square waveform in order to generate high homogeneity of crystals and high in-plane or out-of-plane anisotropy in a controlled manner, enabling the creation of a variety of devices, including but not limited to high density storage media.
    Type: Application
    Filed: April 9, 2001
    Publication date: October 10, 2002
    Applicant: University of Alabama
    Inventors: Giovanni Zangari, Ming Sun, Robert M. Metzger
  • Patent number: 6461493
    Abstract: A process for fabricating a structure using a metal carrier and forming a double capacitor structure. The process comprises forming a first via hole through the metal carrier, forming a dielectric layer around the metal carrier and inside the first via hole, forming a second via hole through the dielectric layer and the metal carrier, and filling at least one of the via holes with conductive material. In one preferred embodiment, the process further comprises forming a third via hole through the metal carrier before the forming of a dielectric layer, wherein the dielectric layer is formed around the metal carrier, inside the first via hole, and inside the third via hole. The first via hole, the second via hole, and the third via hole are all filled with a conductive material. In one preferred embodiment, the dielectric layer comprises a top surface opposed to a bottom surface, and electrodes are formed on at least one of the top surface and the bottom surface of the dielectric layer.
    Type: Grant
    Filed: December 23, 1999
    Date of Patent: October 8, 2002
    Assignee: International Business Machines Corporation
    Inventors: Mukta S. Farooq, Shaji Farooq, John U. Knickerbocker, Robert A. Rita, Srinivasa N. Reddy
  • Patent number: 6461677
    Abstract: A method of fabricating an electrical component includes the steps of providing a metal electrical component and immersing the component in a bath of resist material. A selected area of the component is prepared by an ink-jet process for reception of a conductive plating material. The plating material is applied to the selected area, and the resist material is removed from the component.
    Type: Grant
    Filed: April 18, 2000
    Date of Patent: October 8, 2002
    Assignee: Molex Incorporated
    Inventors: William J. Copping, Bretton I. Rickett
  • Patent number: 6461680
    Abstract: The present invention relates to a method and apparatus of fabricating electromagnetic coil vanes. The method involves photolithographically exposing high resolution, dense wire patterns in a flash coat of copper, on both sides of a ceramic vane substrate. The substrate can be pre-drilled with a through hole to connect the two copper coil patterns. Additional copper is then deposited on both high resolution patterns and in the through hole by plating until the desired thickness is obtained. A firing operation is then performed that eutectically bonds the copper to the ceramic.
    Type: Grant
    Filed: December 23, 1999
    Date of Patent: October 8, 2002
    Assignee: Nikon Corporation
    Inventor: David J. Pinckney
  • Patent number: 6458263
    Abstract: In the formation of multilevel LIGA microstructures, a preformed sheet of photoresist material, such as polymethylmethacrylate (PMMA) is patterned by exposure through a mask to radiation, such as X-rays, and developed using a developer to remove the exposed photoresist material. A first microstructure is then formed by electroplating metal into the areas from which the photoresist has been removed. Additional levels of microstructure are added to the initial microstructure by covering the first microstructure with a conductive polymer, machining the conductive polymer layer to reveal the surface of the first microstructure, sealing the conductive polymer and surface of the first microstructure with a metal layer, and then forming the second level of structure on top of the first level structure. In such a manner, multiple layers of microstructure can be built up to allow complex cantilevered microstructures to be formed.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: October 1, 2002
    Assignee: Sandia National Laboratories
    Inventors: Alfredo Martin Morales, Linda A. Domeier
  • Publication number: 20020134684
    Abstract: Disclosed is a process flows for treating seed layers including copper such that various problems such as oxidation and insufficient coverage can be repaired in an effective and efficient manner.
    Type: Application
    Filed: October 25, 2001
    Publication date: September 26, 2002
    Applicant: Shipley Company, L.L.C.
    Inventors: Jeffrey M. Calvert, Denis Morrissey, David Merricks
  • Publication number: 20020125143
    Abstract: A method of anodizing an aluminum substrate comprising heating the substrate to a first temperature of 200° C. to about 380° C.; suspending the substrate into a first electrolyte and applying a first anodizing current to the first electrolyte; rinsing the substrate; heating the substrate to a second temperature of 200° C. to about 380° C.; and suspending the substrate into a second electrolyte and applying a second anodizing current to the second electrolyte, wherein the first electrolyte and second electrolyte each comprise an aqueous solution of at least one salt of alpha-hydroxy acid.
    Type: Application
    Filed: March 7, 2001
    Publication date: September 12, 2002
    Inventors: Albert Kennedy Harrington, Brian John Melody, John Tony Kinard, Philip Michael Lessner, David Alexander Wheeler
  • Patent number: 6447663
    Abstract: A method of nanometer-scale deposition of a metal onto a nanostructure includes the steps of: providing a substrate having thereon at least two electrically conductive nanostructures spaced no more than about 50 &mgr;m apart; and depositing metal on at least one of the nanostructures by electric field-directed, programmable, pulsed electrolytic metal deposition. Moreover, a method of nanometer-scale depletion of a metal from a nanostructure includes the steps of providing a substrate having thereon at least two electrically conductive nanostructures spaced no more than about 50 &mgr;m apart, at least one of the nanostructures having a metal disposed thereon; and depleting at least a portion of the metal from the nanostructure by electric field-directed, programmable, pulsed electrolytic metal depletion. A bypass circuit enables ultra-finely controlled deposition.
    Type: Grant
    Filed: October 24, 2000
    Date of Patent: September 10, 2002
    Assignee: UT-Battelle, LLC
    Inventors: James Weifu Lee, Elias Greenbaum
  • Publication number: 20020112964
    Abstract: The present invention provides a composition and method for void-free plating of a metal into high aspect ratio features. The plating process is carried out in a plating solution containing metal at a molar concentration of between about 0.4 M and about 0.9 M, an acid at a concentration of between about 4 mg/L and about 40 mg/L, a suppressor at a concentration of between about 2 mL/L and about 15 mL/L, an accelerator at a concentration of between about 1.5 mL/L and about 8 mL/L, and a leveler at a concentration of between about 4 mL/L and about 11 mL/L.
    Type: Application
    Filed: March 26, 2002
    Publication date: August 22, 2002
    Applicant: Applied Materials, Inc.
    Inventors: Srinivas Gandikota, Chris McGuirk, Deenesh Padhi, Sivakami Ramanathan, Girish Dixit
  • Publication number: 20020112963
    Abstract: Methods are disclosed for manufacturing coils for use in a charged-particle-beam (CPB) optical system such as would be used in a CPB imaging apparatus or CPB lithography apparatus. In an embodiment, on a surface of a coil substrate is formed a mask layer defining channels corresponding to a coil pattern. Using the mask layer as a mask, a pattern of conductive coil-forming material is applied to the substrate surface in the channels. Coil elements formed on the substrate surface by this method exhibit steep sides and a desired aspect ratio. To such end, the depth of the channels desirably is greater than the desired thickness of the coil elements. Alternatively, a metal layer (for use as an electroplating electrode) is formed on a surface of the substrate. The metal layer is coated with a resist at a thickness of at least 0.1 mm. The resist is removed by lithography from regions where coil elements are to be formed. In the regions, conductive metal is grown by electroplating to form the coil elements.
    Type: Application
    Filed: February 22, 2002
    Publication date: August 22, 2002
    Applicant: Nikon Corporation
    Inventors: Katsushi Nakano, Ichiro Ono, Masami Masuko, Akira Okada
  • Publication number: 20020104762
    Abstract: A method is disclosed for the manufacture of colloidal rod particles as nanobarcodes. Template membranes for the deposition of materials are prepared using photolithographic techniques.
    Type: Application
    Filed: October 2, 2001
    Publication date: August 8, 2002
    Inventors: Walter Stonas, Louis J. Dietz, Ian D. Walton, Michael J. Natan, James L. Winkler
  • Publication number: 20020100692
    Abstract: An electrochemical deposition and testing system consisting of individually addressable electrode arrays, a fully automated deposition head, and a parallel screening apparatus is described. The system is capable of synthesizing and screening millions of new compositions at an unprecedented rate.
    Type: Application
    Filed: March 26, 2002
    Publication date: August 1, 2002
    Applicant: Symyx Technologies, Inc.
    Inventors: Christopher J. Warren, Robert C. Haushalter, Leonid Matsiev
  • Publication number: 20020100691
    Abstract: The invention is a method for the fabrication of an imprint tool master. The process begins with a metallic substrate. A layer of photoresist is placed onto the metallic substrate and a image pattern mask is then aligned to the mask. The mask pattern has opaque portions that block exposure light and “open” or transparent portions which transmit exposure light. The photoresist layer is then exposed to light transmitted through the “open” portions of the first image pattern mask and the mask is then removed. A second layer of photoresist then can be placed onto the first photoresist layer and a second image pattern mask may be placed on the second layer of photoresist. The second layer of photoresist is exposed to light, as before, and the second mask removed. The photoresist layers are developed simultaneously to produce a multi-level master mandrel upon which a conductive film is formed. A tool master can now be formed onto the conductive film.
    Type: Application
    Filed: February 12, 2002
    Publication date: August 1, 2002
    Inventors: William D. Bonivert, John T. Hachman
  • Publication number: 20020088714
    Abstract: To provide a plate of high resolution and large area. The channel plate configured by including a substrate, a first electrode placed on the top face of the substrate, and a second electrode placed on the bottom face of the substrate, wherein the substrate is a porous element having a plurality of pores extending therethrough, and the porous element is formed by a compound including aluminum, and the porous element has an electron multiplier on a wall surface of the pore.
    Type: Application
    Filed: October 5, 2001
    Publication date: July 11, 2002
    Inventors: Taiko Motoi, Mitsuru Ohtsuka, Tohru Den, Toshiaki Aiba
  • Publication number: 20020088709
    Abstract: There are provided a method and apparatus for forming interconnects by embedding a metal such as copper (Cu) into recesses for interconnects formed on the surface of a substrate such as a semiconductor substrate. The method of the present invention includes the steps of: providing a substrate having fine recesses formed in the surface; subjecting the surface of the substrate to plating in a plating liquid; and subjecting the plated film formed on the surface of the substrate to electrolytic etching in an etching liquid.
    Type: Application
    Filed: June 27, 2001
    Publication date: July 11, 2002
    Inventors: Akihisa Hongo, Naoki Matsuda, Kanji Ohno, Ryoichi Kimizuka
  • Patent number: 6413403
    Abstract: An apparatus capable of assisting in controlling an electrolyte flow and distribution of an electric field, a magnetic field, or an electromagnetic field in order to process a substrate is provided with improved fluid distribution. A support member having a top surface and a bottom surface contains at least one support member electrolyte channel. Each support member electrolyte channel forms a passage between the top surface and the bottom surface and allows the electrolyte to flow therethrough. A pad is attachable to the support member and contains at least one set of pad electrolyte channels also allowing for electrolyte flow therethrough to the substrate. Each support member electrolyte channel is connected to one set of pad electrolyte channels by fluid distribution structure. A method of assisting in control of the electrolyte flow and distribution of the electric field, the magnetic field, or the electromagnetic field, utilizing the apparatus, is also provided.
    Type: Grant
    Filed: July 21, 2000
    Date of Patent: July 2, 2002
    Assignee: NuTool Inc.
    Inventors: Paul Lindquist, Bulent Basol, Cyprian Uzoh, Homayoun Talieh
  • Publication number: 20020066673
    Abstract: A method for plating copper conductors on an electronic substrate and devices formed are disclosed. In the method, an electroplating copper bath that is filled with an electroplating solution kept at a temperature between about 0° C. and about 18° C. is first provided. A copper layer on the electronic substrate immersed in the electroplating solution is then plated either in a single step or in a dual-step deposition process. The dual-step deposition process is more suitable for depositing copper conductors in features that have large aspect ratios, such as a via hole in a dual damascene structure having an aspect ratio of diameter/depth of more than ⅓ or as high as {fraction (1/10)}. Various electroplating parameters are utilized to provide a short resistance transient in either the single step deposition or the dual-step deposition process.
    Type: Application
    Filed: January 22, 2002
    Publication date: June 6, 2002
    Applicant: International Business Machines Corporation
    Inventors: Kenneth P. Rodbell, Panayotis C. Andricacos, Cyril Cabral, Lynne M. Gignac, Cyprian E. Uzoh, Peter S. Locke
  • Patent number: 6399153
    Abstract: A method and an apparatus for restricting the areas of contact between components to be plated or coated and liquid solutions containing plating or coating agents, without the use of masking tape. Components made of electrically conductive material are suspended underneath a hood or bell housing which is sized and shaped to receive those portions of the components that should not be plated (or coated). Then the suspended components and the hood or bell housing are fully immersed in a bath of plating (or coating) solution, forming an air pocket under the hood or bell housing. This air pocket surrounds those portions of the components which are not to be plated (or coated) and prevents the liquid solution in the bath from touching those portions. The air acts as a mask that prevents paint or metal from contacting or adhering to surfaces not to be plated (or coated).
    Type: Grant
    Filed: October 31, 2000
    Date of Patent: June 4, 2002
    Assignee: Bombardier Motor Corporation of America
    Inventor: Ryan K. Kephart
  • Publication number: 20020064729
    Abstract: Within both a method for forming a patterned photoresist layer and a method for forming an electroplated patterned conductor layer while employing the patterned photoresist layer as a patterned photoresist plating mask layer there is first provided a substrate. There is then formed over the substrate a blanket photoresist layer formed of a negative photoresist material. There is then photoexposed the blanket photoresist layer to form a photoexposed blanket photoresist layer while employing a photoexposure apparatus which employs an annular edge ring exclusion apparatus positioned over an annular edge ring of the blanket photoresist layer and the substrate. Finally, there is then developed the photoexposed blanket photoresist layer to form a patterned photoresist layer having an annular edge ring excluded over the annular edge ring of the substrate.
    Type: Application
    Filed: November 30, 2000
    Publication date: May 30, 2002
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Ming Ching, Sheng-Liang Pan, Hao-Wei Chang, Chun-Hong Chang, Yen-Ming Chen
  • Publication number: 20020053516
    Abstract: A system for depositing materials on a surface of a wafer includes an anode, a shaping plate, a liquid electrolyte contained between the anode and the surface of the wafer, and electrical contact members contacting selected locations on the surface of the wafer. The shaping plate defines a recessed edge and is supported between the anode and the surface of the wafer such that an upper surface of the shaping plate faces the surface of the substrate. The shaping plate can have a plurality of channels such that each puts the surface of the wafer in a fluid communication with the anode. The deposition process progresses through the shaping plate. The upper surface of the shaping plate has a substantially larger area than the area of the surface of the wafer.
    Type: Application
    Filed: January 17, 2001
    Publication date: May 9, 2002
    Inventors: Bulent M. Basol, Cyprian Uzoh, Homayoun Talieh
  • Patent number: 6383357
    Abstract: A three-dimensional formed metallic structure with varying thickness including sloping flanks is formed on a substrate. A conductive layer is applied to the substrate initially, in the form of laterally spaced electrically isolated conductive islands. A cathodic potential is connected to at least one of the islands, leaving others unconnected, and deposition proceeds due to the cathodic potential. As metallic material is deposited and builds up, it eventually contacts adjacent islands, thereby coupling the cathodic potential to a wider area where deposition commences. Deposition is thickest at the at least one island initially coupled to the cathodic potential and thinner progressing away, forming flanks that are linearly sloped, curved or similarly formed by thickness variations the vary proceeding away from the initially coupled island or islands.
    Type: Grant
    Filed: December 29, 1998
    Date of Patent: May 7, 2002
    Assignee: Fraunhofer-Gesellschaft zur Forderung der Angewandten Forschung, E.V.
    Inventor: Andreas Maciossek
  • Publication number: 20020050458
    Abstract: To provide a method capable of producing a separator integrated with a gas flow channel of fuel cells efficiently at low costs without deteriorating processing accuracy and the like.
    Type: Application
    Filed: June 28, 2001
    Publication date: May 2, 2002
    Inventors: Masanori Matsukawa, Ryuta Kimata, Youhei Kuwabara, Kenji Dewaki, Shinji Dewaki
  • Publication number: 20020050459
    Abstract: An electronic device manufacturing method comprises forming an insulating film above a substrate, forming a to-be-filled region which includes at least one of an interconnection groove and a hole in the insulating film, forming a first conductive film containing a catalyst metal which accelerates electroless plating, so as to line an internal surface of the to-be-filled region, forming a second conductive film on the first conductive film by the electroless plating, so as to line the internal surface of the to-be-filled region via the first conductive film, and forming a third conductive film on the second conductive film by electroplating, so as to fill the to-be-filled region via the first conductive film and the second conductive film.
    Type: Application
    Filed: November 1, 2001
    Publication date: May 2, 2002
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tetsuo Matsuda, Hiroshi Toyoda, Hisashi Kaneko
  • Patent number: 6375823
    Abstract: A cathode potential is applied to a conductive layer formed on a substrate having a depression pattern. A plating solution in electrical contact with an anode is supplied to the conductive layer to form a plating film on the conductive layer. At this time, the plating solution is supplied by causing an impregnated member containing the plating solution to face the conductive layer. Since the plating solution stays in the depression, a larger amount of plating solution is supplied than on the upper surface of the substrate, and the plating rate of the plating film in the depression increases. Consequently, the plating film can be preferentially formed in the depression such as a groove or hole.
    Type: Grant
    Filed: February 9, 2000
    Date of Patent: April 23, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuo Matsuda, Hisashi Kaneko, Katsuya Okumura
  • Patent number: 6372114
    Abstract: A method of forming a multi-layer structure over an insulating layer comprises the steps of: selectively depositing a barrier layer on a predetermined region of an insulating layer by use of a first deposition mask; selectively depositing a metal seed layer made of a metal which is different in substance from the barrier layer by use of a second deposition mask, so that the metal seed layer extends not only on an entire surface of the barrier layer but also a peripheral region positioned outside the predetermined region of the insulating layer; and forming a metal plating layer made of the metal of the metal seed layer, so that the metal plating layer is adhered on the metal seed layer whereby the metal plating layer is separated from the barrier layer and also from the insulating layer.
    Type: Grant
    Filed: April 8, 1999
    Date of Patent: April 16, 2002
    Assignee: NEC Corporation
    Inventor: Nobukazu Ito
  • Patent number: 6372110
    Abstract: The electrochemical processing of a component such as an injection nozzle, must be calibrated in order to compare the throughput of the nozzle to a standard nozzle. Both throughput rates are determine at the same high pressure which is far above 100 bar. As a throughput medium, electrolyte is used in an ecm unit. From this a sufficient quantity is delivered into a temporarily pressure chamber in which another fluid has been supplied by a high pressure pump. A predetermined high pressure is built up which by way of a highly accurate control valve is maintained during the calibration procedure.
    Type: Grant
    Filed: March 23, 2000
    Date of Patent: April 16, 2002
    Inventor: Fritz-Herbert Frembgen
  • Patent number: 6368482
    Abstract: A system and a method for selective plating processes are disclosed which use directed beams of high intensity acoustic waves to create non-linear effects that alter and improve the plating process. The directed beams are focused on the surface of an object, which in one embodiment is immersed in a plating solution, and in another embodiment is suspended above a plating solution. The plating processes provide precise control of the thickness of the layers of the plating, while at the same time, in at least some incidents, eliminates the need for masking.
    Type: Grant
    Filed: September 19, 2000
    Date of Patent: April 9, 2002
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration, Washington, DC (US)
    Inventors: Richard C. Oeftering, Charles Denofrio
  • Patent number: 6368467
    Abstract: An electrolytic process for metal-coating the surface of a workpiece of an electrically conductive material includes i) providing an electrolytic cell with a cathode defining the surface of the workpiece and an anode; ii) introducing an electrolyte of an aqueous solution containing one or more water soluble compounds of the metal or metals to be deposited into the zone created between the anode and the cathode in a manner such that the cathode is bathed but not immersed in the electrolyte; and iii) applying a voltage between the anode and the cathode such that an electrical plasma arc is maintained between the anode and cathode during the deposition of the metal-coating onto the surface of the cathode.
    Type: Grant
    Filed: September 12, 2000
    Date of Patent: April 9, 2002
    Assignee: Metal Technology, Inc.
    Inventors: Edgar Harold Andrews, Valerij Leontievich Steblianko, Vitalij Makarovich Riabkov
  • Publication number: 20020038764
    Abstract: A continuous layer of a metal is electrodeposited onto a substrate having both hydrodynamically inaccessible recesses and hydrodynamically accessible recesses on its surface by a twostep process in which the hydrodynamically inaccessible recesses are plated using a pulsed reversing current with cathodic pulses having a duty cycle of less than about 50% and anodic pulses having a duty cycle of greater than about 50% and the hydrodynamically accessible recesses are then plated using a pulsed reversing current with cathodic pulses having a duty cycle of greater than about 50% and anodic pulses having a duty cycle of less than about 50%.
    Type: Application
    Filed: April 3, 2001
    Publication date: April 4, 2002
    Inventors: E. Jennings Taylor, Jenny J. Sun, Maria E. Inman
  • Patent number: 6365029
    Abstract: A thin film magnetic head comprising a lower magnetic core, an upper magnetic core, and a thin film copper coil wound between magnetic poles of the lower and upper magnetic cores, the time constant of which can be reduced by reducing the specific resistance of the thin film coil and reducing insulating resin layers between the thin film coil conductors and between the coil layers, thereby allowing writing information at higher frequencies. The average crystal grain size of the thin film copper coil is made to be not more than 0.5 &mgr;m. More preferably, the average crystal grain size should be not more than 0.2 &mgr;m. In the thin film magnetic head, the surface roughness of the thin film copper coil can be reduced to not more than 15 nm.
    Type: Grant
    Filed: May 11, 1999
    Date of Patent: April 2, 2002
    Assignee: Hitachi Metals, Ltd.
    Inventors: Kiyoharu Fujita, Shinji Furuichi, Takeo Sasaki
  • Publication number: 20020033341
    Abstract: A smooth layer of a metal is electroplated onto a microrough electrically conducting substrate by immersing the substrate and a counterelectrode in an electroplating bath of the metal to be electroplated and passing a modulated reversing electric current between the electrodes. The current contains pulses that are cathodic with respect to said substrate and pulses that are anodic with respect to said substrate. The cathodic pulses have a duty cycle less than about 50% and said anodic pulses have a duty cycle greater than about 50%, the charge transfer ratio of the cathodic pulses to the anodic pulses is greater than one, and the frequency of said pulses ranges from about 10 Hertz to about 12000 Hertz. The plating bath is substantially devoid of levelers and may be devoid of brighteners.
    Type: Application
    Filed: April 3, 2001
    Publication date: March 21, 2002
    Inventors: E. Jennings Taylor, Chengdong Zhou, Jenny J. Sun
  • Publication number: 20020033342
    Abstract: The present invention relates to a method for fabricating high performance chip interconnects and packages by providing methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. This is accomplished by selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses methods for forming multi-level interconnects and the corresponding structures.
    Type: Application
    Filed: July 13, 2001
    Publication date: March 21, 2002
    Inventors: Cyprian Emeka Uzoh, Homayoun Talieh, Bulent Basol
  • Patent number: 6358388
    Abstract: A semiconductor workpiece holder used in electroplating systems for plating metal layers onto a semiconductor workpieces, and is of particular advantage in connection with plating copper onto semiconductor materials. The workpiece holder includes electrode assemblies which have a contact part which connects to a distal end of an electrode shaft and bears against the workpiece and conducts current therebetween. The contact part is preferably made from a corrosion resistant material, such as platinum. The electrode assembly also preferably includes a dielectric layer which covers the distal end of the electrode shaft and seals against the contact part to prevent plating liquid from corroding the joint between these parts.
    Type: Grant
    Filed: November 16, 1999
    Date of Patent: March 19, 2002
    Assignee: Semitool, Inc.
    Inventors: Martin C. Bleck, Lyndon W. Graham, Kyle M. Hanson
  • Patent number: 6350364
    Abstract: A method for electroplating copper in trenches, including the steps of providing a semiconductor substrate having a trench formed therein and electrolytically depositing a first copper containing layer having an upper surface and a predetermined thickness within the trench. The first copper deposition step has a first ratio of brighteners concentration:levelers concentration. Then a second copper containing layer having an upper surface and a predetermined thickness is electrolytically deposited over the first copper containing layer. The second copper deposition step has a second ratio of brighteners concentration:levelers concentration that is less than the said first ratio of brighteners concentration:levelers concentration. The second copper containing layer upper surface having a greater planarity than the first copper containing layer upper surface due to an increased concentration of levelers relative to the brighteners in the electrolytic bath.
    Type: Grant
    Filed: February 18, 2000
    Date of Patent: February 26, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Syun-Ming Jang
  • Patent number: 6344125
    Abstract: A process for the electrolytic deposition of a metal, preferably copper or an alloy of copper, directly onto a barrier layer coated on a dielectric layer. The process is advantageous because it electrolytically deposits metal in a pattern that is either the duplicate of a first conductive pattern under the dielectric or the inverse image of the first conductive pattern, depending on the first conductive pattern shape. Thus, metal is deposited on the barrier layer duplicating a first conductive pattern under the dielectric layer when the first pattern is a serpentine pattern and the metal deposits in the spaces between the conductive lines of a first conductive pattern of a discrete passive element such as a spiral.
    Type: Grant
    Filed: April 6, 2000
    Date of Patent: February 5, 2002
    Assignee: International Business Machines Corporation
    Inventors: Peter S. Locke, Kevin S. Petrarca, Seshadri Subbanna, Richard P. Volant
  • Publication number: 20020011416
    Abstract: The present invention provides plating solutions, particularly copper plating solutions, designed to provide uniform coatings on substrates and to provide substantially defect free filling of small features formed on substrates with none or low supporting electrolyte, i.e., which include no acid, low acid, no base, or no conducting salts, and/or high metal ion, e.g., copper, concentration. Defect free filling of features is enhanced by a plating solution containing blends of polyethers (“carrier”) and organic divalent sulfur compounds (“accelerator”), wherein the concentration of the carrier ranges from about 0.1 ppm to about 2500 ppm of the plating solution, and the concentration of the accelerator ranges from about 0.05 ppm to about 1000 ppm of the plating solution. The plating solution is further improved by adding an organic nitrogen compound at a concentration from about 0.01 ppm to about 1000 ppm to improve the filling of vias on a resistive substrate.
    Type: Application
    Filed: August 24, 2001
    Publication date: January 31, 2002
    Applicant: Applied Materials, Inc.
    Inventors: Uziel Landau, John J. D'Urso
  • Publication number: 20020008036
    Abstract: An apparatus for plating a conductive film directly on a substrate with a barrier layer on top includes anode rod (1) placed in tube (109), and anode rings (2), and (3) placed between cylindrical walls (107) and (105), (103) and (101), respectively. Anodes (1), (2), and (3) are powered by power supplies (13), (12), and (11), respectively. Electrolyte (34) is pumped by pump (33) to pass through filter (32) and reach inlets of liquid mass flow controllers (LMFCs) (21), (22), and (23). Then LMFCs (21), (22) and (23) deliver electrolyte at a set flow rate to sub-plating baths containing anodes (3), (2) and (1), respectively. After flowing through the gap between wafer (31) and the top of the cylindrical walls (101), (103), (105), (107) and (109), electrolyte flows back to tank (36) through spaces between cylindrical walls (100) and (101), (103) and (105), and (107) and (109), respectively.
    Type: Application
    Filed: April 18, 2001
    Publication date: January 24, 2002
    Inventor: Hui Wang
  • Publication number: 20020003092
    Abstract: A process for the production of refractory metal plates platinized on one side, in which refractory metal plates of predetermined dimensions are tightly, form-fittingly joined together back to back, are coated with platinum on their exposed surfaces by melt electrolysis and the plates are then separated one from the other. These plates may be processed into expanded metal grids platinized on one side. These refractory metal plates platinized on one side and the expanded metal grids platinized on one side produced therefrom may be used highly advantageously as anodes in electrolytic and electroplating processes.
    Type: Application
    Filed: June 12, 2001
    Publication date: January 10, 2002
    Inventors: Thomas Engert, Gerhard Steinhilber
  • Publication number: 20010045361
    Abstract: The parts are produced by two-component injection molding. Those regions that are to be metallized consist of a first plastic and those regions that are not to be metallized consist of a second plastic. After the entire surface of the parts has been seeded, the seeding is selectively removed with the aid of a solvent in the regions which are not to be metallized. The first plastic is insoluble and the second plastic soluble in the solvent. The selective metallization then takes place by electroless metal deposition and, if appropriate, electrodeposition of metal.
    Type: Application
    Filed: April 16, 2001
    Publication date: November 29, 2001
    Inventor: Luc Boone
  • Publication number: 20010042690
    Abstract: The present invention deposits a conductive material from an electrolyte solution to a predetermined area of a wafer. The steps that are used when making this application include applying the conductive material to the predetermined area of the wafer using an electrolyte solution disposed on a surface of the wafer, when the wafer is disposed between a cathode and an anode, and preventing accumulation of the conductive material to areas other than the predetermined area by mechanically polishing the other areas while the conductive material is being applied.
    Type: Application
    Filed: December 14, 2000
    Publication date: November 22, 2001
    Applicant: NuTool, Inc.
    Inventor: Homayoun Talieh
  • Publication number: 20010042689
    Abstract: This invention employs a novel approach to the copper metallization of a workpiece, such as a semiconductor workpiece. In accordance with the invention, an alkaline electrolytic copper bath is used to electroplate copper onto a seed layer, electroplate copper directly onto a barrier layer material, or enhance an ultra-thin copper seed layer which has been deposited on the barrier layer using a deposition process such as PVD. The resulting copper layer provides an excellent conformal copper coating that fills trenches, vias, and other microstructures in the workpiece. When used for seed layer enhancement, the resulting copper seed layer provide an excellent conformal copper coating that allows the microstructures to be filled with a copper layer having good uniformity using electrochemical deposition techniques. Further, copper layers that are electroplated in the disclosed manner exhibit low sheet resistance and are readily annealed at low temperatures.
    Type: Application
    Filed: June 20, 2001
    Publication date: November 22, 2001
    Applicant: Semitool, Inc.
    Inventor: Linlin Chen
  • Publication number: 20010040100
    Abstract: An apparatus for plating a conductive film directly on a substrate with a barrier layer on top includes anode rod (1) placed in tube (109), and anode rings (2), and (3) placed between cylindrical walls (107) and (105), (103) and (101), respectively. Anodes (1), (2), and (3) are powered by power supplies (13), (12), and (11), respectively. Electrolyte (34) is pumped by pump (33) to pass through filter (32) and reach inlets of liquid mass flow controllers (LMFCs) (21), (22), and (23). Then LMFCs (21), (22) and (23) deliver electrolyte at a set flow rate to sub-plating baths containing anodes (3), (2) and (1), respectively. After flowing through the gap between wafer (31) and the top of the cylindrical walls (101), (103), (105), (107) and (109), electrolyte flows back to tank (36) through spaces between cylindrical walls (100) and (101), (103) and (105), and (107) and (109), respectively.
    Type: Application
    Filed: April 16, 2001
    Publication date: November 15, 2001
    Inventor: Hui Wang
  • Publication number: 20010040264
    Abstract: A method of forming a multi-layer structure over an insulating layer comprises the steps of: selectively depositing a barrier layer on a predetermined region of an insulating layer by use of a first deposition mask; selectively depositing a metal seed layer made of a metal which is different in substance from the barrier layer by use of a second deposition mask, so that the metal seed layer extends not only on an entire surface of the barrier layer but also a peripheral region positioned outside the predetermined region of the insulating layer; and forming a metal plating layer made of the metal as the seed layer, so that the metal layer is adhered on the metal seed layer whereby the metal plating layer is separated from the barrier layer and also from the insulating layer.
    Type: Application
    Filed: July 31, 2001
    Publication date: November 15, 2001
    Inventor: Nobukazu Ito
  • Publication number: 20010037943
    Abstract: A contact is disposed to come into contact with a metal layer formed on a substrate being treated, the contact being in contact with a surface being treated from an opposite surface through a through hole present in a substrate. Alternatively, a contact is disposed to come into contact with a metal layer formed on a substrate, the contact coming into contact at an approximate center of the substrate. Alternatively, a plurality of needle bodies are disposed to be in electrical contact with a metal layer of a substrate being treated, thereby power supply for electrolytic polishing/plating to a substrate being treated being implemented, without restricting to a periphery of a substrate, from a plurality of points on a surface thereof. Due to any one of these, liquid treatment equipment enables to improve uniformity in plane of an electric current sent to a surface being treated and of liquid treatment.
    Type: Application
    Filed: May 7, 2001
    Publication date: November 8, 2001
    Inventors: Kyungho Park, Katsusuke Shimizu, Wataru Okase, Takenobu Matsuo