Coating Selected Area Patents (Class 205/118)
  • Publication number: 20100059365
    Abstract: A process for manufacturing a mask having submillimetric openings on a surface portion of a substrate, characterized in that: a layer known as a mask layer is deposited from a solution of colloidal particles that are stabilized and dispersed in a solvent; and the drying of the mask layer is carried out until a two-dimensional irregular network of substantially straight-edged interstices that gives a mask is obtained, with a random mesh of interstices in at least one direction. Submillimetric grid obtained by the process.
    Type: Application
    Filed: March 21, 2008
    Publication date: March 11, 2010
    Applicant: SAINT-GOBAIN GLASS FRANCE
    Inventors: Emmanuel Valentin, Bernard Nghiem, Arnaud Huignard, Georges Zagdoun, Eddy Royer
  • Patent number: 7674361
    Abstract: Multi-layer fabrication methods (e.g. electrochemical fabrication methods) for forming microscale and mesoscale devices or structures (e.g. turbines) provide bushings or roller bearing that allow rotational or linear motion which is constrained by multiple structural elements spaced from one another by gaps that are effectively less than minimum features sizes associated with the individual layers used to form the structures. In some embodiments, features or protrusions formed on different layers on opposing surfaces are offset along the axis of layer stacking so as to bring the features into positions that are closer than allowed by the minimum features sizes associated with individual layers. In other embodiments, interference is used to create effective spacings that are less than the minimum features sizes.
    Type: Grant
    Filed: May 26, 2006
    Date of Patent: March 9, 2010
    Assignee: Microfabrica Inc.
    Inventor: Adam L. Cohen
  • Publication number: 20100051467
    Abstract: A process for surface treating aluminum and aluminum alloy articles is provided. The method includes the steps of providing a substrate of aluminum or aluminum alloy material, the substrate having an internal surface and an external surface; machining the external surface of substrate, thereby forming a first surface appearance on the external surface; forming a first oxide coating with a first color on the substrate surface by a first anodizing process; removing at least a portion of the first oxide coating on the internal surface of the substrate to make the substrate electricity conductive; machining the external surface of the substrate, thereby removing at least a portion of the first oxide coating on the external surface and forming a second surface appearance thereon; forming a second oxide coating with a second color on the area of the external surface excluding the first oxide coating by a second anodizing process.
    Type: Application
    Filed: August 3, 2009
    Publication date: March 4, 2010
    Applicants: SHENZHEN FUTAIHONG PRECISION INDUSTRY CO., LTD., FIH (Hong Kong) Limited
    Inventors: MIN TIAN, NAI-JUAN REN
  • Patent number: 7666291
    Abstract: A method for fabricating metal wires is disclosed. A substrate is first provided, and a first metal layer is formed over the surface of the substrate. Next, a mask with patterns is formed on the surface of the substrate, in which the first metal layer is partially exposed. Next, an electroplating process is performed to form a second metal layer on top of the partially exposed first metal layer. Next, the mask with patterns is removed and an etching process is performed to remove part of the first metal layer by utilizing the second metal layer as a mask for forming a metal wire.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: February 23, 2010
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventor: Kang-Chia Peng
  • Publication number: 20100038253
    Abstract: Some embodiments of the present invention provide processes and apparatus for electrochemically fabricating multilayer structures (e.g. mesoscale or microscale structures) with improved endpoint detection and parallelism maintenance for materials (e.g. layers) that are planarized during the electrochemical fabrication process. Some methods involve the use of a fixture during planarization that ensures that planarized planes of material are parallel to other deposited planes within a given tolerance. Some methods involve the use of an endpoint detection fixture that ensures precise heights of deposited materials relative to an initial surface of a substrate, relative to a first deposited layer, or relative to some other layer formed during the fabrication process. In some embodiments planarization may occur via lapping while other embodiments may use a diamond fly cutting machine.
    Type: Application
    Filed: September 15, 2009
    Publication date: February 18, 2010
    Inventors: Uri Frodis, Adam L. Cohen, Michael S. Lockard
  • Publication number: 20100032301
    Abstract: An aluminum alloy member includes a main body including an aluminum alloy serving as a base material, and an electrolytic oxidation ceramic coating coated at a portion of a surface of the main body and including a most outer layer and an inner layer which is arranged close to the main body relative to the most outer layer, the inner layer in which an aluminum oxide is richer than the most outer layer, the most outer layer in which a volume of a titanium oxide or a total volume of the titanium oxide and a zirconium oxide is richer than the inner surface.
    Type: Application
    Filed: August 6, 2009
    Publication date: February 11, 2010
    Applicants: Nihon Parkerizing Co., Ltd., AISIN SEIKI KABUSHIKI KAISHA
    Inventors: Ichiro Hiratsuka, Mie Tokuhara, Tomoyoshi Konishi, Arata Suda
  • Patent number: 7658831
    Abstract: Systems and methods for depositing a plurality of droplets in a three-dimensional array are disclosed. The array can comprise a first type of droplets disposed to form a support structure and a second type of droplets forming a conductive seed layer on the support structure. A structure material can be electrodeposited onto the seed layer to create a three-dimensional structure.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: February 9, 2010
    Assignee: FormFactor, Inc
    Inventors: Gaetan L. Mathieu, Treliant Fang, Eric D. Hobbs
  • Patent number: 7655126
    Abstract: A method for making a gasket (32) for an internal combustion engine (20) includes forming a generally annual stopper (38) on a metallic gasket body (40) through the process of electrochemical deposition. An electrolytic cell is completed with the gasket body (40) forming a cathode. The stopper (38) is formed with a contoured compression surface (42) by selectively varying the electrical energy delivered to selected electrodes (70) over time. Electrolyte (48) rich with metallic ions is pumped at high speed through the inter-electrode gap. A PC controller (82) switches selected electrodes (70) ON at certain times, for certain durations, which cause metallic ions in the electrolyte (48) to reduce or deposit onto the gasket body (40), which are built in columns or layers into a three-dimensional formation approximating the target surface profile (106) for the compression surface (42). The subject method for building a three-dimensional formation can be applied to work parts other than cylinder head gaskets (32).
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: February 2, 2010
    Assignee: Federal Mogul World Wide, Inc.
    Inventor: Yuefeng Luo
  • Publication number: 20100021695
    Abstract: An engraved plate which includes a substrate and an insulating layer on a surface of the substrate wherein a concave portion which increases in width toward an opening and to which the substrate is exposed is formed at the insulating layer, and an engraved plate, a substrate with conductor layer pattern manufactured by a transferring method using the engraved plate, and a conductor layer pattern are provided.
    Type: Application
    Filed: December 27, 2007
    Publication date: January 28, 2010
    Inventors: Susumu Naoyuki, Hisashige Kanbara, Minoru Tosaka, Kyosuke Suzuki, Toshirou Okamura, Yoshihito Kikuhara, Masami Negishi, Tadayasu Fujieda, Kouichi Tsuyama
  • Patent number: 7647697
    Abstract: The method manufactures a nozzle plate, and comprises: a patterned resist formation step of forming a patterned resist on a flat surface of a matrix substrate, the patterned resist having a shape corresponding to a diameter of nozzle holes in a nozzle plate to be formed, the patterned resist having a thickness corresponding to a length of the nozzle holes; a nozzle length regulating member placement step of placing the nozzle length regulating member having a flat surface onto the patterned resist in such a manner that the flat surface of the nozzle length regulating member faces the flat surface of the matrix substrate across the patterned resist; and a nozzle plate formation step of forming the nozzle plate by plating with the patterned resist between the flat surface of the matrix substrate and the flat surface of the nozzle length regulating member.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: January 19, 2010
    Assignee: Fujifilm Corporation
    Inventor: Tsutomu Yokouchi
  • Publication number: 20100006443
    Abstract: Embodiments of the invention are directed to the formation of beam-like structures using electrochemical fabrication techniques where the beam like structures have narrow regions and wider regions such that a beam of desired compliance is obtained. In some embodiments, narrower regions of the beam are thinner than a minimum feature size but are formable as a result of the thicker regions. In some embodiments the beam-like structures are formed from a plurality of adhered layers.
    Type: Application
    Filed: July 16, 2009
    Publication date: January 14, 2010
    Applicant: Microfabrica Inc.
    Inventors: Adam L. Cohen, Michael S. Lockard, Christopher A. Bang, Marvin M. Kilgo, III
  • Publication number: 20090321052
    Abstract: The present invention provides a water-cooled heat sink having an integrated structure, and having inside a precise, freely formed flow path, the water-cooled heat sink being produced without using a technique for pasting a plurality of metal sheets. In a water-cooled heat sink 1, a formed body 2 is provided outwardly, a flow path 3 for passage of a liquid is formed inwardly of the formed body 2, and an inlet 5 and an outlet 4 for the liquid, which communicate with the flow path 3, are formed in the main body of the heat sink 1. The entire formed body 2 of the heat sink 1 is integrally formed by thick coating layers applied by electroplating, and has no joints.
    Type: Application
    Filed: November 17, 2006
    Publication date: December 31, 2009
    Inventors: Houkichi Yoshioka, Takahisa Yoshimura, Tohru Natsume
  • Publication number: 20090316335
    Abstract: The invention relates to a self-supporting composite element and to a method of producing same. The composite element comprises a substrate of electronic conductive material which is covered with metal nanowires that are essentially oriented along a plane that is perpendicular to the substrate. The element is produced in a cell comprising a cathode which is formed by the substrate to be covered, one or more anodes and an electrolyte which is formed by a solution of a precursor of the metal material and optionally containing a conductive ionic salt, a flat porous membrane which is placed between the cathode and each of the anodes and a spacer element between each membrane and the anode adjacent thereto, the different constituent parts of the cell being maintained in contact.
    Type: Application
    Filed: May 5, 2006
    Publication date: December 24, 2009
    Inventors: Patrice Simon, Pierre-Louis Taberna, Jean-Pascal Cambronne, Thierry Lebey
  • Publication number: 20090311542
    Abstract: A metal shell with printing patterns has a metal body, a printing layer and an electroplating layer. The metal body has an outer surface and an area. The printing layer is attached to the outer surface of the metal body to form the printing patterns and has an area smaller than that of the metal body. The electroplating layer is attached to the outer surface of the metal body at a region beside the printing layer.
    Type: Application
    Filed: June 17, 2008
    Publication date: December 17, 2009
    Inventors: Da-Sen Lin, Chien-Liang Lin
  • Publication number: 20090308754
    Abstract: The present invention provides a method of fabricating a micro hollow tube, more specifically, a method of fabricating a micro hollow tube by template-free localized electrochemical deposition, in which the micro hollow tube is fabricated by the accurate control of the distribution of the electric field strength during deposition with precise interplay of the applied voltage and the distance between the microelectrode and the grown structure.
    Type: Application
    Filed: July 17, 2009
    Publication date: December 17, 2009
    Inventors: Seung Kwon Seol, Jung Ho Je, Yeu Kuang Hwu
  • Publication number: 20090301892
    Abstract: A process and apparatus utilizing at least one conformable anode (40) in a plating process to apply a plating to an article (10). A wire or other material suitable for an anode is shaped to conform to the approximate shape of a region of the article to be coated. The anode is powered by an electrical power source (44), and the article serves as the cathode. The anode and article are both immersed in a plating bath (38). The article and anode are rotated relative to one another about a central axis (22) of the article. The relative movement between the anode and the article causes a uniform plating (46) to be applied to selected regions of the article that pass the anode. Another anode (50) can be arranged in fixed relation with the article to cause plating to a separate selected region of the article concurrently with the other anode.
    Type: Application
    Filed: July 26, 2006
    Publication date: December 10, 2009
    Inventors: James R. Toth, Miguel Azevedo
  • Patent number: 7627946
    Abstract: This invention discloses a method for electroplating nickel/gold on electrically connecting pads on a substrate for chip package and structure thereof. The method comprises: forming a conductive film on a substrate circuit-patterned and defined with a circuit layer; forming on the substrate a resist with an opening for exposing a portion of the conductive film in an electrically connecting pad area intended for the circuit layer; removing a portion of the conductive film not covered with the resist; forming another resist on the substrate to cover a portion of the conductive film residually exposing from the resist; electroplating nickel/gold on at least one electrically connecting pad on the substrate such that the electrically connecting pad is electroplated with a nickel/gold layer; removing the resists and the conductive film thereunder; and forming a solder mask on the substrate, wherein the electrically connecting pad electroplated with the nickel/gold layer is exposed from the solder mask.
    Type: Grant
    Filed: March 19, 2007
    Date of Patent: December 8, 2009
    Assignee: Phoenix Precision Technology Corporation
    Inventor: Pao-Hung Chou
  • Publication number: 20090294292
    Abstract: A method of surface printing and electric plating, it is to perform pre-plating to form a pre-plated layer firstly on a surface of a metallic or non-metallic article to be plated, thereby the metallic or non-metallic surface will not be oxidized, and to perform printing and then electric plating to make the plated layer higher than the electric printed layer, thus an effect of 3 dimensions can be resulted; and the printing oil ink is protected in the plated layer, thereby it is not subjected to being stripped off by abrasion.
    Type: Application
    Filed: June 2, 2008
    Publication date: December 3, 2009
    Inventor: Yu-Hwei HUANG
  • Patent number: 7618525
    Abstract: An electroplating method that includes: a) contacting a first substrate with a first article, which includes a substrate and a conformable mask disposed in a pattern on the substrate; b) electroplating a first metal from a source of metal ions onto the first substrate in a first pattern, the first pattern corresponding to the complement of the conformable mask pattern; and c) removing the first article from the first substrate, is disclosed. Electroplating articles and electroplating apparatus are also disclosed.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: November 17, 2009
    Assignee: University of Southern California
    Inventor: Adam L. Cohen
  • Publication number: 20090277672
    Abstract: The present invention provides a method for forming a metal pattern comprising a step of forming a polymer layer on a substrate; (a2) a step of applying a metal ion or the like to the polymer layer; (a3) a step of forming a conductive layer by reducing the metal ion or the like; (a4) a step of forming a patterned resist layer on the conductive layer; (a5) a step of forming a metal pattern by electroplating in the regions where the resist layer is not formed; (a6) a step of separating the resist layer; (a7) a step of removing the conductive layer from regions protected by the resist layer; and (a8) a step of performing a hydrophobilizing treatment.
    Type: Application
    Filed: April 10, 2007
    Publication date: November 12, 2009
    Applicant: FUJIFILM Corporation
    Inventor: Kazuhiko Matsumoto
  • Patent number: 7615141
    Abstract: An electrochemical printing system (100, 200) and method are disclosed having a printer head (130, 230) that expels a small jet of electrolyte (112) towards a conductive substrate (92) to facilitate electrodeposition or removal of material from the substrate. In an embodiment of the invention the printer head includes a plurality of individually addressable electrodes (220), each electrode having a channel therethrough and wherein the electrodes are much larger than the electrolyte jet outlet. The printer head includes means for inhibiting cross talk between electrodes. For example, the printer head may include a plenum (241) and a nonconductive cross-talk inhibition layer (245) upstream of the electrodes. A resolution defining layer (270) having small apertures (271) is provided at the distal end of the printer head.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: November 10, 2009
    Assignee: University of Washington
    Inventors: Daniel T. Schwartz, John D. Whitaker
  • Patent number: 7611616
    Abstract: Various embodiments of the invention are directed to formation of mesoscale or microscale devices using electrochemical fabrication techniques where structures are formed from a plurality of layers as opened structures which can be folded over or other otherwise combined to form structures of desired configuration. Each layer is formed from at least one structural material and at least one sacrificial material. The initial formation of open structures may facilitate release of the sacrificial material, ability to form fewer layers to complete a structure, ability to locate additional materials into the structure, ability to perform additional processing operations on regions exposed while the structure is open, and/or the ability to form completely encapsulated and possibly hollow structures.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: November 3, 2009
    Assignee: Microfabrica Inc.
    Inventors: Adam L. Cohen, Michael S. Lockard, Dennis R. Smalley
  • Publication number: 20090260992
    Abstract: A multi-layered wafer support apparatus is provided for performing an electroplating process on a semiconductor wafer (“wafer”). The multi-layered wafer support apparatus includes a bottom film layer and a top film layer. The bottom film layer includes a wafer placement area and a sacrificial anode surrounding the wafer placement area. The top film layer is defined to be placed over the bottom film layer. The top film layer includes an open region to be positioned over a surface of the wafer to be processed, i.e., electroplated. The top film layer provides a liquid seal between the top film layer and the wafer, about a periphery of the open region. The top film layer further includes first and second electrical circuits that are each defined to electrically contact a peripheral top surface of the wafer at diametrically opposed locations about the wafer.
    Type: Application
    Filed: June 23, 2009
    Publication date: October 22, 2009
    Applicant: Lam Research Corporation
    Inventor: Carl Woods
  • Publication number: 20090258188
    Abstract: Disclosed herein is a composition for forming an inorganic pattern, comprising an inorganic precursor, at least one stabilizer selected from ?-diketone and ?-ketoester, and a solvent. Use of the composition enables efficient and inexpensive formation of an inorganic micropattern.
    Type: Application
    Filed: August 28, 2008
    Publication date: October 15, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Nam CHA, Dae Joon KANG, Byong Gwon SONG
  • Publication number: 20090242410
    Abstract: A method for the electrochemical plating or marking of metals includes providing a metal surface, providing an electroplating solution at the metal surface, and electroplating the metal surface with the electroplating solution. A top layer of the metal surface comprises an oxide scale. The method can also include masking a portion of the metal surface with a masking material. The electroplating solution can be provided at the metal surface by an electroplating brush, the oxide scale of the metal surface can be comprised primarily of magnetite and hematite, and the material comprising the metal surface can be steel.
    Type: Application
    Filed: March 28, 2008
    Publication date: October 1, 2009
    Applicant: TENARIS CONNECTIONS AG (LIECHTENSTEIN CORPORATION)
    Inventors: Pablo Adrian CASTRO, Federico Jose WILLIAMS
  • Publication number: 20090229857
    Abstract: An electrode for forming an electrochemical cell with a substrate and a method of forming said electrode. The electrode comprises a carrier (1) provided with an insulating layer (7) which is patterned at a front side. Conducting material in an electrode layer (4) is applied in the cavities of the patterned insulating layer and in contact with the carrier. An connection layer (5) is applied at the backside of the carrier and in contact with the carrier. The periphery of the electrode is covered by the insulating material.
    Type: Application
    Filed: May 21, 2009
    Publication date: September 17, 2009
    Inventors: Mikael FREDENBERG, Patrik Moller, Peter Wiwen-Nilsson, Cecillia Aronsson, Matteo Dainese
  • Patent number: 7585424
    Abstract: This invention provides a pattern reversal process for self aligned imprint lithography (SAIL). The method includes providing a substrate and depositing at least one layer of material upon the substrate. A pattern is then established upon the layer of material, the pattern providing at least one exposed area and at least one covered area of the layer of material. The exposed areas are treated to toughen the material and reverse the pattern. Subsequent etching removes the un-toughened material. A thin-film transistor device provided by the pattern reversal process is also provided.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: September 8, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Ping Mei
  • Publication number: 20090211690
    Abstract: A method for making a microstructure includes: providing a film (100) on a release liner (110); feeding the film through a cutting plotter (10); cutting the film with a knife blade (34) of the cutting plotter to form a microstructure pattern; peeling the microstructure pattern from the release liner; and transferring the microstructure pattern to a substrate (170). The cutting plotter for making microstructures includes a knife head with a knife blade disposed adjacent a feed mechanism (20), a motor (42) and control system coupled to the knife head for selectively moving the knife head in relation to the film, and the control system and the knife head having an addressable positioning resolution less than approximately 10 ?m.
    Type: Application
    Filed: April 7, 2006
    Publication date: August 27, 2009
    Inventors: Daniel A. Bartholomeusz, Ameya Kantak, Sung Lee, Merugu Srinivas, Himanshu Sant, Ronald W. Boutte, Bruce Gale, Charles Thomas
  • Publication number: 20090205967
    Abstract: Method of forming a multilayer structure by electroetching or electroplating on a substrate. A seed layer is arranged on the substrate and a master electrode is applied thereto. The master electrode has a pattern layer forming multiple electrochemical cells with the substrate. A voltage is applied for etching the seed layer or applying a plating material to the seed layer. A dielectric material (9) is arranged between the structures (8) thus formed. The dielectric layer is planarized for uncovering the structure below and another structure layer is formed on top of the first. Alternatively, the dielectric layer is applied with a thickness two layers and the structure below is accessed by selective etching of the dielectric layer for selectively uncovering the top surface of the structure below. Multiple structure layer may also be formed in one step.
    Type: Application
    Filed: March 26, 2009
    Publication date: August 20, 2009
    Inventors: Mikael FREDENBERG, Patrik Moller, Peter Wiwen-Nilsson
  • Patent number: 7563353
    Abstract: A method of forming an Sn—Ag—Cu ternary alloy thin-film of the present invention forms the ternary alloy thin-film by electroplating. A plating bath contains an Sn compound, an Ag compound, a Cu compound, an inorganic chelating agent and an organic chelating agent. The inorganic chelating agent is one of a polymerized phosphate-based chelating agent and a chelating agent represented by a chemical formula (I): MFX(X—Y)— . . . (I) where M is an arbitrary metal, X is an arbitrary natural number and Y is an oxidation number of M. The organic chelating agent is one of porphyrins, dipivaloylmethane, phthalocyanines and a compound represented by a chemical formula (II): R—(CH2CH2O)n-A . . . (II) where R is an alkyl group having a carbon number of 8 to 30, A is CH2COONa or CH2SO4Na and n is a natural number.
    Type: Grant
    Filed: October 19, 2005
    Date of Patent: July 21, 2009
    Assignee: FCM Co., Ltd.
    Inventor: Shigeki Miura
  • Patent number: 7560015
    Abstract: Apparatus and method for electrolytic coating of a mould, the internal surfaces of which demarcate a mould cavity, with a coating material for the purpose of achieving or re-achieving intended mould cavity dimensions. The mould, as the cathode, and an anode positioned in the mould cavity and an electrolyte containing the coating material are used. The electrolyte serving as the carrier of the coating material flows through the mould cavity in a controlled manner. During the electrolytic coating, only the internal surfaces of the mould cavity come into contact with the electrolyte and the external surfaces of the s mould therefore do not have to be covered. The mechanical properties can be kept largely uniform over the entire region. The coating can be achieved more rapidly than with the conventional processes.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: July 14, 2009
    Assignee: Concast AG
    Inventor: Adrian Stilli
  • Publication number: 20090165295
    Abstract: Various embodiments are directed to the electrochemical fabrication of multilayer mesoscale or microscale structures which are formed using at least one conductive structural material, at least one conductive sacrificial material, and at least one dielectric material. In some embodiments the dielectric material is a UV-curable photopolymer. In other embodiments, electrochemically fabricated structures are formed on dielectric substrates.
    Type: Application
    Filed: September 18, 2008
    Publication date: July 2, 2009
    Inventors: Adam L. Cohen, Gang Zhang, Fan-Gang Tseng
  • Publication number: 20090145767
    Abstract: Some embodiments of the invention are directed to techniques for electrochemically fabricating multi-layer three-dimensional structures where selective patterning of at least one or more layers occurs via a mask which is formed using data representing cross-sections of the three-dimensional structure which has been modified to place it in a polygonal form which defines only regions of positive area. The regions of positive area are regions where structural material is to be located or regions where structural material is not to be located depending on whether the mask will be used, for example, in selectively depositing a structural material or a sacrificial material. The modified data may take the form of adjacent or slightly overlapped relative narrow rectangular structures where the width of the structures is related to a desired formation resolution. The spacing between centers of adjacent rectangles may be uniform or may be a variable.
    Type: Application
    Filed: September 30, 2008
    Publication date: June 11, 2009
    Inventors: Adam L. Cohen, Jeffrey A. Thompson
  • Publication number: 20090142493
    Abstract: Multi-layer microscale or mesoscale structures are fabricated with adhered layers (e.g. layers that are bonded together upon deposition of successive layers to previous layers) and are then subjected to a heat treatment operation that enhances the interlayer adhesion significantly. The heat treatment operation is believed to result in diffusion of material across the layer boundaries and associated enhancement in adhesion (i.e. diffusion bonding). Interlayer adhesion and maybe intra-layer cohesion may be enhanced by heat treating in the presence of a reducing atmosphere that may help remove weaker oxides from surfaces or even from internal portions of layers.
    Type: Application
    Filed: October 29, 2007
    Publication date: June 4, 2009
    Inventors: Gang Zhang, Adam L. Cohen
  • Publication number: 20090139869
    Abstract: Various embodiments of the invention present techniques for forming structures via a combined electrochemical fabrication process and a thermal spraying process or powder deposition processes. In a first set of embodiments, selective deposition occurs via masking processes (e.g. a contact masking process or adhered mask process) and thermal spraying or powder deposition is used in blanket deposition processes to fill in voids left by selective deposition processes. In a second set of embodiments, after selective deposition of a first material, a second material is blanket deposited to fill in the voids, the two depositions are planarized to a common level and then a portion of the first or second materials is removed (e.g. by etching) and a third material is sprayed into the voids left by the etching operation. In both embodiments the resulting depositions are planarized to a desired layer thickness in preparation for adding additional layers.
    Type: Application
    Filed: November 26, 2008
    Publication date: June 4, 2009
    Inventors: Michael S. Lockard, Adam L. Cohen, Roger W. Barton
  • Publication number: 20090139868
    Abstract: A print-patterned structure may be used as a self-aligned etch and deposition mask. A method of forming conductive lines and other similar features over a plurality of layers comprises forming a print-patterned structure over a first layer. The print-patterned structure is used as an etch mask to expose a portion of a second layer. A seed layer is formed over the exposed portion of the second layer, using the print-patterned structure as a deposition mask. Conductive lines or other features may be formed, for example, by electroplating using the seed layer as a contact pad and the print-patterned structure as deposition mask. The present invention is particularly useful in the formation of features for solar cells and the like where the print-patterned structure may be used to form high aspect ratio features.
    Type: Application
    Filed: December 3, 2007
    Publication date: June 4, 2009
    Applicant: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Eric Shrader, Scott Limb
  • Publication number: 20090136723
    Abstract: A coated plastic sheet comprises a transparent plastic sheet having a top and bottom surface, and a first film on the top surface and covering less than all of the top surface, thereby creating at least one uncovered area. At least a portion of the first film has a first metallic luster on its exposed surface. The coated plastic sheet also comprises a second film on the bottom surface. At least a portion of the second film is visible through the uncovered area of the sheet, wherein the second film presents a second metallic luster through the uncovered area.
    Type: Application
    Filed: October 24, 2008
    Publication date: May 28, 2009
    Inventors: Lihong Zhao, Wenhai Luo, Xijing Liu
  • Patent number: 7537663
    Abstract: A corrosion-inhibiting coating, process, and system that provides a tight, adherent zinc- or zinc-alloy coating that is directly deposited onto steel or cast iron surfaces for enhanced corrosion protection. A process for applying the coating is also provided. The process includes the application of two sequential aqueous baths. The first bath contains a precursor zinc compound while the second bath contains a reducing agent to deposit the zinc directly upon the steel or cast iron.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: May 26, 2009
    Assignee: University of Dayton
    Inventors: Andrew W. Phelps, Jeffrey A. Sturgill
  • Patent number: 7534337
    Abstract: A substrate before an insulation process, which is provided with a protection film to prevent a part of a surface area, which has electrical conductivity from being insulated, the substrate comprises: a base including the surface area, which has electrical conductivity; a protection film covering over the part of the surface area, which has electrical conductivity, and being formed on the base; the protection film including; a first protection layer having a circumferential partition wall and a second protection layer placed and embedded in an area, which is surrounded by the circumferential partition wall.
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: May 19, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Hironori Hasei
  • Patent number: 7531077
    Abstract: Some embodiments of the invention are directed to the electrochemical fabrication of microprobes which are formed from a core material and a material that partially coats the surface of the probe. Other embodiments are directed to the electrochemical fabrication of microprobes which are formed from a core material and a material that completely coats the surface of each layer from which the probe is formed including interlayer regions. These first two groups of embodiments incorporate both the core material and the coating material during the formation of each layer. Still other embodiments are directed to the electrochemical fabrication of microprobe arrays that are partially encapsulated by a dielectric material during a post layer formation coating process. In even further embodiments, the electrochemical fabrication of microprobes from two or more materials may occur by incorporating a coating material around each layer of the structure without locating the coating material in inter-layer regions.
    Type: Grant
    Filed: January 3, 2005
    Date of Patent: May 12, 2009
    Assignee: Microfabrica Inc.
    Inventors: Adam L. Cohen, Ananda H. Kumar, Michael S. Lockard, Dennis R. Smalley
  • Publication number: 20090107846
    Abstract: The present invention improves the wetting between electrolyte and the wafer surface when they are put into contact by pre-implementing an adsorbed liquid layer on the entire front surface of the wafer just prior to the plating process. The pre-implementing adsorbed liquid layer is realized by transporting vaporized liquid molecules from vapor phase at elevated temperature (relative to wafer) and condensing them onto wafer surface.
    Type: Application
    Filed: December 27, 2007
    Publication date: April 30, 2009
    Applicant: ACM Research (Shanghai) Inc.
    Inventors: Yue Ma, David Wang
  • Patent number: 7524427
    Abstract: Some embodiments of the present invention are directed to techniques for building up single layer or multi-layer structures on dielectric or partially dielectric substrates. Certain embodiments deposit seed layer material directly onto substrate materials while other embodiments use an intervening adhesion layer material. Some embodiments use different seed layer materials and/or adhesion layer materials for sacrificial and structural conductive building materials. Some embodiments apply seed layer and/or adhesion layer materials in what are effectively selective manners while other embodiments apply the materials in blanket fashion. Some embodiments remove extraneous depositions (e.g. depositions to regions unintended to form part of a layer) via planarization operations while other embodiments remove the extraneous material via etching operations.
    Type: Grant
    Filed: January 3, 2005
    Date of Patent: April 28, 2009
    Assignee: Microfabrica Inc.
    Inventors: Adam L. Cohen, Michael S. Lockard, Kieun Kim, Qui T. Le, Gang Zhang, Uri Frodis, Dale S. McPherson, Dennis R. Smalley
  • Publication number: 20090101508
    Abstract: The invention relates to a method for producing at least one hydrophilic area on a hydrophobic substrate. The method consists in performing an electrochemical reduction of the surface under the following conditions: the reduction is performed in an electrochemical cell which contains an electrolytic solution containing a compound that is a precursor of a reducing agent, said compound having a standard potential of less than ?2.7 V relative to the saturated calomel electrode (SCE); the reducing electrode is placed relative to the substrate surface to be treated such that said surface is facing the surface of the electrode, which is the image of the area to be reduced; the reducing electrode is subjected to the formation potential of the reducing agent.
    Type: Application
    Filed: June 6, 2006
    Publication date: April 23, 2009
    Applicant: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Catherine Combellas, Frederic Kanoufi, Adrien Fuchs
  • Publication number: 20090098318
    Abstract: Described herein is a housing comprising an inside and at least one sidewall, wherein the at least one sidewall comprises inner and outer surfaces. An etch stop deposit is disposed over at least a portion of the housing, and a diaphragm material deposit is disposed over at least a portion of the etch stop deposit.
    Type: Application
    Filed: October 15, 2007
    Publication date: April 16, 2009
    Applicant: KAVLICO CORPORATION
    Inventors: Robert GUZIAK, Enrique GANDARIA
  • Publication number: 20090095632
    Abstract: An electrochemical fabrication process produces three-dimensional structures (e.g. components or devices) from a plurality of layers of deposited materials wherein the formation of at least some portions of some layers are produced by operations that remove material or condition selected surfaces of a deposited material. In some embodiments, removal or conditioning operations are varied between layers or between different portions of a layer such that different surface qualities are obtained. In other embodiments varying surface quality may be obtained without varying removal or conditioning operations but instead by relying on differential interaction between removal or conditioning operations and different materials encountered by these operations.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 16, 2009
    Inventors: Adam L. Cohen, Dennis R. Smalley
  • Patent number: 7517462
    Abstract: Some embodiments of the present invention are directed to techniques for building up single layer or multi-layer structures on dielectric or partially dielectric substrates. Certain embodiments deposit seed layer material directly onto substrate materials while other embodiments use an intervening adhesion layer material. Some embodiments use different seed layer materials and/or adhesion layer materials for sacrificial and structural conductive building materials. Some embodiments apply seed layer and/or adhesion layer materials in what are effectively selective manners while other embodiments apply the materials in blanket fashion. Some embodiments remove extraneous depositions (e.g. depositions to regions unintended to form part of a layer) via planarization operations while other embodiments remove the extraneous material via etching operations.
    Type: Grant
    Filed: January 3, 2005
    Date of Patent: April 14, 2009
    Assignee: Microfabrica Inc.
    Inventors: Adam L. Cohen, Michael S. Lockard, Kieun Kim, Qui T. Le, Gang Zhang, Uri Frodis, Dale S. McPherson, Dennis R. Smalley
  • Patent number: 7517444
    Abstract: The present invention relates to methods and apparatus for plating a conductive material on a workpiece surface in a highly desirable manner. Using a workpiece-surface-influencing device, such as a mask or sweeper, that preferentially contacts the top surface of the workpiece, relative movement between the workpiece and the workpiece-surface-influencing device is established so that an additive in the electrolyte solution disposed on the workpiece and which is adsorbed onto the top surface is removed or otherwise its amount or concentration changed with respect to the additive on the cavity surface of the workpiece. Plating of the conductive material can place prior to, during and after usage of the workpiece-surface-influencing device, particularly after the workpiece surface influencing device no longer contacts any portion of the top surface of the workpiece, to achieve desirable semiconductor structures.
    Type: Grant
    Filed: July 26, 2005
    Date of Patent: April 14, 2009
    Assignee: Novellus Systems, Inc.
    Inventor: Bulent M. Basol
  • Publication number: 20090084756
    Abstract: An electrochemical fabrication process produces three-dimensional structures (e.g. components or devices) from a plurality of layers of deposited materials wherein the formation of at least some portions of some layers are produced by operations that remove material or condition selected surfaces of a deposited material. In some embodiments, removal or conditioning operations are varied between layers or between different portions of a layer such that different surface qualities are obtained. In other embodiments varying surface quality may be obtained without varying removal or conditioning operations but instead by relying on differential interaction between removal or conditioning operations and different materials encountered by these operations.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 2, 2009
    Inventors: Adam L. Cohen, Dennis R. Smalley
  • Publication number: 20090081381
    Abstract: A method of enabling selective area plating on a substrate includes forming a first electrically conductive layer (310) over substantially all of the substrate, covering sections of the first electrically conductive layer with a mask (410) such that the first electrically conductive layer has a masked portion and an unmasked portion, forming a second electrically conductive layer (710, 1210), the second electrically conductive layer forming only over the unmasked portion of the first electrically conductive layer, and removing the mask and the masked portion of the first electrically conductive layer. In an embodiment, the mask covering sections of the first electrically conductive layer is a non-electrically conductive substance (1010) applied with a stamp (1020). In an embodiment, the mask is a black oxide layer.
    Type: Application
    Filed: September 26, 2007
    Publication date: March 26, 2009
    Inventors: Omar Bchir, Houssam Jomaa, Islam A. Salama, Yonggang Li
  • Publication number: 20090072222
    Abstract: Preferred embodiments provide a method for forming at least one catalyst nanoparticle on at least one sidewall of a three-dimensional structure on a main surface of a substrate, the main surface lying in a plane and the sidewall of the three-dimensional structure lying in a plane substantially perpendicular to the plane of the main surface of the substrate. The method comprises obtaining a three-dimensional structure on the main surface, the three-dimensional structure comprising catalyst nanoparticles embedded in a non-catalytic matrix and selectively removing at least part of the non-catalytic matrix at the sidewalls of the three-dimensional structure to thereby expose at least one catalyst nanoparticle. According to preferred embodiments a method is also provided for forming at least one elongated nanostructure, such as e.g. a nanowire or carbon nanotube, using the catalyst nanoparticles formed by the method according to preferred embodiments as a catalyst.
    Type: Application
    Filed: June 26, 2008
    Publication date: March 19, 2009
    Applicant: Interuniversitair Microelektronica Centrum vzw (IMEC)
    Inventors: Aleksandar Radisic, Philippe M. Vereecken