Masking Of A Substrate Using Material Resistant To An Etchant (i.e., Etch Resist) Patents (Class 216/41)
  • Patent number: 9023219
    Abstract: A method of manufacturing a magnetoresistive-based device includes a metal hard mask that is inert to a top electrode etch chemistry and that has low sputter yield during a magnetic stack sputter. The metal hard mask is patterned by the photo resist and the photo mask is then stripped and the top electrode (overlying magnetic materials of the magnetoresistive-based device) is patterned by the metal hard mask.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: May 5, 2015
    Assignee: Everspin Technologies, Inc.
    Inventors: Sarin Deshpande, Sanjeev Aggarwal, Kerry Nagel
  • Patent number: 9023223
    Abstract: In a method of generating a nanocrystal with a core-frame structure, a seed crystal, including a first substance, is exposed to a capping agent. The seed nanocrystal has a plurality of first portions that each has a first characteristic and a plurality of second portions that each has a second characteristic, different from the first characteristic. The capping agent has a tendency to adsorb to portions having the first characteristic and has a tendency not to adsorb to portions having the second characteristic. As a result, a selectively capped seed nanocrystal is generated. The selectively capped seed nanocrystal is exposed to a second substance that has a tendency to nucleate on the plurality of second portions and that does not have a tendency to nucleate on portions that have adsorbed the capping agent, thereby generating a frame structure from the plurality of second portions of the seed nanocrystal.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: May 5, 2015
    Assignee: Georgia Tech Research Corporation
    Inventors: Younan Xia, Shuifen Xie
  • Patent number: 9023457
    Abstract: Described herein are various methods for making textured articles, textured articles that have improved fingerprint resistance, and methods of using the textured articles. The methods generally make use of masks comprising nanostructured metal-containing features to produce textured surfaces that also comprise nanostructured features. These nanostructured features in the textured surfaces can render the surfaces hydrophobic and oleophobic, thereby beneficially providing the articles with improved fingerprint resistance relative to similar or identical articles that lack the texturing.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: May 5, 2015
    Assignee: Corning Incorporated
    Inventors: Albert Carrilero, Prantik Mazumder, Johann Osmond, Valerio Pruneri, Paul Arthur Sachenik, Lili Tian
  • Publication number: 20150119807
    Abstract: A method of preparing a substantially planar microdevice comprising a plurality of reservoirs is provided. In general, the method comprises forming a plurality of microdevices comprising a plurality of reservoirs from a planar layer of a biocompatible polymer. The method also comprises depositing one or more bioactive agents into the reservoirs. The microdevice is configured to attach to a target tissue and release the bioactive agent in close proximity to the tissue.
    Type: Application
    Filed: May 24, 2013
    Publication date: April 30, 2015
    Applicant: The Regents of the University of California
    Inventors: Tejal A. Desai, Hariharasudhan D. Chirra
  • Patent number: 9017561
    Abstract: A piezo-resistive MEMS resonator comprising an anchor, a resonator mounted on the anchor, an actuator mounted to apply an electrostatic force on the resonator and a piezo-resistive read-out means comprising a nanowire coupled to the resonator.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: April 28, 2015
    Assignee: NXP, B.V.
    Inventors: Gerhard Koops, Jozef Thomas Martinus van Beek
  • Patent number: 9017563
    Abstract: Provided is a plating method of a circuit substrate comprising a conductive pattern in which a metal layer containing at least silver and copper is exposed on an outer surface. The plating method comprises: step (A) of treating the circuit substrate with a first liquid agent containing an oxidizing agent; step (B) of treating the circuit substrate after the step (A) with a second liquid agent which dissolves copper oxide, and thereby removing copper oxide from the conductive pattern's surface; step (C) of treating the circuit substrate after the step (B) with a third liquid agent whose rate of dissolving silver oxide (I) at 25° C. is 1000 times or more faster than its rate of dissolving copper (0) at 25° C., and thereby removing silver oxide from the conductive pattern's surface; and step (D) of performing electroless plating on the conductive pattern of the circuit substrate after the step (C).
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: April 28, 2015
    Assignee: Tokuyama Corporation
    Inventors: Emi Ushioda, Tetsuo Imai
  • Patent number: 9011705
    Abstract: The present invention relates to a method of forming polymer substrate with variable refractive index sensitivity, the method comprising the steps of: (a) contacting a metal-coated patterned mold with a polymer substrate at a temperature sufficient to deform said polymer substrate to thereby deposit a patterned mask of a metal film on the polymer substrate; and (b) etching away portions of said polymer substrate not covered by said patterned mask under conditions to form a region of variable refractive index sensitivity on said polymer substrate.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: April 21, 2015
    Assignee: Agency for Science, Technology and Research
    Inventors: Kwok Wei Shah, Xiaodi Su, Soo Jin Chua, Hong Yee Low
  • Patent number: 9009950
    Abstract: Disclosed herein is a method for manufacturing a high frequency inductor, the method including; forming a primary coil for manufacturing the high frequency inductor on a wafer; coating a primary PSV on the wafer on which the primary coil is formed; forming a secondary coil for manufacturing the high frequency inductor, after the coating of the primary PSV; coating a secondary PSV, after the forming of the secondary coil; forming a barrier layer on an electrode portion to be exposed of the high frequency inductor, after the coating of the secondary PSV; filling and curing an insulating resin on the wafer, after the forming of the barrier layer; and polishing the cured resin up to the barrier layer to expose the electrode.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: April 21, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Sang Moon Lee, Young Seuck Yoo, Jong Yun Lee, Young Do Kweon, Sung Kwon Wi
  • Patent number: 9005458
    Abstract: Disclosed method and apparatus embodiments provide a photonic device with optical isolation from a supporting substrate. A generally rectangular cavity in cross section is provided below an element of the photonic device and the element may be formed from a ledge of the supporting substrate which is over the cavity.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: April 14, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej Sandhu, Roy Meade
  • Patent number: 9005463
    Abstract: A method of forming a substrate opening includes forming a plurality of side-by-side openings in a substrate. At least some of immediately adjacent side-by-side openings are formed in the substrate to different depths relative one another. Walls that are laterally between the side-by-side openings are removed to form a larger opening having a non-vertical sidewall surface where the walls were removed in at least one straight-line vertical cross-section that passes through the sidewall surface orthogonally to the removed walls.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: April 14, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Mark Kiehlbauch
  • Patent number: 9005456
    Abstract: Disclosed herein is a method for manufacturing a printed circuit board, wherein a protective film for stripping and a metal layer closely adhered to the protective film for stripping are formed on an inner layer pad to protect the inner layer pad at the time of laser processing related to cavity processing and applying an etchant, thereby making it possible to improve reliability of a product.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: April 14, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kwang Sun You, Seung Ryeol Lee, Sang Hoon Park, Kyung Jin Heo, Jae Ho Shin, Joong Hyuk Jung
  • Publication number: 20150097204
    Abstract: A method of producing the crystalline substrate having a concave-convex structure includes: (A) forming a transfer film by forming a concave-convex film on a support film on the surface having a concave-convex pattern thereon so that thickness of the residual film of the concave-convex film is 0.01 to 1 ?m, the concave-convex pattern of the support film having concave parts with a width of 0.05 to 100 ?m, a depth of 0.05 to 10 ?m, and a ratio of the depth of the concave part to the width of the concave part of up to 1.5, (B) disposing the transfer film on the crystalline substrate, and transferring the concave-convex film onto the crystalline substrate to produce a crystalline substrate having the concave-convex film thereon, (C) etching the crystalline substrate having the concave-convex film thereon to form a concave-convex structure on the surface of a crystalline substrate.
    Type: Application
    Filed: August 9, 2012
    Publication date: April 9, 2015
    Applicant: Toray Industries, Inc.
    Inventors: Susumu Takada, Emi Kuraseko, Motoyuki Suzuki
  • Patent number: 8999180
    Abstract: A process of manufacturing a solar cell is provided. The process comprising the steps of: i) ink jet printing an alkali removable water insoluble hot melt ink jet ink onto a substrate comprising a silicon wafer to form a resist image on the substrate; ii) etching or plating the substrate in an aqueous acid medium; and iv) removing the resist image with an aqueous alkali.
    Type: Grant
    Filed: August 6, 2007
    Date of Patent: April 7, 2015
    Assignee: Sun Chemical Corporation
    Inventor: Nigel Anthony Caiger
  • Patent number: 8992787
    Abstract: Anode foils suitable for use in electrolytic capacitors, including those having multiple anode configurations, have improved strength, reduced brittleness, and increased capacitance compared to conventional anode foils for electrolytic capacitors. Exemplary methods of manufacturing an anode foil suitable for use in an electrolytic capacitor include disposing a resist material in a predetermined pattern on an exposed surface of an anode foil substrate such that a first portion of the exposed surface of the anode foil substrate is covered by the resist material, and a second portion of the exposed surface remains uncovered; polymerizing the resist material; exposing at least the second portion of the exposed surface to one or more etchants so as to form a plurality of tunnels; stripping the polymerized resist material; and widening at least a portion of the plurality of tunnels. The resist material may be deposited, for example, by ink-jet printing, stamping or screen printing.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: March 31, 2015
    Assignee: Pacesetter, Inc.
    Inventors: David R. Bowen, Ralph Jason Hemphill, Xiaofei Jiang, Corina Geiculescu, Tearl Stocker
  • Patent number: 8992788
    Abstract: In conjunction with a photomask blank comprising a transparent substrate, a pattern-forming film, and an etch mask film, a set of etching conditions for the pattern-forming film is evaluated by measuring a first etching clear time (C1) taken when the etch mask film is etched under the etching conditions to be applied to the pattern-forming film, measuring a second etching clear time (C2) taken when the pattern-forming film is etched under the etching conditions, and computing a ratio (C1/C2) of the first to second etching clear time.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: March 31, 2015
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shinichi Igarashi, Hiroki Yoshikawa, Yukio Inazuki, Hideo Kaneko
  • Patent number: 8992789
    Abstract: According to one embodiment, a method is disclosed for manufacturing a mold. The method can include forming a second major surface receded from a first major surface by irradiating a portion of the first major surface with a charged beam to etch a base material having the first major surface. The method can include forming a mask pattern on the first major surface and the second major surface. In addition, the method can include forming a first pattern on the first major surface and a second pattern on the second major surface by etching the base material through the mask pattern.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masato Suzuki, Tetsuro Nakasugi
  • Publication number: 20150087524
    Abstract: There is provided a method for producing a substrate (600) suitable for supporting an elongated superconducting element, wherein, e.g., a deformation process is utilized in order to form disruptive strips in a layered solid element, and where etching is used to form undercut volumes (330, 332) between an upper layer (316) and a lower layer (303) of the layered solid element. Such relatively simple steps enable providing a substrate which may be turned into a superconducting structure, such as a superconducting tape, having reduced AC losses, since the undercut volumes (330, 332) may be useful for separating layers of material. In a further embodiment, there is placed a superconducting layer on top of the upper layer (316) and/or lower layer (303), so as to provide a superconducting structure with reduced AC losses.
    Type: Application
    Filed: May 17, 2013
    Publication date: March 26, 2015
    Inventor: Anders Christian Wulff
  • Patent number: 8986560
    Abstract: A method for producing an optical semiconductor device includes the steps of determining a wafer size to make a section arrangement including a plurality of sections in each of which the optical semiconductor device including a semiconductor mesa is formed; obtaining an in-plane distribution of a thickness of a resin layer on a wafer; obtaining a correlation between a thickness of a resin layer and a trench width; forming a trench width map using the in-plane distribution of the thickness and the correlation; preparing an epitaxial substrate by forming a stacked semiconductor layer; forming, on the epitaxial substrate, a mask based on the trench width map; forming a trench structure including the semiconductor mesa by etching the stacked semiconductor layer using the mask; forming a resin layer on the trench structure; and forming an opening on the semiconductor mesa by etching the resin layer.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: March 24, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takamitsu Kitamura, Hideki Yagi
  • Patent number: 8985049
    Abstract: Pressure maskers for masking at least one passageway of an article include a body portion that surrounds at least a portion of the article around the at least one passageway, at least one fluid inlet connected to the body portion that provides a conduit for pressurized masking fluid to pass from an exterior of the pressure masker to an interior of the pressure masker, wherein the article is at least partially disposed within the interior of the pressure masker, and at least one seal that seals the body portion at least partially around the article such that the pressurized masking fluid that enters the interior of the pressure masker is at least partially forced through the at least one passageway.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 24, 2015
    Assignee: General Electric Company
    Inventors: Mark Carmine Bellino, Jonathan Matthew Lomas, Matthew Paul Berkebile, Michael Anthony DePalma, III
  • Patent number: 8986554
    Abstract: A method of forming patterns includes forming a photoresist film on a substrate. The photoresist film is exposed with a first dose of light to form a first area and a second area in the photoresist film. A first hole and a second hole are formed by removing the first area and the second area with a first developer. The photoresist film is re-exposed with a second dose of the light to form a third area in the photoresist film between the first hole and the second hole. A third hole is formed between the first hole and the second hole by removing the third area with a second developer.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: March 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-sung Kim, Kyoung-seon Kim, Jae-woo Nam, Chul-ho Shin, Shi-young Yi
  • Patent number: 8986561
    Abstract: Disclosed is a substrate processing method of etching a substrate including a target layer, and a mask layer and an intermediate layer that are stacked on the target layer, to form a pattern on the target layer via the intermediate layer and the mask layer. The intermediate layer is etched under a processing pressure of 100 mTorr (1.33×10 Pa) to 150 mTorr (2.0×10 Pa) by using as a processing gas a mixture gas of CF4, CHF3, and C4F8, and the mask layer is etched by using a COS-containing gas as a processing gas.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: March 24, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Sungtae Lee, Masahiro Ogasawara, Masahiro Ito
  • Patent number: 8986555
    Abstract: A method of manufacturing a printed circuit board having a bump is disclosed. The method includes preparing a first carrier having a first circuit formed thereon, compressing the first carrier to one surface of an insulation layer such that the first circuit is buried, stacking an etching resist on the first carrier in accordance with where the bump is to be formed and forming the bump by etching the first carrier. In accordance with an embodiment of the present invention, the difference in height between a bump and its adjacent bump in a printed circuit board can be reduced, and thus electrical connection between an electronic component and the printed circuit board can be better implemented.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: March 24, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Ji-Eun Kim, Nam-Keun Oh, Jung-Hyun Park, Young-Ji Kim, Jong-Gyu Choi, Sang-Duck Kim
  • Publication number: 20150079336
    Abstract: A processing chamber component and method for fabricating the same are provided. The processing chamber component is fabricated in the manner described herein and includes the creation of at least a macro texture on a surface of the chamber component. The macro texture is defined by a plurality of engineered features arranged in a predefined orientation on the surface of the chamber component. In some embodiments, the engineered features prevent formation of a line of sight surface defined between the features to enhance retention of films deposited on the chamber component.
    Type: Application
    Filed: September 17, 2013
    Publication date: March 19, 2015
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Jianqi WANG, William Ming-ye LU, Yukari NISHIMURA, Joseph F. SOMMERS, Sio On LO, Rajan BALESAN
  • Patent number: 8980110
    Abstract: A liquid ejection head includes a substrate having an ejection energy generating element formed at a first surface side thereof, a common liquid chamber formed at a second surface of the substrate, and a liquid supply port extending from the bottom of the common liquid chamber to the first surface. The liquid ejection head is manufactured by preparing a substrate having the common liquid chamber formed at the second surface side, then arranging a material to be filled in the common liquid chamber, subsequently forming an aperture in the filled material as corresponding to the liquid supply port to be formed, and thereafter forming the liquid supply port by reactive ion etching, using at least the filled material as a mask.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: March 17, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masahisa Watanabe, Kazuhiro Hayakawa, Toshiyasu Sakai
  • Patent number: 8980418
    Abstract: A plasma etch resist material modified by an inorganic protective component via sequential infiltration synthesis (SIS) and methods of preparing the modified resist material. The modified resist material is characterized by an improved resistance to a plasma etching or related process relative to the unmodified resist material, thereby allowing formation of patterned features into a substrate material, which may be high-aspect ratio features. The SIS process forms the protective component within the bulk resist material through a plurality of alternating exposures to gas phase precursors which infiltrate the resist material. The plasma etch resist material may be initially patterned using photolithography, electron-beam lithography or a block copolymer self-assembly process.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: March 17, 2015
    Assignee: UChicago Argonne, LLC
    Inventors: Seth B. Darling, Jeffrey W. Elam, Yu-Chih Tseng, Qing Peng
  • Publication number: 20150069015
    Abstract: In a method of generating a nanocrystal with a core-frame structure, a seed crystal, including a first substance, is exposed to a capping agent. The seed nanocrystal has a plurality of first portions that each has a first characteristic and a plurality of second portions that each has a second characteristic, different from the first characteristic. The capping agent has a tendency to adsorb to portions having the first characteristic and has a tendency not to adsorb to portions having the second characteristic. As a result, a selectively capped seed nanocrystal is generated. The selectively capped seed nanocrystal is exposed to a second substance that has a tendency to nucleate on the plurality of second portions and that does not have a tendency to nucleate on portions that have adsorbed the capping agent, thereby generating a frame structure from the plurality of second portions of the seed nanocrystal.
    Type: Application
    Filed: September 9, 2014
    Publication date: March 12, 2015
    Applicant: GEORGIA TECH RESEARCH CORPORATION
    Inventors: Younan Xia, Shuifen Xie
  • Patent number: 8974682
    Abstract: A self-assembled pattern forming method in an embodiment includes: forming a guide pattern on a substrate; forming a layer of a first polymer; filling a first block copolymer; and phase-separating the first block copolymer. The guide pattern includes a first recessed part having a depth T and a diameter D smaller than the depth T, and a second recessed part having a width larger than double of the diameter D. The first block copolymer has the first polymer and a second polymer which are substantially the same in volume fraction. By phase-separating the first block copolymer, a cylinder structure and a lamellar structure are obtained.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: March 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Hieda, Yoshiyuki Kamata, Naoko Kihara, Akira Kikitsu, Ryosuke Yamamoto
  • Patent number: 8974685
    Abstract: Provided is a fine-processing agent which, when fine-processing a laminated film stacked at least with a silicon dioxide film and a silicon nitride film, can selectively fine-process the silicon dioxide film. Also provided is a fine-processing method utilizing the fine-processing agent. The fine-processing agent is characterized by including: (a) 0.01-15.0 weight % hydrogen fluoride and/or 0.1-40.0 weight % ammonium fluoride, (b) water, and (c) 0.001-10.00 weight % water-soluble polymer selected from among a group consisting of acrylic acid, ammonium acrylate, acrylic acid ester, acrylamide, styrenesulfonic acid, ammonium styrenesulfonate, and styrenesulfonic acid ester.
    Type: Grant
    Filed: May 21, 2009
    Date of Patent: March 10, 2015
    Assignee: Stella Chemifa Corporation
    Inventors: Masayuki Miyashita, Takanobu Kujime, Keiichi Nii
  • Patent number: 8974683
    Abstract: A method of reducing roughness in an opening in a surface of a resist material disposed on a substrate, comprises generating a plasma having a plasma sheath and ions therein. The method also includes modifying a shape of a boundary defined between the plasma and the plasma sheath with a plasma sheath modifier so that a portion of the boundary facing the resist material is not parallel to a plane defined by the surface of the substrate. The method also includes providing a first exposure of ions while the substrate is in a first position, the first exposure comprising ions accelerated across the boundary having the modified shape toward the resist material over an angular range with respect to the surface of the substrate.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: March 10, 2015
    Inventors: Ludovic Godet, Patrick M. Martin, Joseph C. Olson, Andrew J. Hornak
  • Patent number: 8974678
    Abstract: Block copolymers can be self-assembled and used in methods as described herein for sub-lithographic patterning, for example. The block copolymers can be diblock copolymers, triblock copolymers, multiblock copolymers, or combinations thereof. Such methods can be useful for making devices that include, for example, sub-lithographic conductive lines.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: March 10, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Dan Millward
  • Publication number: 20150065389
    Abstract: The present invention is drawn to the generation of micropatterns of biomolecules and cells on standard laboratory materials through selective ablation of a physisorbed biomolecule with oxygen plasma. In certain embodiments, oxygen plasma is able to ablate selectively physisorbed layers of biomolecules (e.g., type-I collagen, fibronectin, laminin, and Matrigel) along complex non-linear paths which are difficult or impossible to pattern using alternative methods. In addition, certain embodiments of the present invention relate to the micropatterning of multiple cell types on curved surfaces, multiwell plates, and flat bottom flasks. The invention also features kits for use with the subject methods.
    Type: Application
    Filed: March 26, 2014
    Publication date: March 5, 2015
    Applicant: Massachusetts Institute of Technology
    Inventors: David T. Eddington, Sangeeta N. BHATIA
  • Publication number: 20150060402
    Abstract: Methods for forming vias in glass substrates by laser drilling and acid etching are disclosed. In one embodiment, a method forming a via in a glass substrate includes laser drilling the via through at least a portion of a thickness of the glass substrate from an incident surface of the glass substrate. The method further includes etching the glass substrate for an etching duration to increase a diameter of an incident opening of the via and applying ultrasonic energy to the glass substrate during at least a portion of the etching duration. The applied ultrasonic energy has a frequency between 40 kHz and 192 kHz.
    Type: Application
    Filed: August 21, 2014
    Publication date: March 5, 2015
    Inventors: Robert Carl Burkett, Uta-Barbara Goers, Samuel Odei Owusu, Tammy Lynn Petriwsky
  • Publication number: 20150061455
    Abstract: A vibration device including a supporting portion formed to cover both ends of a vibration region, and a method of manufacturing the vibration device are provided. The vibration device may include a lower substrate on which an insulating layer is formed, an upper substrate connected onto the insulating layer, and including a vibration region that vibrates and that is separated from the lower substrate by at least a predetermined distance, and a supporting portion formed to cover both ends of the vibration region, to support the vibration region.
    Type: Application
    Filed: September 2, 2014
    Publication date: March 5, 2015
    Inventors: In Bok BAEK, Han Young YU, Yark Yeon KIM, Young Jun KIM, Chang Geun AHN, Yong Sun YOON, Bong Kuk LEE, Ji Eun LIM, Won Ick JANG
  • Patent number: 8968586
    Abstract: A pattern-forming method includes forming a prepattern on a substrate. A space other than a space in which the prepattern is formed on the substrate is filled with a resin composition containing a compound which is diffusible into the prepattern. The compound is diffused into a part of the prepattern. Portions in which the compound is undiffused in the prepattern are removed using a removing liquid.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: March 3, 2015
    Assignee: JSR Corporation
    Inventor: Hayato Namai
  • Patent number: 8968585
    Abstract: Methods to fabricate reaction cartridges for biological sample preparation and analysis are disclosed. A cartridge may have a reaction chamber and openings to allow fluids to enter the chamber. The cartridge may also have handles to facilitate its use. Such cartridges may be used for polymerase chain reaction.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: March 3, 2015
    Assignee: California Institute of Technology
    Inventors: Imran R. Malik, Axel Scherer, Erika F. Garcia, Xiomara L. Madero
  • Patent number: 8968584
    Abstract: A method for manufacturing a liquid ejection head includes the steps of: disposing an etching mask layer on a substrate having a first face and a second face that is on an opposite side of the first face, the etching mask layer being disposed on the second face; forming a concave line pattern at a region of the etching mask layer other than a region where an opening for the support port is to be formed; providing an etching opening at the etching mask layer; performing anisotropic etching from a side of the second face using the etching mask layer provided with the etching opening as a mask, thus forming the supply port at the substrate; comparing the line pattern with a recess generated at the substrate, thus selecting a device chip for liquid ejection; and connecting the selected device chip to a liquid supply part.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: March 3, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Jun Yamamuro, Yoshinori Tagawa, Satoshi Ibe, Hiroto Komiyama, Kouji Hasegawa, Shiro Sujaku
  • Publication number: 20150056809
    Abstract: Disclosed is an improved double patterning method for forming openings (e.g., vias or trenches) or mesas on a substrate. This method avoids the wafer topography effects seen in prior art double patterning techniques by ensuring that the substrate itself is only subjected to a single etch process. Specifically, in the method, a first mask layer is formed on the substrate and processed such that it has a doped region and multiple undoped regions within the doped region. Then, either the undoped regions or the doped region can be selectively removed in order to form a mask pattern above the substrate. Once the mask pattern is formed, an etch process can be performed to transfer the mask pattern into the substrate. Depending upon whether the undoped regions are removed or the doped region is removed, the mask pattern will form openings (e.g., vias or trenches) or mesas, respectively, on the substrate.
    Type: Application
    Filed: September 30, 2014
    Publication date: February 26, 2015
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Ying Zhang
  • Patent number: 8961800
    Abstract: Functional nanoparticles may be formed using at least one nano-lithography step. In one embodiment, sacrificial material may be patterned on a multi-layer substrate using an imprint lithography system. The pattern may be further etched into the multi-layer substrate. Functional material may then be deposited on multi-layer substrate and solidified. At least a portion of the functional material may then be removed to provide a crown surface exposing pillars. Pillars may be removed from multi-layer substrate forming functional nanoparticles.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: February 24, 2015
    Assignees: Board of Regents, The University of Texas System, Molecular Imprints, Inc.
    Inventors: Sidlgata V. Sreenivasan, Shuqiang Yang, Frank Y. Xu, Vikramjit Singh
  • Patent number: 8961799
    Abstract: A method of forming a nano-structured substrate is provided, the method comprising including forming non-integral nano-pillars on a substrate surface and directionally etching the substrate surface using the non-integral nano-pillars as a mask to form integral nano-structures in the substrate.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: February 24, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Peter Mardilovich, Anthony M. Fuller, Qingqiao Wei
  • Patent number: 8961801
    Abstract: In an embodiment, there is provided an imprint lithography method that includes providing a first amount of imprintable medium on a first area of a substrate, the first amount of imprintable medium, when fixed, having a first etch rate; and providing a second amount of imprintable medium on a second, different area of the substrate, the second amount of imprintable medium, when fixed, having a second, different etch rate.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: February 24, 2015
    Assignee: ASML Netherlands B.V.
    Inventors: Sander Frederik Wuister, Vadim Yevgenyevich Banine, Johan Frederik Dijksman, Yvonne Wendela Kruijt-Stegeman, Jeroen Herman Lammers, Roelof Koole
  • Publication number: 20150048375
    Abstract: Provided is a method of manufacturing a gradually stretchable substrate. The method includes forming convex regions and concave regions on a top surface of a stretchable substrate by compressing a mold onto the stretchable substrate and forming non-stretchable patterns by filling the concave regions of the stretchable substrate. The stretchable substrate includes a stretchable region defined by the non-stretchable patterns, the non-stretchable patterns have side surfaces in contact with the stretchable region, and the side surfaces of the non-stretchable patterns are formed of protrusions and a non-protrusion between the protrusions repetitively connected to one another.
    Type: Application
    Filed: April 2, 2014
    Publication date: February 19, 2015
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Ji-Young OH, Jae Bon KOO, Sang Chul LIM, Chan Woo PARK, Soon-Won JUNG, Bock Soon NA, Sang Seok LEE, Hye Yong CHU
  • Patent number: 8956544
    Abstract: A method for manufacturing a micromechanical structure, and a micromechanical structure. The micromechanical structure encompasses a first micromechanical functional layer, made of a first material, that comprises a buried conduit having a first end and a second end; a micromechanical sensor structure having a cap in a second micromechanical functional layer that is disposed above the first micromechanical functional layer; an edge region in the second micromechanical functional layer, such that the edge region surrounds the sensor structure and defines an inner side containing the sensor structure and an outer side facing away from the sensor structure; such that the first end is located on the outer side and the second end on the inner side.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: February 17, 2015
    Assignee: Robert Bosch GmbH
    Inventors: Johannes Classen, Jochen Reinmuth, Sebastian Guenther, Pia Bustian-Todorov
  • Publication number: 20150044686
    Abstract: An article for holding a plurality of biological samples includes a substrate a substrate comprising a first surface and an opposing second surface and a plurality of reaction sites in the substrate. Each of the reaction sites extends from an opening in the first surface to an opening in the second surface. The reaction sites comprise a hexagonal shape and are configured to provide sufficient surface tension by capillary action to hold respective biological samples. The reaction sites have a density over at least a portion of the surfaces that is at least 170 holes per square millimeter. At least one of the surfaces may have a surface roughness characterized by an arithmetic average roughness (Ra) that is less than or equal to 5 nanometers.
    Type: Application
    Filed: March 15, 2013
    Publication date: February 12, 2015
    Applicant: Life Technologies Corporation
    Inventors: Michael Pallas, James C. Nurse, Kevin Maher, Jorge Fonseca, Eliodor Ghenciu, Evan Foster
  • Patent number: 8951612
    Abstract: A method for processing a surface involves depositing at least one class of enzymes (2) onto the surface (1); introducing at least a reactant (3) into an environment of the surface (1), and causing interaction between the enzymes (2) and the reactant (3), thereby to cause processing of a region of the surface (1), the processed region of the surface (1) being defined with respect to a region thereof that is proximate (4) to where the enzymes (3) have been deposited.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Emmanuel Delamarche, Matthias Geissler
  • Patent number: 8951424
    Abstract: A substrate for an electrowetting display device including a pixel electrode, a partition wall pattern and a water-repellent pattern. The pixel electrode is formed on a base substrate. The partition wall pattern is disposed along an edge of the pixel electrode to expose the pixel electrode. The water-repellent pattern is disposed at a space formed by the pixel electrode and the partition wall pattern to be extended along a lower portion of side surfaces of the partition wall pattern from an area on which the pixel electrode is formed. The water-repellent pattern exposes an upper portion of the side surfaces and an upper surface of the partition wall pattern. Thus, a manufacturing reliability of a substrate for an electrowetting display device is improved to prevent a display quality from being reduced.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: February 10, 2015
    Assignee: Amazon Technologies, Inc.
    Inventors: Seung Bo Shim, Jin-Ho Ju, Dae Ho Kim, Sang-Il Kim, Sung-Kyun Park, Jae-Jin Lyu
  • Patent number: 8951699
    Abstract: An adjustable photo-mask for providing variable properties includes a casing and a plate. The casing has a receiving room inside and a plurality of openings, with the openings extending from the receiving room to a front face of the casing. The plate has a plurality of through holes, with an axial direction of the through holes defined as a ray-transmission direction, with the plate slideably received in the receiving room, and with the through holes and the openings totally or partially overlapping in the ray-transmission direction.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: February 10, 2015
    Assignee: National Kaohsiung University of Applied Science
    Inventors: Chia-Chin Chiang, Chien-Chia Tseng
  • Patent number: 8951427
    Abstract: A method for manufacturing electrical and/or optical components, wherein a hot melt composition including an alkane based wax and an amorphous material as a masking material is used. The hot melt composition has a melting point of between 40° C. and 85° C. and a viscosity of between 5 and 20 mPa·s at not less than one temperature within the range of between 50° C. and 140° C. A hot melt composition includes between 40 weight % and 89.9 weight % of an alkane based wax; between 10 weight % and 50 weight % of an amorphous material; and between 0.1 weight % and 10 weight % of a phosphonium based ionic liquid. A system and a method for manufacturing electronic and/or optical components is provided, wherein after the etch processes and/or plating processes, the hot melt composition is removed from the substrate with the aid of hot water.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: February 10, 2015
    Assignee: Oce Technologies B.V.
    Inventors: Björn H. A. J. M. Ketelaars, Hylke Veenstra
  • Publication number: 20150034592
    Abstract: A method or process is disclosed for etching deep, high-aspect ratio features into silicon dioxide material layers and substrates, including glass, fused silica, quartz, or similar materials, using a plasma etch technology. The method has application in the fabrication and manufacturing of MEMS, microelectronic, micro-mechanical, photonic and nanotechnology devices in which silicon dioxide material layers or substrates are used and must be patterned and etched. Devices that benefit from the method described in this invention include the fabrication of MEMS gyroscopes, resonators, oscillators, microbalances, accelerometers, for example. The etch method or process allows etch depths ranging from below 10 microns to over 1 millimeter and aspect ratios from less than 1 to 1 to over 10 to 1 with etched feature sidewalls having vertical or near vertical angles. Additionally, the disclosed method provides requirements of the etched substrates to reduce or eliminate undesired effects of an etch.
    Type: Application
    Filed: July 30, 2013
    Publication date: February 5, 2015
    Applicant: Corporation For National Research Initiatives
    Inventors: Michael A. Huff, Michael Pedersen
  • Publication number: 20150036295
    Abstract: An electronic device includes a housing, a mother board received in the housing, and a plurality of heat-generating members received in the housing. A dissipation area is formed in the housing, and a plurality of dissipation holes are defined in an outer surface of the dissipation area. Each dissipation hole is in a nanometer scale. The disclosure also supplies a method for manufacturing a housing of the electronic device.
    Type: Application
    Filed: July 30, 2014
    Publication date: February 5, 2015
    Inventors: SHYAN-JUH LIU, KAR-WAI HON, SHA-SHA LIU
  • Patent number: 8945408
    Abstract: Provided is a method for preparing a patterned directed self-assembly layer, comprising: providing a substrate having a block copolymer layer comprising a first phase-separated polymer defining a first pattern in the block copolymer layer and a second phase-separated polymer defining a second pattern in the block copolymer layer; and performing an etching process to selectively remove the second phase-separated polymer while leaving behind the first pattern of the first phase-separated polymer on the surface of the substrate, the etching process being performed at a substrate temperature less than or equal to about 20 degrees C. The method further comprises providing a substrate holder for supporting the substrate, the substrate holder having a first temperature control element for controlling a first temperature at a central region and second temperature control element at an edge region of the substrate and setting a target value for the first and the second temperature.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: February 3, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Vidhya Chakrapani, Akiteru Ko, Kaushik Kumar