Gate Arrays Patents (Class 257/202)
With particular chip input/output means (Class 257/203)
Having specific type of active device (e.g., cmos) (Class 257/204)
With particular power supply distribution means (Class 257/207)
With particular signal path connections (Class 257/208)
  • Transistor structure and integrated circuit
    Patent number: 7385249
    Abstract: A process for forming a conductive gate structure for a sub-0.25 MOSFET technology, has been developed. The process features a conductive gate structure defined from a composite polysilicon or amorphous layer, which in turn is obtained via a dual deposition procedure. The first, or underlying silicon layer of the composite silicon layer, is deposited using a first silane flow rate which results in a silicon layer offering good performance characteristics but comprised with large silicon bumps. The second or overlying silicon layer of the composite silicon layer, is next deposited using a second silane flow rate, with the second silane flow greater than the silane flow used for the underlying silicon layer. The second silicon layer is formed with silicon bumps smaller in size than the silicon bumps of the first silicon layer.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: June 10, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Shih-I Yang
  • Gate array integrated circuit including a unit cell basic layer having gate terminal regions allowing two contact pads to be disposed laterally
    Patent number: 7385233
    Abstract: A gate array integrated circuit forming part of a semiconductor integrated circuit includes a basic layer of a unit cell in which a PMOS and an NMOS transistor are connected with a poly-silicon strip. The poly-silicon strip has gate terminal regions formed to laterally extend to allow two or more contact pads or through-holes to be disposed in each gate terminal region. It is thus possible to improve wiring efficiency and also micro-miniaturization and yield of the gate array integrated circuit. A layout method for a gate array integrated circuit is also provided.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: June 10, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hirofumi Uchida
  • Enhanced field programmable gate array
    Patent number: 7382155
    Abstract: An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: June 3, 2008
    Assignee: Actel Corporation
    Inventors: Samuel W. Beal, Sinan Kaptonoglu, Jung-Cheun Lien, William Shu, King W. Chan, William C. Plants
  • Methods of automatically generating dummy fill having reduced storage size
    Publication number: 20080121939
    Abstract: The disclosure relates generally to production of lithography masks such as used in mass production of monolithic integrated circuits (IC's). Layers of such IC's often need to be filled with dummy-fill. In accordance with the disclosure, dummy-objects are first generated by a conventional flat-fill technique and then they are automatically surrounded by outlines that are substantially wrinkle-free. The outlines are cleared of the original flat-fill and then used as areas that are to be automatically tiled by an auto-tiling program. Tiles are then re-filled with array definitions of regularly-spaced dummy-objects. The arrays consume less data storage space than do the original, individually-specified (flat-filled) dummy-objects. The array data is appended to layout data of functional objects in a layer of the integrated monolithic device (IC) to thereby generate a dummy-filled tapeout file.
    Type: Application
    Filed: November 6, 2006
    Publication date: May 29, 2008
    Inventors: Michael Murray, Van Nguyen
  • Semiconductor integrated circuit device
    Patent number: 7379319
    Abstract: A semiconductor integrated circuit device includes a semiconductor substrate and a plurality of cell transistors provided on a surface of the semiconductor substrate. A local bit line is provided above the cell transistors and electrically connected to one of a source diffusion layer and a drain diffusion layer of each of the cell transistors. Ferroelectric capacitors corresponding in number to the cell transistors, are provided above the local bit line, where each of the ferroelectric capacitors has an upper electrode and a lower electrode electrically connected to the other one of the source diffusion layer and drain diffusion layer of the corresponding one of the cell transistors. A plate line is provided above the upper electrodes and electrically connected to the upper electrodes. A reset transistor and a block selection transistor are provided on the surface of the semiconductor substrate.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: May 27, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Daisaburo Takashima
  • Top layers of metal for high performance IC's
    Patent number: 7372155
    Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length-by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: May 13, 2008
    Inventor: Mou-Shiung Lin
  • Semiconductor integrated circuit device formed by automatic layout wiring by use of standard cells and design method of fixing its well potential
    Patent number: 7368767
    Abstract: A standard cell is read from a library and automatic layout wiring is performed, thereby configuring a circuit. Next, each cell column in the configured circuit is searched for an empty region. In the empty region in the cell column searched for, a spacer cell or a filler cell is placed. At this time, using the spacer cell or filler cell, the well potential of the standard cells in the cell column is fixed.
    Type: Grant
    Filed: March 24, 2005
    Date of Patent: May 6, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Kinoshita, Yasuhito Itaka, Takeshi Sugahara
  • Fin field effect transistors (FinFETs) and methods for making the same
    Patent number: 7368787
    Abstract: In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) forming a first side of a fin of a fin field effect transistor (FinFET); (2) processing the first side of the fin; and (3) forming a second side of the fin while supporting the first side of the fin. Numerous other aspects are provided.
    Type: Grant
    Filed: May 19, 2005
    Date of Patent: May 6, 2008
    Assignee: International Business Machines Corporation
    Inventors: William P. Hovis, Jack A. Mandelman
  • Self-aligned method of forming a semiconductor memory array of floating gate memory cells with source side erase, and a memory array made thereby
    Publication number: 20080099789
    Abstract: A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a substrate of semiconductor material having a first conductivity type, source and drain regions formed in the substrate, a block of conductive material disposed over and electrically connected to the source, and a floating gate having a first portion disposed over and insulated from the source region and a second portion disposed over and insulated from the channel region. The floating gate first portion includes a sloped upper surface and a side surface that meet at an acute edge. An electrically conductive control gate is disposed over and insulated from the channel region for controlling a conductivity thereof.
    Type: Application
    Filed: November 1, 2006
    Publication date: May 1, 2008
    Inventors: Alexander Kotov, Amitay Levi, Hung Q. Nguyen, Pavel Klinger
  • Semiconductor integrated circuit device using four-terminal transistors
    Patent number: 7365377
    Abstract: In a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type, second well regions of a second conductivity type, and a third well region of the second conductivity type are formed. The second well regions are formed in the semiconductor substrate excluding the region where the first well region has been formed. The third well region is formed under the first and second well regions in the semiconductor substrate in such a manner that a part of the third well region under the first well region is removed, thereby connecting the second well regions to one another electrically.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: April 29, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Sugahara, Yasuhito Itaka
  • Selective deposition to improve selectivity and structures formed thereby
    Patent number: 7358547
    Abstract: Methods and associated apparatus of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising a region of higher active area density comprising source and drain recesses and a region of lower active area density comprising source and drain recesses, wherein the region of lower active area density further comprises dummy recesses, and selectively depositing a silicon alloy layer in the source, drain and dummy recesses to enhance the selectivity and uniformity of the silicon alloy deposition.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: April 15, 2008
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Nayanee Gupta, Chris Auth, Glenn A. Glass
  • MOS transistor structure with easy access to all nodes
    Patent number: 7355217
    Abstract: A transistor device structured such that the bulk, gate, drain, and source are all accessible from all four edges of the device is provided. The transistor is created with a four-metal CMOS process. A bulk connection can be made with Metal 1, which is all around the device. A gate connection can be made with Metal 2, which is all around the device. Additionally, a drain/source connection can be made with Metal 3, which is all around the device. A source/drain connection can be made with Metal 4, which is all around the device. The transistor structure may be used to create an array of transistors for a high power output stage, with the transistors arranged in a checkerboard pattern. The connections of each transistor are automatic by abutting edges of the transistors.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: April 8, 2008
    Assignee: National Semiconductor Corporation
    Inventor: Joerg Brand
  • Method of trimming technology
    Patent number: 7354847
    Abstract: A process for trimming a photoresist layer during the fabrication of a gate electrode in a MOSFET is described. A bilayer stack with a top photoresist layer on a thicker organic underlayer is patternwise exposed with 193 nm or 157 nm radiation to form a feature having a width w1 in the top layer. A pattern transfer through the underlayer is performed with an anisotropic etch based on H2/N2 and SO2 chemistry. The feature formed in the bilayer stack is trimmed by 10 nm or more to a width w2 by a HBr/O2/Cl2 plasma etch. The pattern transfer through an underlying gate layer is performed with a third etch based on HBr/O2/Cl2 chemistry. The underlayer is stripped by an O2 ashing with no damage to the gate electrode. Excellent profile control of the gate electrode is achieved and a larger (w1?w2) is possible than in prior art methods.
    Type: Grant
    Filed: January 26, 2004
    Date of Patent: April 8, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Bor-Wen Chan, Yi-Chun Huang, Baw-Ching Perng, Hun-Jan Tao
  • Memory device
    Patent number: 7348640
    Abstract: A memory capable of reducing the memory cell size is provided. In this memory, a first gate electrode of a first selection transistor and a second gate electrode of a second selection transistor are provided integrally with a word line, and arranged to obliquely extend with respect to the longitudinal direction of a first impurity region on a region formed with memory cells and to intersect with the first impurity region on regions formed with the first selection transistor and the second selection transistor in plan view.
    Type: Grant
    Filed: August 16, 2005
    Date of Patent: March 25, 2008
    Assignee: Sanyo Electric Company, Ltd.
    Inventor: Kouichi Yamada
  • Semiconductor memory device and defect remedying method thereof
    Patent number: 7345929
    Abstract: A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: March 18, 2008
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
  • DEMULTIPLEXERS USING TRANSISTORS FOR ACCESSING MEMORY CELL ARRAYS
    Publication number: 20080054306
    Abstract: A demultiplexer using transistors for accessing memory cell arrays. The demultiplexer includes (a) a substrate; (b) 2N semiconductor regions which are parallel to one another and run in a first direction; (c) first N gate electrode lines, which (i) run in a second direction which is perpendicular to the first direction, (ii) are electrically insulated from the 2N semiconductor regions, and (iii) are disposed between the first plurality of memory cells and the contact region; (d) a contact region; (e) a first plurality of memory cells. An intersection transistor exists at each of intersections between the first N gate electrode lines and the 2N semiconductor regions. In response to pre-specified voltage potentials being applied to the contact region and the first N gate electrode lines, memory cells of the first plurality of memory cells disposed on only one of the 2N semiconductor regions are selected.
    Type: Application
    Filed: August 30, 2006
    Publication date: March 6, 2008
    Inventors: Kailash Gopalakrishnan, Rohit Sudhir Shenoy
  • Structures of and methods of fabricating trench-gated MIS devices
    Patent number: 7335946
    Abstract: In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.
    Type: Grant
    Filed: July 22, 2004
    Date of Patent: February 26, 2008
    Assignee: Vishay-Siliconix
    Inventors: Anup Bhalla, Dorman Pitzer, Jacek Korec, Xiaorong Shi, Sik Lui
  • PHASE CHANGE MATERIALS AND ASSOCIATED MEMORY DEVICES
    Publication number: 20080042167
    Abstract: A memory device utilizes a phase change material as the storage medium. The phase change material includes at least one of Ge, Sb, Te, Se, As, and S, as well as a nitride compound as a dopant. The memory device can be a solid-state memory cell with electrodes in electrical communication with the phase change medium, an optical phase change storage device in which data is read and written optically, or a storage device based on the principle of scanning probe microscopy.
    Type: Application
    Filed: August 16, 2006
    Publication date: February 21, 2008
    Inventors: Yi-Chou Chen, Frances Anne Houle, Simone Raoux, Charles Thomas Rettner, Alejandro Gabriel Schrott
  • Methods of modulating the work functions of film layers
    Patent number: 7332433
    Abstract: Methods for fabricating two metal gate stacks with varying work functions for complementary metal oxide semiconductor (CMOS) devices are provided A first metal layer may be deposited onto a gate dielectric, followed by the deposition of a second metal layer, where the second metal layer modulated the work function of the first metal layer. The second metal layer and subsequently etch, exposing a portion of the first metal layer. A third metal layer may be deposited on the etched second metal layer and the exposed first metal layer, where the third metal layer may modulate the work function of the exposed first metal layer. Subsequent fabrication techniques may be used to define the gate stack.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: February 19, 2008
    Assignee: Sematech Inc.
    Inventors: Kisik Choi, Husam Alshareef, Prashant Majhi
  • Semiconductor device, wafer and method of designing and manufacturing the same
    Patent number: 7332753
    Abstract: A process margin of an interconnect is to be expanded, to minimize the impact of vibration generated during a scanning motion of a scanning type exposure equipment. In a semiconductor device, the interconnect handling a greater amount of data (frequently used interconnect) is disposed in a same orientation such that the longitudinal direction of the interconnects is aligned with a scanning direction of a scanning type exposure equipment, in an interconnect layer that includes a narrowest interconnect or a narrowest spacing between the interconnects. Aligning thus the direction of the vibration with the longitudinal direction of the pattern can minimize the positional deviation due to the vibration.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: February 19, 2008
    Assignee: NEC Electronics Corporation
    Inventors: Yoshihisa Matsubara, Hiromasa Kobayashi
  • Integrated circuit memory system with dummy active region
    Patent number: 7332378
    Abstract: An integrated circuit memory system including a substrate formed with equidistant spaced shallow trench isolation regions. Forming active regions and dummy active regions within the substrate between the equidistant spaced shallow trench isolation regions. Forming sources and drains within the active regions. Providing wordlines and source lines extending in a first direction and bitlines extending in a second direction. Forming contact regions over the dummy active regions for strapping the wordlines and the source lines to the bitlines.
    Type: Grant
    Filed: March 4, 2006
    Date of Patent: February 19, 2008
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Sung Mun Jung, Ching Dong Wang, Louis Yoke Leng Lim, Swee Tuck Woo, Donghua Liu, Xiaoyu Chen
  • Memory device with non-orthogonal word and bit lines
    Publication number: 20080035956
    Abstract: A semiconductor memory device such as a dynamic random access memory (DRAM) has substantially non-orthogonal word and bit lines. For a given memory cell size, such as six square lithographic features (6F2), the non-orthogonal layout allows for larger-pitch word and bit lines when compared to the orthogonal layout of the word and bit lines.
    Type: Application
    Filed: August 14, 2006
    Publication date: February 14, 2008
    Inventor: H. Montgomery Manning
  • NANO-electronic memory array
    Patent number: 7330369
    Abstract: Systems and methods are disclosed to process a semiconductor substrate by fabricating a first layer on the substrate using semiconductor fabrication techniques; fabricating a second layer above the first layer having one or more NANO-bonding areas; self-assemblying one or more NANO-elements; and bonding the NANO-elements to the NANO-bonding areas.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: February 12, 2008
    Inventor: Bao Tran
  • Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
    Patent number: 7326634
    Abstract: A method of a bulk tri-gate transistor having stained enhanced mobility and its method of fabrication. The present invention is a nonplanar transistor having a strained enhanced mobility and its method of fabrication. The transistor has a semiconductor body formed on a semiconductor substrate wherein the semiconductor body has a top surface on laterally opposite sidewalls. A semiconductor capping layer is formed on the top surface and on the sidewalls of the semiconductor body. A gate dielectric layer is formed on the semiconductor capping layer on the top surface of a semiconductor body and is formed on the capping layer on the sidewalls of the semiconductor body. A gate electrode having a pair of laterally opposite sidewalls is formed on and around the gate dielectric layer. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.
    Type: Grant
    Filed: March 22, 2005
    Date of Patent: February 5, 2008
    Assignee: Intel Corporation
    Inventors: Nick Lindert, Stephen M. Cea
  • Method and apparatus for coupling to a common line in an array
    Patent number: 7323726
    Abstract: A method and apparatus for coupling to a common line in an array. Gate structures of an integrated circuit are formed. Source and drain regions adjacent to the gate structures are implanted. A source contact from a metal Vss line to a source region is formed. Dopants of the source and drain regions diffuse laterally to overlap. The overlapping diffusion regions conduct and couple the drain region to a source region. Beneficially, the drain region is coupled to the metal Vss line. As a beneficial result, source contacts may be formed along a line of drain contacts in associated rows of drain contacts, and coupled to a common source line via the novel overlapping diffusion regions. A plurality of word lines may be formed without any bending in the word lines to accommodate source contacts that are larger than the source line.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: January 29, 2008
    Assignee: Spansion LLC
    Inventors: Kuo-Tung Chang, Yu Sun
  • Input display with embedded photo sensor
    Patent number: 7323718
    Abstract: A readout pixel of an input display is provided. The readout pixel includes the fundamental elements as the normal pixel, and further includes a photo sensing element with a second switching element and a third switching element for generating a photo signal. The second switching element includes a second gate electrode connecting to a gate line, a second drain electrode, and a second source electrode connecting to a readout line. The third switching element includes a third gate electrode and a third drain electrode both connecting to a reference voltage, and a third source electrode connecting to the second drain electrode.
    Type: Grant
    Filed: May 2, 2006
    Date of Patent: January 29, 2008
    Assignee: Hannstar Display Corporation
    Inventors: Po-Yang Chen, Po-Sheng Shih, Wei-Chou Chen, Kei-Hsiung Yang
  • Flat panel display
    Patent number: 7321135
    Abstract: The claimed invention is directed to a flat panel display having R, G, and B unit pixels. At least one of the R, G, and B unit pixels includes at least two or more transistors, each having source and drain regions. At least one drain region in the source/drain regions of at least one transistor in the transistors has a resistance value different from a resistance value of at least a drain region of the other transistor. The difference in resistance values may be accomplished by doping each drain region with a different concentration of dopant or by shaping each drain region differently.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: January 22, 2008
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Sang-Il Park, Jae Bon Koo
  • Transistor layout for standard cell with optimized mechanical stress effect
    Patent number: 7321139
    Abstract: A layout for a transistor in a standard cell is disclosed. The layout for a transistor includes an active region with at least one portion having a first edge and at least one portion having a second edge all perpendicular to a channel of the transistor; and a gate placed on top of the active region with a distance from an edge of the gate to the first edge being shorter than a distance from the edge of the gate to the second edge of the active region, wherein the active region is of a non-rectangular shape.
    Type: Grant
    Filed: May 26, 2006
    Date of Patent: January 22, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mi-Chang Chang, Liang-Kai Han, Huan-Tsung Huang, Wen-Jya Liang, Li-Chun Tien
  • Integrated circuit structures for increasing resistance to single event upset
    Patent number: 7319253
    Abstract: A configuration memory cell (“CRAM”) for a field programmable gate array (“FPGA”) integrated circuit (“IC”) device is given increased resistance to single event upset (“SEU”). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size of the remainder of the gate structure. Part of the enlarged gate structure is located capacitively adjacent to an N-well region of the IC, and another part is located capacitively adjacent to a P-well region of the IC. This arrangement gives the input node increased capacitance to resist SEU, regardless of the logical level of the input node. The invention is also applicable to any node of any type of memory cell for which increased resistance to SEU is desired.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: January 15, 2008
    Assignee: Altera Corporation
    Inventors: Lakhbeer S Sidhu, Irfan Rahim, Jeffrey Watt, John E Turner
  • Array substrate for liquid crystal display device and method of manufacturing the same
    Publication number: 20080001175
    Abstract: An array substrate for a liquid crystal display device includes a substrate, a gate line over the substrate, a data line crossing the gate line to define a pixel region and including a transparent conductive layer and an opaque conductive layer, a data pad at one end of the data line and including a transparent conductive layer, a thin film transistor connected to the gate line and the data line and including a gate electrode, an active layer, an ohmic contact layer, a buffer metallic layer, a source electrode and a drain electrode, and a pixel electrode in the pixel region and connected to the thin film transistor, the pixel electrode including a transparent conductive layer.
    Type: Application
    Filed: December 28, 2006
    Publication date: January 3, 2008
    Inventors: Hyo-Uk Kim, Byung-chul Ahn, Byoung-Ho Lim
  • METHODS OF FORMING A SEMICONDUCTOR DEVICE INCLUDING BURIED BIT LINES
    Publication number: 20070295995
    Abstract: A method of forming a buried interconnection includes removing a semiconductor substrate to form a groove in the semiconductor substrate. A metal layer is formed on inner walls of the groove using an electroless deposition technique. A silicidation process is applied to the substrate having the metal layer, thereby forming a metal silicide layer on the inner walls of the groove.
    Type: Application
    Filed: June 4, 2007
    Publication date: December 27, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Ho Yun, Byung-Hee Kim, Dae-Yong Kim, Hyun-Su Kim, Eun-Ji Jung, Eun-Ok Lee
  • Circuit layout structure
    Patent number: 7307294
    Abstract: Main-transistors M1 and M2 are divided into sub-transistors that are arrayed in a matrix with four rows and four columns to form four cells so that each of the cells is formed of four of the sub-transistors that have a common center. This can realize a layout configuration that is as good in matching of the main-transistors M1 and M2 as a four-segment layout scheme and takes small pattern area.
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: December 11, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Sachin Aggarwal
  • Alignment insensitive D-cache cell
    Patent number: 7304352
    Abstract: A D-Cache SRAM cell having a modified design in schematic and layout that exhibits increased symmetry from the circuit schematic and the physical cell layout perspectives. That is, the SRAM cell includes two read ports and minimizes asymmetry by provisioning one read port on a true side and one on the complement side. Asymmetry is additionally minimized in layout as cross coupling on both the true and complement sides rises up one level by providing from the local interconnect level a via connection to a M1 or metallization level. Moreover, the distance between the local interconnect (MC) and the gate conductor structure (PC) has been enlarged and equalized for each of the pFETs in the cross-latched SRAM cell. As a result, the SRAM cell has been rendered insensitive to overlay (local interconnect processing too close) by maximizing this MC-PC distance.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: December 4, 2007
    Assignee: International Business Machines Corporation
    Inventors: K. Paul Muller, Kevin A. Batson, Michael J. Lee
  • Circuit layout for improved performance while preserving or improving density
    Patent number: 7301182
    Abstract: In one embodiment, a circuit may be formed by forming at least one bent-gate output stage transistor and at least one bent-gate input stage transistor. The bent-gate output stage transistor may be electrically isolated from an input to the bent-gate input stage transistor by forming at least one bent-gate grounded-gate transistor between the bent-gate output stage transistor and the input to the bent-gate input stage transistor.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: November 27, 2007
    Assignee: Lattice Semiconductor Corporation
    Inventors: Larry Metzger, Kerry Ilgenstein, Sunil Mehta
  • DISPLAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME AND DISPLAY APPARATUS HAVING THE SAME
    Publication number: 20070262347
    Abstract: A display substrate having a high aperture ratio includes gate and source metallic patterns, first and second gate insulating layers, and a pixel electrode. The gate metallic pattern includes a gate line, a gate electrode and a first storage electrode. The first gate insulating layer covers at least one of the gate electrode and the first storage electrode. The second gate insulating layer is patterned to expose the first gate insulating layer on the first storage electrode. The source metallic pattern includes a second storage electrode contacting a source line and the first gate insulating layer on the first storage electrode. The pixel electrode is electrically connected to a switching element. Therefore, the display substrate having the high aperture ratio may be obtained to enhance luminance of a display image.
    Type: Application
    Filed: April 9, 2007
    Publication date: November 15, 2007
    Inventor: Chun-Gi You
  • Method of forming a phase change material layer, method of forming a phase change memory device using the same, and a phase change memory device so formed
    Publication number: 20070246743
    Abstract: A method of forming a phase change material layer includes preparing a substrate having an insulator and a conductor, loading the substrate into a process housing, injecting a deposition gas into the process housing to selectively form a phase change material layer on an exposed surface of the conductor, and unloading the substrate from the process housing, wherein a lifetime of the deposition gas in the process housing is shorter than a time the deposition gas takes to react by thermal energy.
    Type: Application
    Filed: April 20, 2007
    Publication date: October 25, 2007
    Inventors: Sung-Lae Cho, Choong-Man Lee, Jin- Il Lee, Sang-Wook Lim, Hye-Young Park, Young-Lim Park
  • Unit cell of semiconductor integrated circuit and wiring method and wiring program using unit cell
    Publication number: 20070228419
    Abstract: A unit cell of a semiconductor integrated circuit capable of improving wiring efficiency in layout of a functional circuit block or the like using a unit cell, and a wiring method and wiring program using the unit cell are provided. In a unit cell, auxiliary power wiring regions are formed with reference to grids that exist from a cell edge every basic cell width in the X-direction. Input signal terminals and an output signal terminal are each arranged so as to include at least one wiring connecting portion outside the auxiliary power wiring regions. This makes it possible to wire wiring other than signal wiring in the auxiliary power wiring region. When a functional circuit block is constructed by arranging unit cells in a matrix, auxiliary power wiring regions are formed at a pitch of the basic cell width, through the functional circuit block in the Y-direction.
    Type: Application
    Filed: August 23, 2006
    Publication date: October 4, 2007
    Inventor: Masaki Komaki
  • Semiconductor integrated circuit device and dummy pattern arrangement method
    Publication number: 20070221957
    Abstract: A semiconductor integrated circuit device according to an embodiment of the present invention includes a functional circuit region including a functional circuit, a dummy region formed in a region other than the functional circuit region, and plural dummy MOSFETs formed in a dummy region and having a dummy gate electrode on a dummy diffusion layer 12, the plural dummy MOSFETs being arranged such that date rates of the dummy diffusion layer and dummy gate electrode are kept constant in a predetermined section.
    Type: Application
    Filed: February 28, 2007
    Publication date: September 27, 2007
    Inventors: Hiroyasu Kitajima, Hiroshi Furuta, Toshikatsu Jinbo
  • Electronic device, method for producing the same, and communication apparatus including the same
    Publication number: 20070200146
    Abstract: An electronic device according to the present invention includes a functional element acting as a predetermined circuit packaged using a resin member. The electronic device comprises a wiring substrate having a wiring member for electric connection with an external circuit; the functional element mounted on one main surface of the wiring substrate so as to be electrically connected to the wiring member; and the resin member provided on the one main surface of the wiring substrate having the functional element, so as to package the functional element. The resin member includes a filler formed of a magnetic material.
    Type: Application
    Filed: February 27, 2007
    Publication date: August 30, 2007
    Inventors: Keiji Onishi, Hiroshi Nakatsuka, Takehiko Yamakawa
  • Active matrix substrate, electro-optic device and electronic apparatus
    Publication number: 20070194349
    Abstract: An active matrix substrate comprises a substrate, a first electrode disposed on one surface side of the substrate, an insulating film, a plurality of second electrodes, and a plurality of switching elements. The insulating film is disposed between the first electrode and the plurality of second electrodes, and each of the plurality of second electrodes is electrically connected to one of the plurality of switching elements.
    Type: Application
    Filed: February 21, 2007
    Publication date: August 23, 2007
    Applicant: Seiko Epson Corporation
    Inventors: Takeo Kawase, Tsutomu Miyamoto, Soichi Moriya
  • Integrated capacitor for RF applications with Ta adhesion layer
    Patent number: 7253522
    Abstract: A precision RF passive component including: a silicon substrate; a first dielectric layer deposited above the silicon substrate; a first metal layer formed above the first dielectric layer; a second dielectric layer formed above the first metal layer; and a second metal layer formed above the second dielectric layer. In one embodiment a passivation layer is added above the second metal layer. In an exemplary embodiment the first metal layer includes a first adhesion layer, a metal sub-layer, and a second adhesion layer; and the second dielectric layer includes a first diffusion barrier layer, a dielectric sub-layer second diffusion barrier. In an exemplary embodiment, the metal sub-layer includes copper. In another exemplary embodiment the dielectric sub-layer includes SiO2 or Si3N4 between diffusion barrier layers including SiN.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: August 7, 2007
    Assignee: AVX Israel, Ltd.
    Inventors: Elad Irron, Eitan Avni
  • Electronic device and method for designing the same
    Patent number: 7250644
    Abstract: The electronic device includes a plurality of layout regions each including a plurality of patterns defined by a buried structure buried in a substrate. For each of the layout regions, in each of the layout regions, the minimum space between the patterns, and a maximum area percentage allowed for the patterns in the layout region are defined based on a size of the layout region. In larger one of the layout regions, the minimum space between the patterns in the region is set larger.
    Type: Grant
    Filed: March 17, 2005
    Date of Patent: July 31, 2007
    Assignee: Fujitsu Limited
    Inventor: Naoki Idani
  • High-voltage device structure
    Patent number: 7244975
    Abstract: A high-voltage device structure includes a high-voltage device disposed on a semiconductor substrate. The semiconductor includes an active region and an isolation region, and the high-voltage device is disposed in the active region. The high-voltage device structure includes a source diffusion region of a first conductive type, a drain region of the first conductive type, and a gate longer than the source diffusion region and the drain diffusion region so as to form spare regions on both sides of the gate. The isolation region is outside the active region and surrounds the active region. In the isolation region, an isolation ion implantation region of a second conductive type and an extended ion implantation region are disposed to prevent parasitic current from being generating between the source diffusion region and the drain diffusion region.
    Type: Grant
    Filed: July 5, 2005
    Date of Patent: July 17, 2007
    Assignee: United Microelectronics Corp.
    Inventors: Anchor Chen, Chih-Hung Lin, Hwi-Huang Chen, Jih-Wei Liou, Chin-Hung Liu, Ming-Tsung Tung, Chien-Ming Lin, Jung-Ching Chen
  • Gate Capacitor Having Horizontal Structure and Method for Manufacturing the Same
    Publication number: 20070152241
    Abstract: A gate capacitor having a horizontal structure and a method for manufacturing the same is provided. The gate capacitor having a horizontal structure can be formed on a semiconductor substrate and used as a MOS transistor. The gate capacitor includes at least two adjacent gate electrodes and a capacitor dielectric layer filled between the two gate electrodes. In this case, insulating spacers can be formed at a sidewall of the gate electrodes in which the capacitor dielectric layer is not formed. As the gate capacitors can be used as a MOS transistor, a gate insulating layer can be formed between the two gate electrodes and the semiconductor substrate.
    Type: Application
    Filed: December 19, 2006
    Publication date: July 5, 2007
    Inventor: Jung Ho Ahn
  • SRAM device having high aspect ratio cell boundary
    Patent number: 7233032
    Abstract: A static random access memory (SRAM) device including a substrate and an SRAM unit cell. The substrate includes an n-doped region interposing first and second p-doped regions. The SRAM unit cell includes: (1) a first pass-gate transistor and a first pull-down transistor located at least partially over the first p-doped region; (2) first and second pull-up transistors located at least partially over the n-doped region; and (3) a second pass-gate transistor, a second pull-down transistor, and first and second read port transistors, all located at least partially over the second p-doped region. A boundary of the SRAM unit cell comprises first and second primary dimensions having an aspect ratio of at least about 3.2.
    Type: Grant
    Filed: April 5, 2004
    Date of Patent: June 19, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Semiconductor device and cell
    Patent number: 7227202
    Abstract: A cell 100 includes three wiring layers (a gate electrode layer, a source/drain electrode layer and a terminal layer) on a semiconductor substrate including transistors formed thereon. One of the wiring layers (the terminal layer) in which input terminals 151 and output terminals 152 for connecting the cell to another cell are formed includes a power supply line passing region 153 through which a power supply line for supplying a power supply voltage and a ground voltage from an external power supply to the transistors in the cell can be provided.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: June 5, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Keisuke Kishishita
  • Method and apparatus for coupling to a source line in a memory device
    Patent number: 7217964
    Abstract: A method and apparatus for coupling to a source line. Specifically, embodiments of the present invention disclose a memory device comprising an array of flash memory cells with a source line connection that facilitates straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column implanted with n-type dopants is also isolated between an adjoining pair of STI regions. The source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions in the array. A source contact is coupled to the source column for providing electrical coupling with the plurality of source regions. The source contact is located along a row of drain contacts that are coupled to drain regions of a row of memory cells.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: May 15, 2007
    Assignee: Spansion LLC
    Inventors: Richard M. Fastow, Kuo-Tung Chang
  • Self-protecting transistor array
    Patent number: 7217966
    Abstract: A transistor array is self-protected from an electrostatic discharge (ESD) event which can cause localized ESD damage by integrating an ESD protection device into the transistor array. The ESD protection device operates as a transistor during normal operating conditions, and provides a low-resistance current path during an ESD event.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: May 15, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Peter J. Hopper, Philipp Lindorfer
  • Wire mesh patterns for semiconductor devices
    Patent number: 7217962
    Abstract: Different patterns of interconnects for connecting wells in a semiconductor device are described. For example, a semiconductor device may include n-wells and p-wells arrayed in rows and columns that lie on a rectilinear grid. Electrically conductive interconnects link at least some of the wells. The interconnects are arranged as a mesh having openings that are substantially rectangular in shape.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: May 15, 2007
    Assignee: Transmeta Corporation
    Inventor: Robert Paul Masleid
  • Transistor
    Patent number: 7211840
    Abstract: A transistor and a semiconductor integrated circuit with a reduced layout area. Area reduction of a transistor is realized by arranging contacts at higher density. Specifically, in a transistor including a pair of impurity regions and a gate electrode 604 sandwiched therebetween, one of the impurity regions has respective contact holes (a first contact hole 601 and a second contact hole 602) and the other impurity region has a contact hole (a third contact hole 603), and contacts of the contact holes 601 to 603 or regions 605 to 607 each including a margin for a contact are arranged so as to be a triangular lattice except for the gate electrode 604.
    Type: Grant
    Filed: October 19, 2004
    Date of Patent: May 1, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kiyoshi Kato