Abstract: A plurality of integrated circuit features are provided in the context of an array of memory cells including a plurality of word lines and a plurality of bit lines. Each memory cell includes a floating body or is volatile memory. The aforementioned features may include, among others, an option whereby the foregoing bit lines may be situated below a channel region of corresponding memory cells, etc.

Abstract: In one embodiment of the present invention, a method for connecting a plurality of bit lines to sense circuitry comprises providing a plurality of bit lines extending from a memory array in a first metal layer. The plurality of bit lines are separated from each other by an average spacing x in a first region of the first metal layer. The method further comprises elevating a portion of the plurality of bit lines into a second metal layer overlying the first metal layer. The elevated bit lines are separated from each other by an average spacing y in the second metal layer, with y>x. The method further comprises extending a portion of the plurality of bit lines into a second region of the first metal layer. The extended bit lines are separated from each other by an average spacing z in the second region of the first metal layer, with z>x. The method further comprises connecting a bit line in the second metal layer and a bit line in the first metal layer to the sense circuitry.

Abstract: A gate driver-on-array structure for using in a display panel including first conductive patterns, semiconductor patterns, second conductive patterns, third conductive patterns, first electrode line, and first connectors is provided. The first conductive patterns, the second conductive patterns, the semiconductor patterns and the third conductive patterns together form a plurality of thin film transistors. The first electrode line is located at a side of the first conductive patterns and spaced from the first conductive patterns by a first distance. The first connectors are connected to the corresponding first conductive patterns and the first electrode line.

Abstract: An integrated circuit is described. The integrated circuit may have: an active area line formed of a material of a semiconductor substrate with a first longitudinal direction parallel to an upper surface of the semiconductor substrate; wherein the active area line has at least one form-supporting element extending in a second longitudinal direction parallel to the upper surface of the semiconductor substrate; and wherein the second longitudinal direction is arranged with regard to the first longitudinal direction in an angle unequal to 0 degree and unequal to 180 degree.

Abstract: A semiconductor apparatus includes an internal circuit, a CMOS composed of a P-channel MOS transistor with a source connected to a high-potential power supply line and a gate connected to the internal circuit, and an N-channel MOS transistor with a source connected to a low-potential power supply line and a gate connected to the internal circuit, an output terminal connected to a drain of the P-channel MOS transistor and a drain of the N-channel MOS transistor and a protection transistor with a source and a gate connected to one power supply line of the high-potential power supply line and the low-potential power supply line and a drain connected to the output terminal, a conductivity type of the protection transistor being the same as a conductivity type of one MOS transistor of the P-channel MOS transistor and the N-channel MOS transistor, the source of the one MOS transistor being connected to the one power supply line.

Abstract: A substrate is levitated a first distance over a mother substrate when a first group of Coulomb islands are charged. A second group of Coulomb islands are charged and increase a separation to a second distance. When the magnitude of the potential of all Coulomb islands is decreased, the separation decreases from the second distance to the first distance. All potentials associated with the Coulomb islands have decreased yet the distance of separation equals to the first distance. Increasing the number of Coulomb islands in a substrate can reduce the magnitude of potentials applied to the Coulomb islands thereby reducing the concern of voltage stress.

Abstract: A nano device includes an array of cells disposed in rows and columns and constructed over a substrate, and an optical circuit disposed over the substrate, wherein the optical circuit is formed by nano elements in a self-assembled process.

Abstract: A semiconductor device includes: an isolation region formed in a semiconductor substrate; an active region surrounded by the isolation region; and a first gate electrode formed on the isolation region and the active region and including a first region on the isolation region. The first region has a pattern width in a gate length direction larger than a pattern width of the first gate electrode on the active region. The first region includes a part having a film thickness different from a film thickness of the first gate electrode on the active region.

Abstract: A three-dimensional nonvolatile memory device includes: a plurality of channel structures extending in parallel in a first direction and comprising a plurality of channel layers that are alternatively stacked with a plurality of interlayer insulating layers over a substrate; a plurality of memory cells stacked along sidewalls of the channel structures and arranged in the first direction and a second direction crossing the first direction; and a plurality of word lines extending in parallel in the second direction and connected to the memory cells arranged in the second direction.

Abstract: Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column is implanted with n-type dopants after the formation of a tunnel oxide layer and a first polysilicon layer. The implanted source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions associated with memory cells in the array. A source contact is coupled to the implanted source column for providing electrical coupling with the plurality of source regions. The source contact is collinear with a row of drain contacts that are coupled to drain regions associated with a row of memory cells. The arrangement of source contacts collinear with the row of drain contacts allows for straight word line formation.

Abstract: A method for manufacturing a nanotube non-volatile memory cell is proposed. The method includes the steps of: forming a source electrode and a drain electrode, forming a nanotube implementing a conduction channel between the source electrode and the drain electrode, forming an insulated floating gate for storing electric charges by passivating conductive nanoparticles with passivation molecules and arranging a disposition of passivated conductive nanoparticles on the nanotube, the conductive nanoparticles being adapted to store the electric charges and being insulated by the passivation molecules from the nanotube, and forming a control gate coupled with the channel.

Abstract: A semiconductor integrated circuit is provided which entails no increase in the correction time of OPC and in which non-uniformity in the gate lengths due to the optical proximity effects is surely suppressed. A plurality of standard cells (C1, C2, C3, . . . ), each including gates G extended in the vertical direction, are aligned in the transverse direction to form a standard cell row. A plurality of the standard cell rows are located side by side in the vertical direction to form a standard cell group. Each of the standard cell rows has a terminal standard cell Ce at least one end of the standard cell row. The terminal standard cell Ce includes two or more supplementary gates, each of which is any of a dummy gate and a gate of an inactive transistor.

Abstract: Disclosed are embodiments of semiconductor structure and a method of forming the semiconductor structure that simultaneously maximizes device density and avoids contacted-gate pitch and fin pitch mismatch, when multiple parallel angled fins are formed within a limited area on a substrate and then traversed by multiple parallel gates (e.g., in the case of stacked, chevron-configured, CMOS devices). This is accomplished by using, not a minimum lithographic fin pitch, but rather by using a fin pitch that is calculated as a function of a pre-selected contacted-gate pitch, a pre-selected fin angle and a pre-selected periodic pattern for positioning the fins relative to the gates within the limited area. Thus, the disclosed structure and method allow for the conversion of a semiconductor product design layout with multiple, stacked, planar FETs in a given area into a semiconductor product design layout with multiple, stacked, chevron-configured, non-planar FETs in the same area.

Abstract: An array substrate for a liquid crystal display device includes a substrate, a gate line over the substrate, a data line crossing the gate line to define a pixel region and including a transparent conductive layer and an opaque conductive layer, a data pad at one end of the data line and including a transparent conductive layer, a thin film transistor connected to the gate line and the data line and including a gate electrode, an active layer, an ohmic contact layer, a buffer metallic layer, a source electrode and a drain electrode, and a pixel electrode in the pixel region and connected to the thin film transistor, the pixel electrode including a transparent conductive layer.

Abstract: A contact layout structure includes a substrate having at least a first region defined thereon, plural sets of first contact layouts positioned along a predetermined direction in the first region, and a plurality of second contact layouts positioned in the first region. Each set of the first contact layout has two square contact units and two adjacent rectangle contact units positioned between the two square contact units.

Abstract: A static random access memory cell includes a metal hi-k layer; a poly-SiON gate stack over the metal hi-k layer; a plurality of inverters disposed within the poly-SiON gate stack; and a plurality of field effect transistors placed in the metal hi-k layer.

Abstract: A transistor fabricated on a semiconductor substrate includes a source and a drain in the substrate; a gate on the substrate, the gate being insulated from the substrate by gate dielectric; barrier layers covering two sides of the gate and the gate dielectric; spacers of high-k material covering the barrier layers; and nitride spacers covering the spacers of high-k material. The spacers of high-k material significantly increase the node capacitance of the transistor and therefore reduce the transistor's soft error rate.

Abstract: A circuit having a fingerprint for identification of a particular instantiation of the circuit. The circuit comprises a plurality of digital circuits or gates, the plurality digital circuits or gates each having an analog input and wherein each of the digital circuits or gates has at least one functional state wherein the corresponding digital circuit or gate performs an intended digital function and at least one other state wherein the intended digital function is not performed. Each of the digital circuits or gates is responsive to a configuration voltage applied to its analog input for controlling whether or not the digital circuit or gate performs its intended digital function and each of the digital circuits or gates transitioning between its functional state and its at least one other state when the configuration voltage equals a boundary voltage.

Abstract: A semiconductor device having a first semiconductor region and second semiconductor region including impurities formed on an insulating layer formed on a semiconductor substrate, an insulator formed between the first semiconductor region and the second semiconductor region, a first impurity diffusion control film formed on the first semiconductor region and a second impurity diffusion control film formed on the second semiconductor region, a channel layer formed on the first impurity diffusion control film and second impurity diffusion film to cross at right angles with a direction where the first semiconductor region and the second semiconductor region are extended, a gate insulating film formed on the channel layer and a gate electrode formed on the gate insulating layer.

Abstract: The present invention proposes a dummy metal fill structure which makes it possible to reduce variations in transistor characteristics as much as possible even if mask misalignment occurs, as well as to ensure the intended planarizing effect of the metal CMP process. The dummy metal fill formed above the gate electrode extends in the gate length direction with both ends thereof protruding from a region corresponding to the gate electrode. Even if a mask for forming a wiring layer is misaligned and the position of the dummy metal fill is misaligned from an intended position, the shape of the dummy metal fill within a region of the gate electrode is kept symmetric with respect to the center of the gate electrode.

Abstract: A semiconductor integrated circuit having a first p-type MOS transistor; a first n-type MOS transistor; a second p-type MOS transistors; a and second n-type MOS transistors having fourth gate electrodes disposed so as to be adjacent to the second diffused regions of the first n-type MOS transistor. The semiconductor integrated circuit further having an absolute value of a threshold voltage of the second p-type MOS transistor being higher than an absolute value of a threshold voltage of the first p-type MOS transistor, and an absolute value of a threshold voltage of the second n-type MOS transistor being higher than an absolute value of a threshold voltage of the first n-type MOS transistor.

Abstract: An integrated circuit including an array of memory cells and method. In one embodiment, each memory cell includes a resistively switching memory element and a selection diode for selecting one cell from the plurality of memory cells. The memory element is coupled with its top to a first selection line and with its bottom side to the selection diode, the diode further being coupled to the bottom side of a second selection line.

Abstract: Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compressive) to channel regions of the transistors. The covering step may include covering the first and second transistors with a first electrically insulating layer having a sufficiently high internal stress characteristic to impart a net tensile (or compressive) stress in a channel region of the first transistor and covering the second and third transistors with a second electrically insulating layer having a sufficiently high internal stress characteristic to impart a net compressive (or tensile) stress in a channel region of the third transistor. A step may then performed to selectively remove a first portion of the second electrically insulating layer extending opposite a gate electrode of the second transistor.

Abstract: A semiconductor integrated circuit is provided which entails no increase in the correction time of OPC and in which non-uniformity in the gate lengths due to the optical proximity effects is surely suppressed. A plurality of standard cells (C1, C2, C3, . . . ), each including gates G extended in the vertical direction, are aligned in the transverse direction to form a standard cell row. A plurality of the standard cell rows are located side by side in the vertical direction to form a standard cell group. Each of the standard cell rows has a terminal standard cell Ce at least one end of the standard cell row. The terminal standard cell Ce includes two or more supplementary gates, each of which is any of a dummy gate and a gate of an inactive transistor.

Abstract: The invention includes methods of forming electrically conductive material between line constructions associated with a peripheral region or a pitch region of a semiconductor substrate. The electrically conductive material can be incorporated into an electrically-grounded shield, and/or can be configured to create a magnetic field bias. Also, the conductive material can have electrically isolated segments that are utilized as electrical jumpers for connecting circuit elements. The invention also includes semiconductor constructions comprising the electrically conductive material between line constructions associated with one or both of the pitch region and the peripheral region.

Abstract: Methods of forming semiconductor devices that include one or more arrays of memory devices in a three-dimensional arrangement, such as those that include forming a conductive contact in a dielectric material overlying a memory array, wherein a wafer bonding and cleaving process may be utilized to provide a foundation material for forming another memory array having an active region in electrical contact with the conductive contact. Additionally, the conductive contact may be formed in a donor wafer, which in turn may be bonded to a dielectric material overlying a memory array using another wafer bonding process. Novel semiconductor devices and structures including the same may be formed using such methods, for example.

Abstract: A cell array includes a semiconductor substrate including an active region comprising a first region, a second region, and a transition region, the second region being separated from the first region by the transition region, wherein a top surface of the second region is at a different level than a top surface of the first region. The cell array also includes a plurality of word lines crossing over the first region. The cell array also includes a selection line crossing over the active region, wherein at least a portion of the selection line is located over the transition region.

Abstract: A multi-bit memory cell stores information corresponding to a high resistive state and multiple other resistive states lower than the high resistive state. A resistance of a memory element within the multi-bit memory cell switches from the high resistive state to one of the other multiple resistive states by applying a corresponding current to the memory element.

Abstract: A non-volatile memory device integrated on a semiconductor substrate of a first type of conductivity comprising a matrix of non-volatile memory cells organized in rows, called word lines, and columns, called bit lines, the device including a plurality of equidistantly spaced active areas with the non-volatile memory cells integrated therein, each non-volatile memory cell having a source region, a drain region and a floating gate electrode coupled to a control gate electrode, a group of the memory cells sharing a common source line of a second type of conductivity, an implanted region of said second type of conductivity inside at least one of the plurality of active areas in electric contact with the common source line, and at least one source contact aligned and in electric contact with the implanted region.

Abstract: A non-volatile memory array includes a multiplicity of memory cells, each of whose area is less than 4 F2 per cell (where F is a minimum feature size), and periphery elements to control the memory cells. The present invention also includes a non-volatile memory array which includes word lines and bit lines generally perpendicular to the word lines, with a word line pitch of less than 2 F. In one embodiment, the word lines are made of polysilicon spacers.

Abstract: A method of making a semiconductor device includes forming at least one device layer over a substrate, forming a plurality of spaced apart first features over the device layer, where each three adjacent first features form an equilateral triangle, forming sidewall spacers on the first features, filling a space between the sidewall spacers with a plurality of filler features, selectively removing the sidewall spacers, and etching the at least one device layer using at least the plurality of filler features as a mask. A device contains a plurality of bottom electrodes located over a substrate, a plurality of spaced apart pillars over the plurality of bottom electrodes, and a plurality of upper electrodes contacting the plurality of pillars. Each three adjacent pillars form an equilateral triangle, and each pillar comprises a semiconductor device.

Abstract: A method of a bulk tri-gate transistor having stained enhanced mobility and its method of fabrication. The present invention is a nonplanar transistor having a strained enhanced mobility and its method of fabrication. The transistor has a semiconductor body formed on a semiconductor substrate wherein the semiconductor body has a top surface on laterally opposite sidewalls. A semiconductor capping layer is formed on the top surface and on the sidewalls of the semiconductor body. A gate dielectric layer is formed on the semiconductor capping layer on the top surface of a semiconductor body and is formed on the capping layer on the sidewalls of the semiconductor body. A gate electrode having a pair of laterally opposite sidewalls is formed on and around the gate dielectric layer. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Abstract: Some embodiments include cross-point memory structures. The structures may include a line of first electrode material extending along a first horizontal direction, a multi-sided container of access device materials over the first electrode material, a memory element material within the multi-sided container, and a line of second electrode material over the memory element material and extending along a second horizontal direction that is orthogonal to the first horizontal direction. Some embodiments include methods of forming memory arrays. The methods may include forming a memory cell stack over a first electrode material, and then patterning the first electrode material and the memory cell stack into a first set of spaced lines extending along a first horizontal direction. Spaced lines of second electrode material may be formed over the first set of spaced lines, and may extend along a second horizontal direction that is orthogonal to the first horizontal direction.

Abstract: A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).

Abstract: A layout structure of a Sub-Word Line Driver (SWD) and a forming method thereof. A layout structure of an SWD may include first through fourth metal-oxide-semiconductor (MOS) transistors. The layout structure may include a first area including an active area of the first MOS transistor, wherein a gate-poly (GP) of the first MOS transistor may be disposed in a predefined direction over a portion of the first area. The layout structure may also include a second area including an active area of the second through fourth MOS transistors. Each GP of the second through fourth MOS transistors may be disposed in parallel to each other. The GP of the first MOS transistor disposed in the predefined direction may be substantially perpendicular to each GP of the second through fourth MOS transistors. The layout structure of an SWD can improve a driving capability without increasing an area of the chip.

Abstract: A gate driver-on-array structure integrated in a display panel includes a bar-like conductive layer, a semiconductor layer, first conductive patterns, second conductive patterns, a first electrode line and a second electrode line. The bar-like conductive layer has a plurality of regions. The semiconductor layer is disposed within the regions of the bar-like conductive layer. The first conductive patterns and the second conductive patterns are disposed on the semiconductor layer and located within the regions. The bar-like conductive layer is located between the first electrode line and the second electrode line. The first electrode line and the second electrode line are respectively spaced from the bar-like conductive layer by a first distance and a second distance. The GOA structure has first connectors connected to the corresponding first conductive patterns and the first electrode line, and second connectors connected to the second conductive patterns and the second electrode line.

Abstract: A nonvolatile semiconductor memory of an aspect of the present invention comprises a plurality of memory cell transistors which are connected in series to one another with a first gate spacing, every two adjacent transistors of the memory cell transistors sharing a source/drain diffusion layer, and a first select gate transistor which shares a source/drain diffusion layer with an endmost memory cell transistor that is located at one end of the series connection of the memory cell transistors and is adjacent to that memory cell transistor with a second gate spacing. The second gate spacing is set larger than the first gate spacing and the source/drain diffusion layer shared by the endmost memory cell transistor and the first select gate transistor contains a region which is higher in impurity concentration than the source/drain diffusion layer shared by two adjacent memory cell transistors.

Abstract: A three-dimensional non-volatile memory system is disclosed including a memory array utilizing shared pillar structures for memory cell formation. A shared pillar structure includes two non-volatile storage elements. A first end surface of each pillar contacts one array line from a first set of array lines and a second end surface of each pillar contacts two array lines from a second set of array lines that is vertically separated from the first set of array lines. Each pillar includes a first subset of layers that are divided into portions for the individual storage elements in the pillar. Each pillar includes a second subset of layers that is shared between both non-volatile storage elements formed in the pillar. The individual storage elements each include a steering element and a state change element.

Abstract: An integrated circuit includes a substrate including active circuitry fabricated on the substrate and a cross-point memory array formed above the substrate. The cross-point memory array can include conductive array lines arranged in different directions, and re-writable memory cells. Further, the integrated circuit can also include a memory access circuit configured to perform data operations on the cross-point memory array. The integrated circuit can include a cross-point memory array interface layer positioned between the substrate and the cross-point array and including conductive paths configured to electrically couple portions of the memory access circuit with a subset of the conductive array lines. At least one layer of cross-point memory arrays can be formed over the substrate. The memory cells can be two-terminal memory cells that store data as a plurality of conductivity profiles (e.g., resistive states) that can be non-destructively determined by applying a read voltage across the terminals.

Abstract: A semiconductor device is provided. An isolation structure is formed in a substrate to define a first and a second active region, and a channel active region therebetween. A field implant region is formed below a portion of the isolation structure around the first, second, and channel active regions. A channel active region includes two first sides defining a channel width. The distance from each first side to a second side of a neighboring field implant region is d1. The shortest distance from a third side of each first or second active region to an extension line of each second side of the field implant region is d2. R=d1/d2, where 0.15?R?0.85. A gate structure covers the channel active region and extends over a portion of the isolation structure. Source/drain doped regions are formed in the first and the second active regions.

Abstract: A semiconductor device is provided. The semiconductor device includes a first gate line, a second gate line, a first contact electrode, first dummy gates, a second gate pad, and a second contact electrode. The first gate line is formed on a semiconductor substrate and the second gate line of a spacer shape is formed on the sidewalls of the first gate line with a thin insulating layer interposed therebetween. The first contact electrode is vertically connected with the first gate line. The first dummy gates are formed in array spaced a predetermined interval from the first gate line on the semiconductor substrate. The second gate pad of a spacer shape is formed on the sidewalls of the first dummy gates with a thin insulating layer interposed therebetween. The second gate pad is connected to the second gate line and is also gap-filled between the first dummy gates. The second contact electrode is vertically connected with the second gate pad.

Abstract: A multiple-gate transistor structure which includes a substrate, source and drain islands formed in a portion of the substrate, a fin formed of a semi-conducting material that has a top surface and two sidewall surfaces, a gate dielectric layer overlying the fin, and a gate electrode wrapping around the fin on the top surface and the two sidewall surfaces separating source and drain islands. In an alternate embodiment, a substrate that has a depression of an undercut or a notch in a top surface of the substrate is utilized.

Abstract: Provided is a semiconductor device comprising: a plurality of bit line patterns; a plurality of pad patterns that are respectively connected to the plurality of bit line patterns; and at least one contact that is formed on each of the plurality of pad patterns, wherein the pitch of the plurality of pad patterns is greater than the pitch of the plurality of bit line patterns. The bit line patterns may be formed using a double patterning technology (DPT).

Abstract: A semiconductor device manufacturing method includes forming a first insulating film on a semiconductor substrate, forming a first conductor film on the first insulating film, forming a second insulating film on the first conductor film, forming a first line-and-space pattern by etching the second insulating film and the first conductor film, forming a etched region etched into a second line-and-space pattern perpendicular to the first line-and-space pattern by etching the second insulating film, the first conductor film, the first insulating film, and the semiconductor substrate, burying a third insulating film in the etched region, removing the second insulating film, forming a fourth insulating film on the first conductor film and the third insulating film, forming a second conductor film on the fourth insulating film, and forming a third line-and-space pattern parallel to the first line-and-space pattern by etching the second conductor film.

Abstract: A unit cell for an integrated circuit includes a first conductive type active region and a second conductive type active region which extend in a first direction. Each of the active regions has first and second ends. The first end of the second conductive type active region opposes the second end of the first conductive type active region. A poly-silicon pattern extends in the first direction across the first conductive type active region and second conductive type active region. A first contact region is adjacent the first end of the first conductive type active region in the first direction. A second contact region is adjacent the second end of the second conductive type active region in the first direction.

Abstract: An integrated circuit including a memory cell array comprises transistors being arranged along parallel active area lines, bitlines, the bitlines being arranged so that an individual one intersects a plurality of the active area lines to form bitline-contacts, respectively, the bitlines being formed as wiggled lines, wordlines being arranged so that an individual one of the wordlines intersects a plurality of the active area lines, and an individual one of the wordlines intersects a plurality of the bitlines, wherein neighboring bitline-contacts, each of which is connected to one of the active area lines, are connected with different bitlines.

Abstract: A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.

Abstract: Semiconductor devices whose current characteristics can be prevented from varying even if a phase shift mask is used for patterning gate electrodes of MISFETs, and a manufacturing method thereof are disclosed. According to one aspect of the present invention, there is provided a semiconductor device comprising a first transistor including a first gate electrode provided above a semiconductor substrate, and a first source and a first drain provided in the semiconductor substrate, a second transistor arranged to be adjacent to the first transistor, and including a second gate electrode provided above the semiconductor substrate in parallel with the first gate electrode, and a second source and a second drain provided in the semiconductor substrate, and a third gate electrode provided between the first transistor and the second transistor and in parallel with the first and second gate electrodes.

Abstract: A NAND-type flash memory device including selection transistors is provided. The device includes first and second impurity regions formed in a semiconductor substrate, and first and second selection gate patterns disposed on the semiconductor substrate between the first and second impurity regions. The first and second selection gate patterns are disposed adjacent to the first and second impurity regions, respectively. A plurality of cell gate patterns are disposed between the first and second selection gate patterns. A first anti-punchthrough impurity region that surrounds the first impurity region is provided in the semiconductor substrate. The first anti-punchthrough impurity region overlaps with a first edge of the first selection gate pattern adjacent to the first impurity region. A second anti-punchthrough impurity region that surrounds the second impurity region is provided in the semiconductor substrate.

Abstract: A semiconductor memory device is constructed to include a memory cell formed by a plurality of transistors, wherein each of gate wiring layers of all of the transistors forming the memory cell is arranged to extend in one direction.