Abstract: A solid-state imaging device is provided in which noise to an image signal is restrained and miniaturization is facilitated in a peripheral circuit formation region. A solid-state imaging device includes a pixel formation region 4 and a peripheral circuit formation region 20 formed in the same semiconductor substrate; in the peripheral circuit formation region 20 a first element isolation portion is formed of an element isolation layer 21 in which an insulation layer is buried in a semiconductor substrate 10; in the pixel formation region 4 a second element isolation portion made of an element isolation region 11 formed inside the semiconductor substrate 10 and an element isolation layer 12 projecting upward from the semiconductor substrate 10 is formed; and a photoelectric conversion element 16 (14, 15) is formed extending to a position under the element isolation layer 12 of the second element isolation portion.

Abstract: In a solid-state imaging apparatus, a plurality of pixel units are arranged, the pixel units including (i) a photoelectric conversion element formed above a semiconductor substrate and (ii) a color filter layer formed above the photoelectric conversion element. In each color filter layer, the central part is formed thicker than the peripheral part.

Abstract: There is provided a high quality liquid crystal panel having a thickness with high accuracy, which is designed, without using a particulate spacer, within a free range in accordance with characteristics of a used liquid crystal and a driving method, and is also provided a method of fabricating the same. The shape of a spacer for keeping a substrate interval constant is made such that it is a columnar shape, a radius R of curvature is 2 ?m or less, a height H is 0.5 ?m to 10 ?m, a diameter is 20 ?m or less, and an angle ? is 65° to 115°. By doing so, it is possible to prevent the lowering of an opening rate and the lowering of light leakage due to orientation disturbance.

Abstract: The invention provides a solid-state imaging device including a pixel array having a plurality of pixels arranged in a matrix. The pixels can each include a photo diode that generates carriers depending on the intensity of incident light, an accumulation region that accumulates the generated holes, an output transistor that outputs a signal according to threshold voltage that changes depending on the number of carriers accumulated in the accumulation region, and a clear transistor that discharges carriers accumulated in the accumulation region. One of semiconductor regions that form the photo diode and the accumulation region function as a source region of the clear transistor. In the accumulation period, if generated carriers spill from the source region of the clear transistor in the accumulation period, the clear transistor discharges the spilled carriers through a channel of the clear transistor in order to prevent the spilled carriers from entering the accumulation region of adjacent pixels.

Abstract: An imaging area is provided on a surface of a semiconductor substrate, and light-receiving portions and transfer channels are provided in the imaging area. A group of transfer electrodes extends in a direction crossing the transfer channels on the imaging area. A group of transfer signal lines, which are provided for every transfer signal of each phase along the periphery of the imaging area on the semiconductor substrate, is included. A transfer signal line connected to a transfer electrode having a large surface area on the transfer channel, of the group of the transfer electrodes, has an electrical resistance smaller than that of a transfer signal line connected to a transfer electrode having a small surface area on the transfer channel in the group of the transfer electrodes.

Abstract: Embodiments of the invention provide an image sensor having an improved dynamic range. A pixel cell comprises at least one transistor structure. The transistor structure comprises at least one semiconductor channel region, at least one gate for controlling the channel region, and first and second leads respectively coupled to a source region on one side of the at least one channel region and a drain region on an opposite side of the at least one channel region. The transistor structure has at least two threshold voltages associated with the at least one channel region, and an I-V characteristic of the transistor structure is determined at least in part by the threshold voltages.

Abstract: An imager, an image sensor included in the imager and a method of fabricating the image sensor are provided. The image sensor having a substrate with front and back sides to produce image data, includes a transparent conductive coating arranged on the back side of the substrate, a first well region of a first conductive type having first and second opposite sides, the first side being arranged adjacent with the front side of the image sensor; and a second well region of a second conductive type, different from the first conductive type and having a deep well region provided adjacent with the second side of the first well region, the transparent conductive coating configured to develop or to receive a first potential and the first well region configured to receive a second potential to substantially deplete a region between the transparent conductive coating and the first well region.

Abstract: Regions of an integrated circuit are isolated by a structure that includes at least one isolating trench on the periphery of an active area. The trench is deep, extending at least about 0.5 ?m into the substrate. The isolating structure prevents photons and electrons originating in peripheral circuitry from reaching the active area. Where the substrate has a heavily-doped lower layer and an upper layer on it, the trench can extend through the upper layer to the lower layer. A thermal oxide can be grown on the trench walls. A liner can also be deposited on the sidewalls of each trench. A fill material having a high-extinction coefficient is then deposited over the liner. The liner can also be light absorbent so that both the liner and fill material block photons.

Abstract: A grey tone display and a driving method are described. The display comprises a light influencing layer, an electrode pad located adjacent to the layer at one side of the layer in order to define a pixel in the layer, an n-channel field effect transistors connected to the electrode pad at its source terminal, a p-channel field effect transistors connected to the electrode pad at its source terminal, a first control line connected to the drain terminal of the n-channel field effect transistor, a second control line connected to the drain terminal of the p-channel field effect transistor, a third control line connected to the gate terminals of the n-channel field effect transistor and the p-channel field effect transistor, and a control circuit for supplying control signals to the first, second and third control lines. By this configuration, the voltage of the electrode pad can be arbitrarily controlled by adjusting the input level at the gate terminals.

Abstract: Embodiments of the invention provide an image sensor having an improved dynamic range. A pixel cell comprises at least one transistor structure. The transistor structure comprises at least one semiconductor channel region, at least one gate for controlling the channel region, and first and second leads respectively coupled to a source region on one side of the at least one channel region and a drain region on an opposite side of the at least one channel region. The transistor structure has at least two threshold voltages associated with the at least one channel region, and an I-V characteristic of the transistor structure is determined at least in part by the threshold voltages.

Abstract: An image pickup apparatus includes plural light receiving areas arranged two-dimensionally and a vertical scanning circuit composed of plural unit circuit stages arranged in the vertical direction and a horizontal scanning circuit composed of plural unit circuit stages arranged in the horizontal direction for selecting and reading the plural light receiving areas in succession and in which the vertical scanning circuit and the horizontal scanning circuit are arranged in spaces between the light receiving areas. A crossing area of the vertical scanning circuit and the horizontal scanning circuit, in a space between the light receiving areas, is divided into two areas, and at least a unit circuit of the horizontal scanning circuit is provided in one of the two areas while at least a unit circuit of the vertical scanning circuit is provided in the other of the two areas.

Abstract: Photodiodes and methods of fabricating photodiodes are provided. For example, a method of fabricating a photodiode includes forming a buried layer of a first conductive type on a semiconductor substrate and forming a first intrinsic capping epitaxial layer on the buried layer. A first intrinsic epitaxial layer of the first conductive type is formed on the first intrinsic capping epitaxial layer. A first junction region of the first conductive type is formed in the first intrinsic epitaxial layer. A second intrinsic epitaxial layer of the second conductive type is formed on the first junction region and the first intrinsic epitaxial layer. A second intrinsic capping epitaxial layer is formed on the second intrinsic epitaxial layer. A second junction region of the first conductive type is formed such that the second junction region passes through the second intrinsic capping epitaxial layer and the second intrinsic epitaxial layer. The second junction region contacts the first junction region.

Abstract: Failure light emission of an EL element due to failure film formation of an organic EL material in an electrode hole 46 is improved. By forming the organic EL material after embedding an insulator in an electrode hole 46 on a pixel electrode and forming a protective portion 41b, failure film formation in the electrode hole 46 can be prevented. This can prevent concentration of electric current due to a short circuit between a cathode and an anode of the EL element, and can prevent failure light emission of an EL layer.

Abstract: The present invention discloses a multi-passivation layer structure for organic thin-film transistors and a method for fabricating the same by spin coating, inject printing, screen printing and micro-contact on organic thin-film transistors. The multi-passivation layer structure for organic thin-film transistors, comprising: a substrate; a gate layer formed on the substrate; an insulator layer formed on the substrate and the gate layer; an electrode layer formed on the insulator layer; a semiconductor layer formed on the insulator layer and the electrode layer; and a passivation layer formed on the semiconductor layer and the electrode layer, thereby forming a multi-passivation layer structure for organic thin-film transistors.

Abstract: A photoelectric conversion device has pixels arranged in an array. Each pixel includes a light receiving region for converting light to signal charges and an insulation film formed on a surface of the light receiving region. Each pixel further includes transistors, including an amplifying transistor for amplifying the signal charges. A reflection prevention film is provided that has a refractive index higher than that of the insulation film and is arranged above the light receiving region, with the insulation film disposed between the reflection prevention film and the light receiving region. Film thicknesses of the insulation film and gate insulation films of the transistors are different from each other.

Abstract: A solid-state image sensor comprises a semiconductor substrate of a first conductivity type having a color pixel region and a black pixel region; a first well of the first conductivity type formed in the color pixel region; a second well of the first conductivity type formed in the black pixel region; a third well of a second conductivity type formed, surrounding the second well and isolating the second well from the rest region of the semiconductor substrate; a color pixel formed in the first well in the color pixel region and including a first photodiode and a first read transistor for reading a signal generated by the first photodiode; and a black pixel formed in the second well in the black pixel region and including a second photodiode and a second read transistor for reading a signal generated by the second photodiode. The first well includes a first buried impurity doped layer of the first conductivity type formed in a bottom thereof in a region where the first read transistor is formed.

Abstract: An active pixel includes a a photosensitive element formed in a semiconductor substrate. A transfer transistor is formed between the photosensitive element and a floating diffusion and selectively operative to transfer a signal from the photosensitive element to the floating diffusion. The floating diffusion is formed from an n-type implant with a dosage in the range of 5e13 to 5e14 ions/cm2. Finally, an amplification transistor is controlled by the floating diffusion.

Abstract: A pixel cell comprises a photo-conversion device for generating charge and a gate controlled charge storage region for storing photo-generated charge under control of a control gate. The charge storage region can be a single CCD stage having a buried channel to obtain efficient charge transfer and low charge loss. The charge storage region is adjacent to a gate of a transistor. The transistor gate is adjacent to the photo-conversion device and, in conjunction with the control gate, transfers photo-generated charge from the photo-conversion device to the charge storage region.

Abstract: The present invention relates to a semiconductor device formed in a self-light-emitting apparatus having a substrate and a plurality of self-light-emitting elements formed on the substrate, the semiconductor device being used to drive one of the self-light-emitting elements. The semiconductor device includes an active layer of semiconductor material, in which a source region and a drain region are formed, a source electrode having a multi-layered structure including an upper side layer of titanium nitride and a lower side layer of a high melting point metal having low resistance, the source electrode electrically being coupled to the source region, a drain electrode having a multi-layered structure including an upper side layer of titan nitride and a lower side layer of a high melting point metal having low resistance, the source electrode electrically being coupled to said drain region, an insulation layer formed on the active layer, and a gate electrode formed on the insulation layer.

Abstract: A pixel circuit with a dual gate PMOS is formed by forming two P+ regions in an N? well. The N? well is in a P? type substrate. The two P+ regions form the source and drain of a PMOS transistor. The PMOS transistors formed within the N? well will not affect the collection of the photo-generated charge as long as the source and drain potentials of the PMOS transistors are set at a lower potential than the N? well potential so that they remain reverse biased with respect to the N? well. One of the P+ regions used to form the source and drain regions can be used to reset the pixel after it has been read in preparation for the next cycle of accumulating photo-generated charge. The N? well forms a second gate for the dual gate PMOS transistor since the potential of the N? well 12 affects the conductivity of the channel of the PMOS transistor. The addition of two NMOS transistors enables the readout signal to be stored at the gate of one of the NMOS transistors thereby making a snapshot imager possible.

Abstract: A memory embedded semiconductor device according to the present invention has a memory region having a memory transistor and a logic region having a logic transistor each provided in a common semiconductor substrate. The logic transistor has a gate electrode provided on the semiconductor substrate and source/drain diffusion layers formed in the semiconductor substrate each having a silicide film formed thereon. On the other hand, the memory transistor has a gate electrode provided on the semiconductor substrate and source/drain diffusion layers formed in the semiconductor substrate each having a silicide film formed thereon to be thinner than the silicide film formed on each of the source/drain diffusion layers of the logic transistor.

Abstract: A semiconductor light-receiving device includes: a substrate that has a first surface and a second surface facing each other; a first semiconductor layer that is formed on the first surface of the substrate and includes at least one semiconductor layer of a first conductivity type; a light absorption layer that is formed on the first semiconductor layer and generates carriers in accordance with incident light; a second semiconductor layer that is formed on the light absorption layer and includes at least one semiconductor layer of a second conductivity type; a first electrode part that is electrically connected to the first semiconductor layer and applies a first potential thereto; a second electrode part that is electrically connected to the second semiconductor layer and applies a second potential thereto; and a third semiconductor layer of the second conductivity type that is interposed between the first surface of the substrate and the first semiconductor layer.

Abstract: The loss of photogenerated electrons to surface electron-hole recombination sites is minimized by utilizing a first p-type surface region to form a depletion region that functions as a first barrier that repels photogenerated electrons from the surface recombination sites, and a second p-type surface region that provides a substantial change in the dopant concentration.

Abstract: An interline transfer type image sensing device that can be operated at high speed and with low image smear is described. The device incorporates a refractory metal layer which is used for both a light shield over the vertical charge transfer region and as a wiring layer for low resistance strapping of poly crystalline silicon (polysilicon) gate electrodes for the vertical charge transfer region. Plugs provided by a separate metallization layer connect the refractory light shield to the polysilicon gate electrode. These plugs allow high temperature processing after refractory light shield patterning for improved sensor performance without degradation of the polysilicon gate electrode or the refractory lightshield layer.

Abstract: An image sensor includes a semi-conducting substrate having a photo-sensitive region and doping for forming a path to a charge-to-voltage mechanism; a dielectric spanning the substrate; and a semi-conducting layer, which is less than approximately 1 micrometer, spanning the dielectric which contains electrodes and circuit elements that control flow of charge.

Abstract: Each transfer electrode of a charge transfer unit is made of a main electrode layer and subsidiary electrode layers formed on the side walls of the main electrode layer. The upper surfaces of the transfer electrodes are flush with each other. A charge coupled device having a practically sufficient charge transfer efficiency can be provided. If this charge coupled device is used for an image pickup apparatus, the distance between photoelectric conversion elements and micro lenses can be shortened.

Abstract: A method for improving the efficiency for an optoelectronic device, such as semiconductor lasers, Superluminescence Light Emitting Diodes (SLDs), Gain Chips, optical amplifiers is disclosed, see FIG. 4B. In accordance with the principles of the invention, at least one blocking layer (70) is interposed at the interface between materials composing the device. The at least one blocking layers creates a barrier that prevents the leakage of electrons from a device active region contained in the waveguide region, to a device clad region (66). In one aspect of the invention, a blocking layer (70) is formed at the junction of the semiconductor materials having different types of conductivity. The blocking layer prevents electrons from entering the material of a different polarity. In another aspect of the invention, a low-doped or undoped region (64) is positioned adjacent to the blocking layer (70) to decrease optical losses.

Abstract: A method of controlling a MOS-type photodetector includes transferring electrical charge between a photodiode (12) and a sensing node (3) via a transfer transistor. The electrical potential of the sensing node (3) takes an extreme value when a maximum quantity of electrical charge is stored on the sensing node (3). During the electrical charge transfer, an electrical potential is applied to the gate electrode of a transfer transistor in such a way that the electrical potential of the channel (2) of the transfer transistor is brought to a value equal to the extreme value of the electrical potential of the sensing node (3) multiplied by a number greater than or equal to unity.

Abstract: A photoelectric conversion apparatus includes a photoelectric conversion element and a logarithmic conversion unit for converting a signal from the photoelectric conversion element to a logarithmically compressed voltage by means of a diode characteristic of p-n junction. The p-n junction in the logarithmic conversion unit is composed of any two terminals of the emitter, the base and the collector of the bipolar transistor, and a residual terminal of the transistor is connected to a semiconductor substrate.

Abstract: A semiconductor device including a substrate having a plurality of image sensing elements formed therein, a plurality of spaced apart color filters overlying the substrate and a light blocking material interposed between adjacent spaced apart color filters.

Abstract: A spatial light modulator contains a substrate (90), a plurality of overlying liquid-crystal cells (202), a plurality of respectively corresponding transistors (204), an electron-beam system (400 and 500), and a control component (203). Each transistor is in electrical communication with the corresponding liquid-crystal cell. The electron-beam system bombards each transistor with electrons that cause it to be selectively in (i) a non-conductive condition in which its channel-region electric field is substantially insufficient for conduction or (ii) a conductive condition in which its channel-region electric field is sufficient for at least partial conduction. During selected time periods when a transistor is in its conductive condition, the control component provides the transistor with a control signal that results in the polarization direction of specified light being selectively rotated in passing through the corresponding liquid-crystal cell.

Abstract: A photoelectric conversion device capable of improving an open-circuit voltage is obtained. In this photoelectric conversion device, many of crystal grains contained in a third non-single-crystalline semiconductor layer have major axes substantially perpendicular to a main surface of a substrate on an interfacial portion between at least either a first non-single-crystalline semiconductor layer or a second non-single-crystalline semiconductor layer and the third non-single-crystalline semiconductor layer, and many of crystal grains contained in either semiconductor layer have major axes substantially parallel to the main surface of the substrate on the aforementioned interfacial portion.

Abstract: An image sensor is disclosed where individual photo diodes of the respective unit cells separated by an element isolating layer are physically integrated into a single large scale pixel formed widely on a semiconductor substrate so as to hold the pixels in common. A pixel separation pattern is additionally formed on a portion of the large scale photo diode formed so as to electrically separate them. An optimization of the light receiving area of the photo diode, a minimization of the intrusion area of an element isolating layer, and so on are achieved, so that the photo diode recovers an area occupied by an intrusion of the element isolating layer, thus maximizing the light receiving area in an optimal scale and easily preventing electrical impacts between the respective unit cells.

Abstract: An imager having reduced floating diffusion leakage and a mechanism for improving the storing of collected charge is described. A polysilicon contact is provided between a floating diffusion region and a gate of a source follower output transistor, with the contact also electrically connected to a storage capacitor. The storage capacitor provides additional charge storage capacity to the floating diffusion region. In addition, an associated reset transistor has different dopant characteristics in the source and drain regions. The floating diffusion region may be used in the pixels of a CMOS imager or in the output stage of a CCD imager.

Abstract: A method of fabricating a high-sensitivity image sensor is disclosed. The disclosed method comprises: etching a predetermined region of active silicon and a buried oxide layer by using a mask over an SOI substrate to expose an N-type silicon substrate; implanting P-type ions into the exposed N-type silicon substrate to form a P-type region; forming crossed active silicon by patterning the rest of the active silicon not etched while the active silicon is etched to expose the N-type silicon substrate; implanting P-type ions into first two predetermined regions facing each other of the crossed active silicon to form P-type regions; implanting N-type ions into second two predetermined regions facing each other except for the P-type regions of the crossed active silicon to form N-type regions; forming a gate oxide layer and a gate electrode on the crossed active silicon; and forming a connection part to connect the P-type region of the crossed active silicon to the P-type region of the silicon substrate.

Abstract: The invention provides a solid-state imaging device that include a pixel array where a plurality of unit pixels each including a photo diode and an insulated gate field effect transistor for detecting a photocharge are arranged, and a control circuit that controls the operation of the pixel array. The control circuit can apply a predetermined voltage to a source diffused region of the insulated gate field effect transistor and applies voltage by which a channel region becomes a conductive state to a gate electrode to bias a junction region formed of a semiconductor substrate of a first conductivity type and a semiconductor layer of a second conductivity type in a forward direction so as to accumulate a predetermined amount of the charge of a predetermined conductivity type in an accumulation region, and thereby causing the charge of a predetermined conductivity type accumulated in the accumulation region to be discharged.

Abstract: A method and corresponding device for determining the phase and/or amplitude data of an electromagnetic wave. The method comprises the steps: beaming an electromagnetic wave onto the surface of at least one pixel having at least two light sensitive modulation gates Gam, Gbm and associated accumulation gates Ga and Gb, applying modulation voltages Uam(t) and Ubm(t) to gates Gam and Gbm, applying a direct voltage to accumulation gates Ga and Gb, wherein the charge carriers produced in modulation gates Gam and Gbm by the incident electromagnetic wave being subjected to a potential gradient due to the modulation voltages Uam(t) and Ubm(t), thereby drifting to the corresponding accumulation gate Ga or Gb, and forwarding the charge carriers to evaluation electronics. A plurality of corresponding pixels can be assembled to form an array.

Abstract: A self testing CMOS imager chip includes a controller which outputs a sewer signal, a dump signal, a collect signal, and a read signal, and a pixel array connected to the controller including a plurality of pixels arranged in an array of rows and columns, each pixel having a collect gate disposed adjacent a collect well for receiving a charge in response to application of the collect signal to the collect gate, a sewer for injecting a charge into the collect well in response to the concurrent application of the sewer signal to the sewer and the collect signal to the collect well, a read gate disposed adjacent a read well for receiving the injected charge from the collect well in response to application of the read signal to the read gate and the absence of the collect signal at the collect gate, and a transistor having a gate coupled to the read well, a source for receiving the read signal, and a drain coupled to an output node connected to the controller.

Abstract: A solid-state imaging device includes: a plurality of N-type photodiode regions formed inside a P-type well; a gate electrode having one edge being positioned adjacent to each of the photodiode regions; a N-type drain region positioned adjacent to the other edge of the gate electrode; an element-isolating portion having a STI structure, and a gate oxide film having a thickness of not more than 10 nm. One edge of the gate electrode overlaps the photodiode region.

Abstract: The solid-state imaging device according to the present invention comprises: a plurality of light-sensitive elements 1 arranged in a matrix form at regular spacings in a photoreceiving region provided on a semiconductor substrate; a plurality of detecting electrodes provided on the semiconductor substrate corresponding to the plurality of the light-sensitive elements for detecting an electrical charge generated by each light-sensitive element; a light-shielding film 58 coating the plurality of detecting electrodes and having an aperture 65 over each light-sensitive element; and a plurality of reflecting walls 62, which are formed in a grid pattern over the light-shielding film so as to partition the apertures individually over the respective light-sensitive elements, for reflecting a portion of light entering the semiconductor substrate from above onto the aperture on each light-sensitive element.

Abstract: The present invention provides a CMOS imager with a reset scheme, by which a CMOS imager generates a sub-kTC noise so that read noise does not depend on the sense node capacitance. By using a column feedback circuit, reset noise can be suppressed to a negligible amount so that photogate APS or CCD-like circuits can achieve noise performance to very efficient value. This scheme allows increasing sense node capacitance without increasing the noise and also achieves a large full-well value without sacrificing read noise performance. The feedback circuit in one of the embodiment of the present invention is located at the column side of the circuit. This design provides a minimal change to the pixel. As a result quantum efficiency or pixel size is not compromised. The present invention allows a CMOS imager to capture scene with high intra-scene contracts under low illumination with high dynamic range.

Abstract: Three-dimensional structures of arbitrary shape are fabricated on the surface of a substrate through a series of processing steps wherein a monolithic structure is fabricated in successive layers. A first layer of photoresist material is spun onto a substrate surface and is exposed in a desired pattern corresponding to the shape of a final structure, at a corresponding cross-sectional level in the structure. The layer is not developed after exposure; instead, a second layer of photoresist material is deposited and is also exposed in a desired pattern. Subsequent layers are spun onto the top surface of prior layers and exposed, and upon completion of the succession of layers each defining corresponding levels of the desired structure, the layers are all developed at the same time leaving the three-dimensional structure.

Abstract: A SnO2 ISFET device and manufacturing method thereof. The present invention prepares SnO2 as the detection membrane of an ISFET by sol-gel technology to obtain a SnO2 ISFET. The present invention also measures the current-voltage curve for different pH and temperatures by a current measuring system. The temperature parameter of the SnO2 ISFET is calculated according to the relationship between the current-voltage curve and temperature. In addition, the drift rate of the SnO2 ISFET for different pH and hysteresis width of the SnO2 ISFET for different pH loop are calculated by a constant voltage/current circuit and a voltage-time recorder to measure the gate voltage of the SnO2 ISFET.

Abstract: Image sensors and methods of fabricating the same are provided. The image sensor includes a blocking pattern disposed on photodiodes. The blocking pattern is formed of insulation material having a metal diffusion coefficient which is lower than a silicon oxide diffusion coefficient. Therefore, dark defects of the image sensor are reduced. In addition, the image sensor includes a color-ratio control layer. The color ratio control layer controls color ratios between the sensitivities to blue, green and red. As a result, color distinction of the picture that is embodied by the image sensor can be improved.

Abstract: Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.

Abstract: There is provided an amplifying solid-state image pickup device capable of improving S/N and maintaining a charge-voltage conversion efficiency high. In the amplifying solid-state image pickup device, signal charges of a plurality of photodiodes 1 are added up on an input side of a switched capacitor amplification part 20 via the transfer transistors 2.

Abstract: A programmable sensor array (1) having a plurality of programmable cells (2). Each of the cells (2) comprises a programmable module (4) and a sensor element(6) operatively coupled to the programmable module. There is also an analogue module (8), typically an analogue to digital converter, that provides the operatively coupling of the sensor element (6) to the programmable module (4). The sensor element (6), programmable module (4) and analogue module (8) are in a stacked relationship.

Abstract: In thin film transistors (TFTs) having an active layer of crystalline silicon adapted for mass production, a catalytic element is introduced into doped regions of an amorphous silicon film by ion implantation or other means. This film is crystallized at a temperature below the strain point of the glass substrate. Further, a gate insulating film and a gate electrode are formed. Impurities are introduced by a self-aligning process. Then, the laminate is annealed below the strain point of the substrate to activate the dopant impurities. On the other hand, Neckel or other element is also used as a catalytic element for promoting crystallization of an amorphous silicon film. First, this catalytic element is applied in contact with the surface of the amorphous silicon film. The film is heated at 450 to 650° C. to create crystal nuclei. The film is further heated at a higher temperature to grow the crystal grains. In this way, a crystalline silicon film having improved crystallinity is formed.

Abstract: Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.

Abstract: A plurality of apertures is formed in at least one first insulating layer disposed over a sensor formed in a semiconductor substrate. A second insulating layer is disposed over the at least one first insulating layer and the plurality of apertures in the at least one first insulating layer. The apertures form hollow regions in the at least one first insulating layer over the sensor, allowing more light or energy to pass through the at least one first insulating layer to the sensor, and increasing the sensitivity of the sensor.