Abstract: A semiconductor device may include: a semiconductor substrate comprising a plurality of active regions and a device isolation region for isolating the plurality of active regions; and a conductive shield pillar formed in the device isolation region and connected to the semiconductor substrate. Each of the active regions may include: a body portion formed in the substrate; a pillar floating from the body portion and positioned over the body portion; a side portion provided over a side surface of the pillar and connected to the body portion; and an embedded spacer positioned between the side portion and the pillar, the pillar may be coupled to the substrate through the side portion.

Abstract: A transistor includes a substrate having an upper surface, a fin structure protruding from the upper surface of the substrate, an isolation structure over the upper surface of the substrate and surrounding a lower portion of the fin structure, and a first doped region at least partially embedded in an upper portion of the fin structure. The fin structure extends along a first direction. The first doped region has a first type doping different from that of the fin structure.

Abstract: There are disclosed herein various implementations of an insulated-gate bipolar transistor (IGBT) having a deep superjunction structure. Such an IGBT includes a drift region having a first conductivity type situated over a collector having a second conductivity type. The IGBT also includes a gate trench extending through a base having the second conductivity type into the drift region. In addition, the IGBT includes a deep superjunction structure situated under the gate trench. The deep superjunction structure includes one or more first conductivity regions having the first conductivity type and two or more second conductivity region having the second conductivity type, the one or more first conductivity regions and the two or more second conductivity regions configured to substantially charge-balance the deep superjunction structure.

Abstract: A semiconductor device including a semiconductor substrate including a plurality of active regions and a device isolation region for isolating the plurality of active regions; and a buried bit line and a buried gate electrode which are formed in the semiconductor substrate. The device isolation region includes a first device isolation region extending in a first direction and a second device isolation region extending in a second direction crossing with the first direction and having a shield pillar formed therein.

Abstract: A semiconductor device includes a stacked body including a plurality of electrode layers stacked with an insulator interposed; a columnar portion provided in the stacked body and extending in a stacking direction of the electrode layers; and a first separation region provided in the stacked body and extending in a first direction. The stacked body includes a memory cell array and a staircase portion arranged in the first direction, the memory cell array including memory cells provided along the columnar portion, and the staircase portion including a plurality of terraces arranged along the first direction. The first separation region includes a first portion and a second portion in the staircase portion, the first portion having a first width in a second direction crossing the first direction, and the second portion having a second width in the second direction. The second width is narrower than the first width.

Abstract: A method for forming an interconnect structure including: forming a semiconductor structure on a semiconductor substrate, the semiconductor structure having a gate structure, shallow trench isolation and a source/drain; forming a dielectric over the semiconductor structure; removing the dielectric adjacent to the gate structure to create a trench adjacent to the gate structure; depositing a metal into and filling the trench adjacent to the gate structure to form a metal line; etching the metal line to form a gap in the metal line so as to create segments of the metal line; and filling the gap with a dielectric material to enable tip-to-tip spacing between the segments of the metal line.

Abstract: A method for forming a semiconductor device comprises forming a fin in a bulk semiconductor substrate and depositing a first insulator layer over portions of the bulk semiconductor substrate adjacent to the fin. The method further includes removing portions of the first insulator layer to reduce a thickness of the first insulator layer and expose a sidewall of the fin. An etch stop layer is deposited on the first insulator layer. A gate stack is formed over a channel region of the fin and over portions of the etch stop layer. A portion of the bulk semiconductor substrate is removed to expose portions of the etch stop layer and the fin, and a second insulator layer is deposited over exposed portions of the fin and the etch stop layer.

Abstract: Devices and methods for forming a device are disclosed. The method includes providing a crystalline-on-insulator substrate having a bulk substrate and a surface substrate separated by a buried insulator layer. The surface substrate is defined with a device region. A transistor having a gate is formed in the device region. A first diffusion region is formed adjacent to a first side of the gate and a second diffusion region is formed adjacent to and displaced away from a second side of the gate. At least a first drift isolation region is formed in the surface substrate adjacent to and underlaps the second side of the gate. A drift well is formed in the surface substrate encompassing the first drift isolation region. A device isolation region surrounding the device region is formed in the surface substrate. The device isolation region includes a second depth which is deeper than a first depth of the first drift isolation region.

Abstract: A silicon carbide semiconductor device includes trenches formed in a lattice shape on the surface of a silicon carbide substrate on which a semiconductor layer is formed, and gate electrodes formed inside of the trenches via a gate insulating film. The depth of the trenches is smaller in a portion where the trenches are crossingly formed than in a portion where the trenches are formed in parallel to each other. Consequently, the silicon carbide semiconductor device is obtained that increases a withstand voltage between the gate electrodes and corresponding drain electrodes on the semiconductor device rear surface to prevent dielectric breakdown and, at the same time, has a large area of the gate electrodes, high channel density per unit area, and low ON resistance.

Abstract: A semiconductor device includes channel layers arranged in a first direction and a second direction intersecting the first direction; stacked insulating layers surrounding sidewalls of the channel layers; stacked gate electrodes interposed between the insulating layers, the gate electrodes respectively surrounding the channel layers; and stacked gate lines interposed between the insulating layers, the gate lines electrically connecting the gate electrodes to each other.

Abstract: A memory device includes: a substrate; a channel layer on the substrate, in which the channel layer includes a T-shape having a horizontal portion with a first end and a second end and a vertical portion having a third end; a gate structure on a side of the vertical portion; an oxide-nitride-oxide (ONO) layer between the gate structure and the vertical portion; a source region on the first end of the horizontal portion; and a drain region on the third end of the vertical portion.

Abstract: A semiconductor device includes a fin-shaped semiconductor layer, a first insulating film formed around the fin-shaped semiconductor layer, a first metal film formed around the first insulating film, a pillar-shaped semiconductor layer formed on the fin-shaped semiconductor layer, a gate insulating film formed around the pillar-shaped semiconductor layer, a gate electrode formed around the gate insulating film and made of a third metal, a gate line connected to the gate electrode, a second insulating film formed around a sidewall of an upper portion of the pillar-shaped semiconductor layer, and a second metal film formed around the second insulating film. The upper portion of the pillar-shaped semiconductor layer and the second metal film are connected to each other, and an upper portion of the fin-shaped semiconductor layer and the first metal film are connected to each other.

Abstract: A laterally diffused metal-oxide-semiconductor (LDMOS) transistor with a vertical channel region is provided. A first semiconductor region is formed over a second semiconductor region and with a first doping type. The second semiconductor region has a second doping type different than the first doping type. A gate electrode is formed laterally adjacent to the first semiconductor region and extending along a side boundary of the first semiconductor region. A first source/drain contact region and a second source/drain contact region are respectively formed on opposite sides of the gate electrode and with the second doping type. The first source/drain contact region is further formed over the first semiconductor region. A method for manufacturing the LDMOS transistor is also provided.

Abstract: The present invention concerns a semiconductor tunneling Field-Effect device including a source, a drain, at least one elongated semiconductor structure extending in an elongated direction, a first gate, and a second gate. The first gate has a length extending in said elongated direction and is positioned on a first side of the at least one elongated semiconductor structure, and the second gate has a length extending in said elongated direction and is positioned on a second opposing side of the at least one elongated semiconductor structure. The first and second gates extend along the first and second sides of the at least one elongated semiconductor structure to define an overlap zone sandwiched between the first gate and the second gate, said overlap zone extending the full length of the first and/or second gate along the at least one elongated semiconductor structure.

Abstract: A vertical-channel semiconductor device having a buried bit line is disclosed. The vertical-channel semiconductor device enables an active pillar including a vertical channel region to be separate from a substrate, couples the active pillar to the substrate using a body-tied structure, and prevents a floating body effect from occurring therein. In addition, the vertical-channel semiconductor device includes an air gap between buried bit lines to reduce parasitic capacitance between the bit lines.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a self-aligned deep contact for a vertical field effect transistor (VFET) and methods of manufacture. The structure includes a plurality of fin structures, a first contact landing on a substrate material between a first set of fin structures of the plurality of fin structures, sidewalls of the first contact being in direct contact with an insulator material of the first set of the fin structures, and a second contact landing on a work function material between a second set of fin structures of the plurality of fin structures, sidewalls of the second contact being in direct contact with the insulator material of the second set of the fin structures.

Abstract: A semiconductor device includes a first n? type layer and a second n? type layer that are sequentially disposed on a first surface of an n+ type silicon carbide substrate; a first trench and a second trench that are disposed at the second n? type layer and are spaced apart from each other; a p type region surrounding a lateral surface and a lower surface of the first trench; an n+ type region disposed on the p type region and the second n? type layer; a gate insulating layer disposed in the second trench; a gate electrode disposed on the gate insulating layer; an oxide layer disposed on the gate electrode; a source electrode disposed on the oxide layer and the n+ type region disposed in the first trench; and a drain electrode disposed at a second surface of the n+ type silicon carbide substrate.

Abstract: A switching device including: a body of semiconductor material, which has a first conductivity type and is delimited by a front surface; a contact layer of a first conductive material, which extends in contact with the front surface; and a plurality of buried regions, which have a second conductivity type and are arranged within the semiconductor body, at a distance from the contact layer.

Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

Abstract: A silicon layer is formed on a surface of each bottom source/drain region that is present at the footprint of a semiconductor fin. A first set of atoms (nitrogen atoms or carbon atoms) and a second set of atoms (boron atoms and/or carbon atoms) are then ion implanted into the silicon layer and the bottom source/drain regions. An anneal is then performed to convert the silicon layer into a bottom dielectric spacer that is composed of a reaction product of silicon, the first set of atoms and the second set of atoms, while converting each bottom source/drain region into a bottom source/drain structure that includes a first region and a second region. The second region is composed of a doped semiconductor material and at least one of the boron atoms and the carbon atoms; no measurable nitrogen tail and/or oxygen tail is present in the source/drain structures.

Abstract: A method for manufacturing a Schottky diode comprising steps of 1) providing a region with a dopant of a second conductivity type opposite to a first conductivity type to form a top doped region in a semiconductor substrate of said first conductivity type; 2) providing a trench through the top doped region to a predetermined depth and providing a dopant of the second conductivity type to form a bottom dopant region of the second conductivity type; and 3) lining a Schottky barrier metal layer on a sidewall of the trench at least extending from a bottom of the top doped region to a top of the bottom doped region.

Abstract: A method of forming an image sensor can be provided by forming a respective photoelectric conversion region in each of a plurality of unit pixel regions of a substrate and depositing a material configured to provide a negative fixed charge layer on the photoelectric conversion region.

Abstract: A semiconductor device comprises a transistor formed in a semiconductor body having a first main surface. The transistor comprises a source region, a drain region, a channel region, a drift zone, a source contact electrically connected to the source region, a drain contact electrically connected to the drain region, and a gate electrode at the channel region. The channel region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The channel region has a shape of a first ridge extending along the first direction. One of the source contact and the drain contact is adjacent to the first main surface, the other one of the source contact and the drain contact is adjacent to a second main surface that is opposite to the first main surface.

Abstract: A semiconductor device includes a buried layer in a substrate, the buried layer having a first dopant type. The semiconductor device further includes a first layer over the buried layer, the first layer having the first dopant type. The semiconductor device further includes at least one first well in the first layer, the at least one first well having a second dopant type. The semiconductor device further includes an implantation region in a sidewall of the first layer, the implantation region having the second dopant type, wherein the implantation region is below the at least one first well.

Abstract: Devices and methods for forming a device are presented. The method includes providing a substrate prepared with at least a first region for accommodating an anti-fuse based memory cell. A fin structure is formed in the first region. The fin structure includes top and bottom fin portions and includes channel and non-channel regions defined along the length of the fin structure. An isolation layer is formed on the substrate. The isolation layer has a top isolation surface disposed below a top fin surface, leaving the top fin portion exposed. At least a portion of the exposed top fin portion in the channel region is processed to form a sharpened tip profile at top of the fin. A gate having a gate dielectric and a metal gate electrode is formed over the substrate. The gate wraps around the channel region of the fin structure.

Abstract: A memory opening can be formed through a multiple tier structure. Each tier structure includes an alternating stack of sacrificial material layers and insulating layers. After formation of a dielectric oxide layer, the memory opening is filled with a sacrificial memory opening fill structure. The sacrificial material layers are removed selective to the insulating layers and the dielectric oxide layer to form backside recesses. Physically exposed portions of the dielectric oxide layer are removed. A backside blocking dielectric and electrically conductive layers are formed in the backside recesses. Subsequently, the sacrificial memory opening fill structure is replaced with a memory stack structure including a plurality of charge storage regions and a semiconductor channel. Hydrogen or deuterium from a dielectric core may then be outdiffused into the semiconductor channel.

Abstract: Techniques herein provide precise cuts for fins and nanowires without needing dummy gate pairs to compensate for overlay misalignment. Techniques herein include using an etch mask to remove designated portions of gate structures to define a trench or open space having fin structures, nanowires, etc. The uncovered fin structures are etched away or otherwise removed from the trench segments. The etch mask and material defining the trench provide a combined etch mask for removing uncovered fin portions. Subsequently the trench segments are filled with dielectric material. Without needed dummy gate pairs a given substrate can fit significantly more electrical devices per unit area.

Abstract: An embodiment semiconductor device includes a nanowire extending upwards from a semiconductor substrate, a source/drain region in the nanowire, and a channel region in the nanowire over the source/drain region. The source/drain region further extends into the semiconductor substrate past edges of the nanowire. The semiconductor device further includes a gate structure encircling the channel region and a silicide in an upper portion of the source/drain region. A sidewall of the silicide is aligned with a sidewall of the gate structure.

Abstract: A semiconductor device according to the present invention includes a semiconductor layer having a trench, a first insulating film formed along an inner surface of the trench, and an upper electrode and a lower electrode embedded in the trench via the first insulating film and disposed above and below a second insulating film. An electric field relaxation portion that relaxes an electric field arising between the upper electrode and the semiconductor layer is provided between a side surface of the trench and a lower end portion of the upper electrode.

Abstract: A JFET has a semiconductor body with a first surface and second surface substantially parallel to the first surface. A source metallization and gate metallization are arranged on the first surface. A drain metallization is arranged on the second surface. In a sectional plane substantially perpendicular to the first surface, the semiconductor body includes: a first semiconductor region in ohmic contact with the source and drain metallizations, at least two second semiconductor regions in ohmic contact with the gate metallization, spaced apart from one another, and forming respective first pn-junctions with the first semiconductor region, and at least one body region forming a second pn-junction with the first semiconductor region. The at least one body region is in ohmic contact with the source metallization. At least a portion of the at least one body region is, in a projection onto the first surface, arranged between the two second semiconductor regions.

Abstract: Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and method of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. Beneath each gate, a single gap fill dielectric layer extends vertically from a lower surface of the gate, at least partially separating the gate from the underlying global bit line. Between horizontally adjacent pillars, this same dielectric layer extends from its same lower level beneath the gates vertically to a level of the upper source/drain region.

Abstract: A method for forming a power semiconductor device is provided. The method includes providing a substrate having a first surface and a second surface; and forming a plurality of trenches in the second surface of the substrate. The method also includes forming a semiconductor pillar in each of the plurality of trenches, wherein the semiconductor pillars and the substrate form a plurality of super junctions of the power semiconductor device for increasing the breakdown voltage of the power semiconductor device and reducing the on-stage voltage of the power semiconductor device; and forming a gate structure on the first surface of the substrate. Further, the method includes forming a plurality of well regions in the first surface of the substrate around the gate structure; and forming a source region in each of the plurality of well regions around the gate structure.

Abstract: A VDMOS includes a substrate; an epitaxial layer; first and second trenches defined in the epitaxial layer; a shielding gate and a control gate formed in the trenches; a body region formed at the epitaxial layer and between the first and second trenches; a N+ source region formed at the body region; a distinct doping region formed in the epitaxial layer underneath the body region, extending towards bottoms of the trenches; a channel defined between the N+ source region and epitaxial layer adjacent to the trenches; an insulating layer defining a contact hole extending into the body region and the first trench; a P+ body pickup region formed in the body region corresponding to the contact hole; and a metal layer haying a butting contact filled in the contact hole, connecting the N+ source region, P+ body pickup region, and control gate and/or shielding gate in the first trench.

Abstract: A lateral trench MOSFET comprises an insulating layer buried in a substrate, a body region in the substrate, an isolation region in the substrate, a first drain/source region over the body region, a second drain/source region in the substrate, wherein the first drain/source region and the second drain/source region are on opposing sides of the isolation region, a drift region comprising a first drift region of a first doping density formed between the second drain/source region and the insulating layer, wherein the first drift region comprises an upper portion surrounded by isolation regions and a lower portion and a second drift region of a second doping density formed between the isolation region and the insulating layer, wherein a height of the second drift region is equal to a height of the lower portion of the first drift region.

Abstract: Embodiments are directed to an electromagnetic memory device having a memory cell and an encapsulation layer formed over the memory cell. The memory cell may include a magnetic tunnel junction (MTJ), and the encapsulation layer may be formed from a layer of hydrogenated amorphous silicon. Amorphous silicon improves the coercivity of the MTJ but by itself is conductive. Adding hydrogen to amorphous silicon passivates dangling bonds of the amorphous silicon, thereby reducing the ability of the resulting hydrogenated amorphous silicon layer to provide a parasitic current path to the MTJ. The hydrogenated amorphous silicon layer may be formed using a plasma-enhanced chemical vapor deposition, which can be tuned to enable a hydrogen level of approximately 10 to approximately 20 percent. By keeping subsequent processing operations at or below about 400 Celsius, the resulting layer of hydrogenated amorphous silicon can maintain its hydrogen level of approximately 10 to 20 percent.

Abstract: A silicon carbide semiconductor device includes trenches formed in a lattice shape on the surface of a silicon carbide substrate on which a semiconductor layer is formed, and gate electrodes formed inside of the trenches via a gate insulating film. The depth of the trenches is smaller in a portion where the trenches are crossingly formed than in a portion where the trenches are formed in parallel to each other. Consequently, the silicon carbide semiconductor device is obtained that increases a withstand voltage between the gate electrodes and corresponding drain electrodes on the semiconductor device rear surface to prevent dielectric breakdown and, at the same time, has a large area of the gate electrodes, high channel density per unit area, and low ON resistance.

Abstract: The disclosure relates to a semiconductor device and methods of forming same. A representative structure for a semiconductor device comprises a substrate; a nanowire structure protruding from the substrate having a channel region disposed between a source region and a drain region; a pair of silicide regions extending into opposite sides of the source region, wherein each of the pair of silicide regions comprise a vertical portion adjacent to the source region and a horizontal portion adjacent to the substrate; and a metal gate surrounding a portion the channel region.

Abstract: This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer.

Abstract: A semiconductor substrate having a first main surface and a transistor cell includes a drift region, a body region between the drift region and the first main surface, an active trench at the first main surface extending into the drift region, a gate insulating layer at sidewalls and a bottom side of the active trench, a gate conductive layer in the active trench, a source region in the body region, and adjacent to the active trench, a body trench at the first main surface extending into the drift region, the body trench being adjacent to the body region and to the drift region, an insulating layer at sidewalls and at a bottom side of the body trench, the insulating layer being asymmetric with respect to an axis extending perpendicular to the first main surface at a center of the body trench, and a conductive layer in the body trench.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a stacked body provided on the substrate and including a first stacked portion, a second stacked portion and an intermediate layer, the first stacked portion and the second stacked portion including a plurality of electrode layers and a plurality of insulating layers, the intermediate layer provided between the first stacked portion and the second stacked portion; a column including a semiconductor film and a charge storage film; and an insulating part provided in the stacked body. The column has a first enlarged portion. The insulating part has a second enlarged portion surrounded by the intermediate layer, the second enlarged portion has a larger width than a width of the portion of the insulating part in the first stacked portion and the second stacked portion.

Abstract: A semiconductor device includes lower and upper selection lines, a cell gate structure, a lower dummy structure and an upper dummy structure. The cell gate structure is between the lower and upper selection lines and includes cell gate electrodes stacked in a first direction. The lower dummy structure is between the lower selection line and the cell gate structure and includes a lower dummy gate line spaced from a lowermost one of the cell gate electrodes by a first distance. The upper dummy structure is between the upper selection line and the cell gate structure and includes an upper dummy gate line spaced from an uppermost one of the cell gate electrodes by a second distance. The cell gate electrodes are spaced by a third distance less than each of the first and second distances.

Abstract: A vertical gate all around (VGAA) nanowire device circuit routing structure is disclosed. The circuit routing structure comprises a plurality of VGAA nanowire devices including a NMOS and a PMOS device. The devices are formed on a semiconductor-on-insulator substrate. Each device comprises a bottom plate and a top plate wherein one of the bottom and top plates serves as a drain node and the other serves as a source node. Each device further comprises a gate layer. The gate layer fully surrounds a vertical channel in the device. In one example, a CMOS circuit is formed with an oxide (OD) block layer that serves as a common bottom plate for the NMOS and PMOS devices. In another example, a CMOS circuit is formed with a top plate that serves as a common top plate for the NMOS device and the PMOS devices. In another example, a SRAM circuit is formed.

Abstract: A finFET device according to some examples herein may include an active gate element above an active fin element and a dummy fin element that partially breaks the active gate element. In another example, a dummy gate element adjacent to an active gate element contains a dummy fin element that partially breaks the dummy gate element. In another example, a first dummy fin element partially breaks an active gate element and a second dummy fin element partially breaks a dummy gate element. In another example, the dummy fin element is of the same material as the active fin element. In another example, the dummy fin element partially breaks a gate element but does not extend to the substrate like the active fin element.

Abstract: A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of the top surface and the two opposed side surfaces, and a gate electrode covering at least a portion of the gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.

Abstract: A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film; a second step of forming a pillar-shaped semiconductor layer and a first dummy gate; a third step of forming a second dummy gate on side walls of the first dummy gate and the pillar-shaped semiconductor layer; a fourth step of forming a fifth insulating film and a sixth insulating film around the second dummy gate; a fifth step of depositing a first interlayer insulating film, removing the second dummy gate and the first dummy gate, forming a gate insulating film around the pillar-shaped semiconductor layer, depositing metal, and performing etch back to form a gate electrode and a gate line; and a sixth step of forming a first diffusion layer in an upper portion of the pillar-shaped semiconductor layer.

Abstract: An array substrate, a manufacture method thereof and a display device are provided. The array substrate includes: gate lines and data lines which are crossed to define a plurality of pixel units; and common electrode lines intersected with the data lines, the pixel units being provided with pixel electrodes; wherein, the common electrode lines are provided with first protrusions electrically connected to the common electrode lines; the gate lines are provided with first grooves; the first protrusions are disposed in the first grooves; and the pixel electrodes are overlapped with corresponding first protrusions.

Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a first silicide region on a first type surface region of the first type region. The first silicide region is separated at least one of a first distance from a first type diffusion region of the first type region or a second distance from the channel region.

Abstract: Vertical field effect transistor (FET) device with tunable bandgap source/drain regions are provided, as well as methods for fabricating such vertical FET devices. For example, a vertical FET device includes a lower source/drain region formed on a substrate, a vertical semiconductor fin formed on the lower source/drain region, and an upper source/drain region formed on an upper region of the vertical semiconductor fin. The lower source/drain region and vertical semiconductor fin are formed of a first type of III-V semiconductor material. The upper source/drain region is formed of a second type of III-V semiconductor material which comprises the first type of III-V semiconductor material and at least one additional element that increases a bandgap of the second type of III-V semiconductor material of the upper source/drain region relative to a bandgap of the first type of III-V compound semiconductor material of the lower source/drain region and the vertical semiconductor fin.

Abstract: A MOS transistor semiconductor component includes a semiconductor body with first and second surfaces, a first contact electrode on the first surface, a second contact electrode on the second surface, a first insulation layer separating a via region at least from a drift region, a monocrystalline semiconductor region arranged in the via region and extending between the first surface and the second surface, a gate electrode electrically connected to the first contact electrode, a source electrode electrically insulated from the gate electrode, and arranged at least partially above the first surface, and a drain electrode electrically insulated from the second contact electrode on the second surface. The MOS transistor has a gate terminal formed by the second contact electrode and electrically connected to a gate-electrode of the MOS transistor through the via region. The gate-electrode is formed next to the first surface and disposed outside the via region.

Abstract: An embodiment of a structure for a high voltage device of the type which comprises at least a semiconductor substrate being covered by an epitaxial layer of a first type of conductivity, wherein a plurality of column structures are realized, which column structures comprises high aspect ratio deep trenches, said epitaxial layer being in turn covered by an active surface area wherein said high voltage device is realized, each of the column structures comprising at least an external portion being in turn realized by a silicon epitaxial layer of a second type of conductivity, opposed than said first type of conductivity and having a dopant charge which counterbalances the dopant charge being in said epitaxial layer outside said column structures, as well as a dielectric filling portion which is realized inside said external portion in order to completely fill said deep trench.