Abstract: This invention discloses a semiconductor power device formed on an upper epitaxial layer of a first conductivity type supported on a semiconductor substrate comprises an active cell area and a termination area disposed near edges of the semiconductor substrate. The semiconductor power device having a super junction structure with the epitaxial layer formed with a plurality of doped columns of a second conductivity type. The termination area further comprises a plurality of surface guard ring regions of the second conductivity type dispose near a top surface of the epitaxial layer close to the doped columns of the second conductivity type. In one of the embodiments, one of the surface guard ring regions extending laterally over several of the doped columns in the termination area.

Abstract: A semiconductor device includes a region of semiconductor material comprising a semiconductor layer of a first conductivity type and having a first major surface. A body region of a second conductivity type opposite to the first conductivity type is disposed in the second semiconductor layer extending from the first major surface. The body region comprises a first segment having a first doping concentration, and a second segment laterally adjacent to the first segment and adjacent to the first major surface having a second doping concentration less than the first doping concentration. A source region of the first conductivity type is disposed in the first segment but is not disposed in at least a portion of the second segment. An insulated gate electrode is disposed adjacent to the region of semiconductor material adjoining the first segment, the second segment, and the source region. A conductive layer is electrically connected to the first segment, the second segment, and the first source region.

Abstract: Semiconductor device with multiple independent gates. A gate-controlled semiconductor device includes a first plurality of cells of the semiconductor device configured to be controlled by a primary gate, and a second plurality of cells of the semiconductor device configured to be controlled by an auxiliary gate. The primary gate is electrically isolated from the auxiliary gate, and sources and drains of the semiconductor device are electrically coupled in parallel. The first and second pluralities of cells may be substantially identical in structure.

Abstract: The present technology relates to an imaging element, an imaging device, and a manufacturing apparatus and a method that facilitate electric charge transfer. An imaging element of the present technology includes a vertical transistor that has a potential with a gradient in at least part of a charge transfer channel that transfers electric charge of a photoelectric conversion unit. Also, an imaging device of the present technology includes: an imaging element including a vertical transistor that has a potential with a gradient in at least part of a charge transfer channel that transfers electric charge of a photoelectric conversion unit; and an image processing unit that performs image processing on captured image data obtained by the imaging element.

Abstract: The present disclosure provides a semiconductor memory structure and a method for preparing the semiconductor memory structure. The semiconductor memory structure includes a substrate, a gate structure, a drain stressor and a source stressor. The gate structure is disposed in the substrate. Each of the source stressor and the drain stressor includes a strained part disposed in the substrate.

Abstract: Systems and methods of optimizing a gate profile for performance and gate fill are disclosed. A semiconductor device having an optimized gate profile includes a semiconductor substrate and a fin extending above the semiconductor substrate. A pair of source and drain regions are disposed on opposite sides of a channel region. A gate stack is disposed over the channel region, where the gate stack includes a top portion separated from a bottom portion by a tapered portion. The top portion and at least a portion of the tapered portion are disposed above the fin.

Abstract: A semiconductor device includes a substrate, first, second, third and fourth bottom contacts in the substrate, and first, second, third and fourth active fins on respective ones of the first, second, third and fourth bottom contacts, the second and third fins overlapping in a first direction. First, second and third gate electrodes extend longitudinally in the first direction, the first and second gate electrodes disposed on side surfaces of respective ones of the first and fourth active fins and the third gate electrode disposed on side surfaces of the second and third active fins. A first top contact is on the first and second active fins and a second top contact is on the third and fourth active fins.

Abstract: A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side, a plurality of gate electrodes that are arranged at intervals on the first main surface of the semiconductor layer, an interlayer insulating film that is formed on the first main surface of the semiconductor layer such as to cover the gate electrodes, an electrode film that is formed on the interlayer insulating film, and a plurality of tungsten plugs that, between a pair of the gate electrodes that are mutually adjacent, are respectively embedded in a plurality of contact openings formed in the interlayer insulating film at intervals in a direction in which the pair of mutually adjacent gate electrodes face each other and each have a bottom portion contacting the semiconductor layer and a top portion contacting the electrode film.

Abstract: A method of manufacturing a super junction structure includes etching a material to define a trench, wherein the trench has a tapered profile. The method further includes implanting dopants into sidewalls and a bottom surface of the trench to define a doped region, wherein the doped region surrounds the trench. The method further includes depositing an undoped material into the trench. The method further includes performing a thermal process, wherein the thermal process drives the dopants from the doped region into the undoped material to form a conductive pillar in the trench.

Abstract: An embodiment of a semiconductor device includes a semiconductor mesa in an active device area. The semiconductor mesa includes source regions arranged along a longitudinal direction of the semiconductor mesa and separated from one another along the longitudinal direction. The semiconductor device further includes an electrode trench structure including a dielectric and an electrode. The electrode trench structure adjoins a side of the semiconductor mesa. The semiconductor device further includes an isolation trench structure filled with one or more insulating materials. The isolation trench structure extends through the semiconductor mesa and into or through the electrode trench structure along a first lateral direction.

Abstract: A semiconductor device may include active patterns extended in a first direction and spaced apart from each other in the first direction, a device isolation layer defining the active patterns, an insulating structure provided between the active patterns and between the device isolation layer, and a gate structure disposed on the insulating structure and extended in a second direction crossing the first direction. The gate structure may include an upper portion and a lower portion. The lower portion of the gate structure may be enclosed by the insulating structure.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first source/drain structure and a second source/drain structure in the substrate. The semiconductor device structure includes a gate stack over the substrate and between the first source/drain structure and the second source/drain structure. The gate stack includes a gate dielectric layer and a gate over the gate dielectric layer, a portion of the gate dielectric layer is adjacent to a first sidewall of the gate, the gate stack has a gap between the first sidewall and the portion of the gate dielectric layer, and the gap is a vacuum gap or an air gap.

Abstract: A semiconductor device includes a semiconductor layer that has a first surface and a second surface, a trench that is formed at the first surface of the semiconductor layer and that extends in a first direction, an element portion that has a first-conductivity-type first region, a second-conductivity-type second region, and a third-conductivity-type third region that are formed in order along a depth direction of the trench from the first surface of the semiconductor layer, a gate insulating film formed at an inner surface of the trench, and a gate electrode that is embedded in the trench and that faces the first region, the second region, and the third region through the gate insulating film.

Abstract: A method and a transistor device are disclosed. The method includes: forming first regions of a first doping type and second regions of a second doping type in an inner region and an edge region of a semiconductor body; and forming body regions and source regions of transistor cells in the inner region of the semiconductor body. Forming the first regions and second regions includes: forming semiconductor layers one on top of the other; and in each of the semiconductor layers and before forming a respective next one of the semiconductor layers, forming trenches in the inner region and the edge region and implanting dopant atoms into a first sidewall and a second sidewall of each trench. Implanting the dopant atoms into at least one of the semiconductor layers includes partly covering the trenches in the edge region during an implantation process.

Abstract: A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.

Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating first tiers and second tiers. A first insulator tier is above the stack. First insulator material of the first insulator tier comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Channel-material strings are in the stack and in the first insulator tier. Conducting material is in the first insulator tier directly against sides of individual of the channel-material strings. A second insulator tier is formed above the first insulator tier and the conducting material. Second insulator material of the second insulator tier comprises at least one of the (a) and the (b). Conductive vias are formed and extend through the second insulator tier and that are individually directly electrically coupled to the individual channel-material strings through the conducting material.

Abstract: SiC Schottky rectifier 100 with surge current ruggedness. As referenced above, the Schottky rectifier 100 may be configured to provide multiple types of surge current protection.

Abstract: In a contact hole of an interlayer insulating film, a tungsten film forming a contact plug is embedded via a barrier metal. The interlayer insulating film is formed by sequentially stacked HTO and BPSG films. The BPSG film has an etching rate faster than that of the HTO film with respect to a hydrofluoric acid solution used in wet etching of preprocessing before formation of the barrier metal. After the contact hole is formed in the interlayer insulating film, a width of an upper portion of the contact hole at the BPSG film is increased in a step-like shape, to be wider than a width of a lower portion at the HTO film by the wet etching before the formation of the barrier metal, whereby an aspect ratio of the contact hole is reduced. Thus, size reductions and enhancement of the reliability may be realized.

Abstract: In an embodiment, a semiconductor device is provided. The semiconductor device includes: a semiconductor body of a first conductivity type having opposing first and second major surfaces; a gate arranged in a trench extending into the semiconductor body from the first major surface; a body region of a second conductivity type; a source region of the first conductivity type arranged on the body region and having first and second dopant species. The source region forms a pn-junction with the body junction, the pn-junction being arranged at a depth dpn from the first major surface, wherein 50 nm<dpn<300 nm. A drain region of the first conductivity type is arranged in the semiconductor body under the trench.

Abstract: A semiconductor device, a method of fabricating the semiconductor device and a memory are disclosed. In the provided semiconductor device, bit line contact plugs partially reside on insulating material layers in gate trenches in active areas and thus can come into sufficient contact with the active areas. This ensures good electrical transmission between the bit line contact plugs and the active areas even when there are internal voids in the bit line contact plugs. Such bit line contact plugs allowed to contain internal voids can be fabricated in an easier and faster manner, thus allowing a significantly enhanced memory fabrication throughput.

Abstract: The present invention provides a Group III nitride semiconductor device in which current concentration at the corners of the trench is suppressed. The semiconductor device has a pattern in which regular hexagonal unit cells are arranged in a honeycomb pattern. The semiconductor layer is sectionalized into regular hexagonal patterns by the trench. The recess has a small regular hexagonal pattern contained in the regular hexagonal pattern of the semiconductor layer sectionalized by the trench, which is obtained by reducing the regular hexagon of the semiconductor layer with the same center. Moreover, the regular hexagonal pattern of the recess is rotated by 30° with respect to the regular hexagon of the semiconductor layer. The Mg activation ratio is lower in the vicinity of corners of the trench than that in other regions in the vicinity of side walls of the trench of the p-type layer.

Abstract: In at least one general aspect, an apparatus can include a first trench disposed in a semiconductor region and including a gate electrode, and a second trench disposed in the semiconductor region. The apparatus can include a mesa region disposed between the first trench and the second trench, and a source region of a first conductivity type disposed in a top portion of the mesa region. The apparatus includes a plurality of body region segments of a second conductivity type disposed in the side of the mesa region. The plurality of body region segments define an alternating pattern with the plurality of source region segments along the side of the mesa region.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to one embodiment includes a first gate stack, a second gate stack, a first source/drain feature disposed between the first and second gate stacks, and a source/drain contact over and electrically coupled to the first source/drain feature. The source/drain contact is spaced apart from each of the first and second gate stacks by an inner spacer disposed on sidewalls of the source/drain contact, a first air gap, a first gate spacer, and a second air gap separated from the first air gap by the first gate spacer.

Abstract: A semiconductor device according to an embodiment includes: a semiconductor layer including a first trench, a second trench intersecting the first trench, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, and a third semiconductor region of the first conductivity type; a gate electrode located in the first trench; a field plate electrode; a metal region located in the second trench and electrically connected to the second semiconductor region; a gate insulating layer located between the gate electrode and the semiconductor layer; a field plate insulating layer located between the field plate electrode and the semiconductor layer; a first electrode electrically connected to the third semiconductor region and the metal region; and a second electrode.

Abstract: A method of fabricating a semiconductor device includes forming a device isolation layer in a substrate to define a plurality of active regions extending in a first direction; forming a trench in an upper portion of the substrate that crosses the active regions in a second direction that intersects the first direction; forming a sacrificial layer that fills the trench; forming support patterns on the sacrificial layer, wherein the support patterns fill recessed regions provided at a top surface of the sacrificial layer; and removing the sacrificial layer. The support patterns are spaced apart from each other with the active regions interposed therebetween.

Abstract: On a front surface of a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type having an impurity concentration lower than an impurity concentration of the silicon carbide semiconductor substrate is formed. A base region of a second conductivity type is selectively formed in the first semiconductor layer. A second semiconductor layer of the second conductivity type is formed on a surface of the first semiconductor layer. A first semiconductor region of the first conductivity type is selectively formed in a surface layer of the second semiconductor layer. The base region is formed by implanting an impurity of the second conductivity type from an angle that relative to a perpendicular to the silicon carbide semiconductor substrate, is three degrees or more.

Abstract: In a general aspect, a semiconductor device can include a semiconductor region of a first conductivity type and a well region of a second conductivity type. The well region can be disposed in the semiconductor region. An interface between the well region and the semiconductor region can define a diode junction at a depth below an upper surface of the semiconductor region. The semiconductor device can further include at least one dielectric region disposed in the semiconductor region. A dielectric region of the at least one dielectric region can have an upper surface that is disposed in the well region at a depth in the semiconductor region that is above the depth of the diode junction; and a lower surface that is disposed in the semiconductor region at a depth in the semiconductor region that is the same depth as the diode junction or below the depth of the diode junction.

Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a first insulating portion, a second electrode, a gate electrode, a second insulating portion, and a third electrode. The second electrode is provided inside the first insulating portion, and includes a portion opposing the first semiconductor region in the second direction. The gate electrode is provided inside the first insulating portion and opposes the second semiconductor region with a gate insulating layer interposed in the second direction. The second insulating portion is linked to the first insulating portion. The third electrode is electrically connected to the second semiconductor region, and the third semiconductor region.

Abstract: The disclosure describes a tunneling field effect transistor having an overlapping structure between the source and drain regions providing a greater tunneling area. The source or drain region may be a doped region in a semi-conductive substrate. The other source or drain region may be formed by epitaxial deposition over the doped region. The gate is formed over the epitaxial region where the doped and epitaxial regions overlap. The doped region may be formed in a fin structure with the epitaxial region and gate being formed on the top and sides of the fin.

Abstract: A trench gate metal oxide semiconductor field effect transistor (MOSFET) device includes an epitaxial layer on a substrate both doped a first conductivity type. Active area trenches have polysilicon gates over a double shield field plate. A junction termination trench includes a single shield field plate in a junction termination area which encloses the active area that includes a retrograde dopant profile of the second conductivity type into the epitaxial layer in the junction termination area. Pbody regions of a second conductivity type are between active trenches and between the outermost active trench and the junction termination trench. Source regions of the first conductivity type are in the body regions between adjacent active trenches. Metal contacts are over contact apertures that extend through a pre-metal dielectric layer reaching the body region under the source region, the single shield field plate, and that couples together the polysilicon gates.

Abstract: At edge termination region, a trench is disposed near an interface of an active region. Inside the trench, an embedded insulating film is embedded, and inside the embedded insulating film, a FP long in a direction of depth is disposed. The FP curves outwardly away from an inner sidewall of the trench as a depth from a base front surface increases. At least near a bottom end of the FP, a distance between the FP and the inner sidewall of trench is greater than a width of the groove. The FP is connected to a front surface electrode that extends on the embedded insulating film. As a result, breakdown voltage can be enhanced, adverse effects of the surface charge can be reduced, and chip size can be further reduced.

Abstract: A high-voltage semiconductor device includes a substrate, a first insulating structure, a gate, a drain region, a source region and a doped region. The substrate has a first conductive type, and the first insulating structure is disposed on the substrate. The drain region and the source region are disposed in the substrate. The source region has a first portion and a second portion. The first portion has the second conductive type and the second portion has the first conductive type. The gate is disposed on the substrate, between the source region and the drain region to partially cover a side of the first insulating structure. The doped region is disposed in the substrate and has a first doped region and a second doped region, and the first doped region and the second doped region both include the first conductive type and separately disposed under the first insulating structure.

Abstract: A lateral insulated gate turn-off device includes an n-drift layer, a p-well formed in the n? drift layer, a shallow n+ type region formed in the well, a shallow p+ type region formed in the well, a cathode electrode shorting the n+ type region to the p+ type region, a trenched first gate extending through the n+ type region and into the well, a p+ type anode region laterally spaced from the well, an anode electrode electrically contacting the p+ type anode region, and a trenched second gate extending from the p+ type anode region into the n-drift layer. For turning the device on, a positive voltage is applied to the first gate the reduce the base width of the npn transistor, and a negative voltage is applied to the second gate to effectively extend the p+ emitter of the pnp transistor further into the n-drift layer to improve performance.

Abstract: A semiconductor device includes a semiconductor layer that has a main surface and that includes an active region, a first-conductivity-type first impurity region formed at a surface layer portion of the main surface of the semiconductor layer, a second-conductivity-type field limit region formed along a peripheral edge of the active region in a surface layer portion of the first impurity region, and a second-conductivity-type low concentration region that has a second-conductivity-type impurity concentration lower than a second-conductivity-type impurity concentration of the field limit region and that is formed along a peripheral edge of the field limit region in a region on a side opposite to the active region with respect to the field limit region in the surface layer portion of the first impurity region.

Abstract: An insulated gate bipolar transistor includes: a semiconductor substrate; an emitter electrode arranged on one main surface of the semiconductor substrate; and a trench gate arranged in a rectangular trench having a rectangular shape and disposed on the one main surface of the semiconductor substrate. The semiconductor substrate includes a body contact region and an emitter region in a rectangular region surrounded by the rectangular trench. The rectangular trench has a straight trench that constitutes one side of the rectangular trench. The body contact region is in contact with a side of the straight trench. The emitter region is in contact with the side of the straight trench, and is adjacent to the body contact region. The body contact region has a protrusion portion protruding in a depth direction from a center portion of the body contact region.

Abstract: A semiconductor device of an embodiment includes: a first semiconductor layer of a first conductive type; a second semiconductor layer of the first conductive type, being provided on the first semiconductor layer and including a first trench, a plurality of holes, a plurality of second trenches, and a plurality of third trenches; a first semiconductor region of a second conductive type, being provided on the second semiconductor layer; a second semiconductor region of the first conductive type, being provided on the first semiconductor region; a first electrode electrically connected to the second semiconductor region; a second electrode disposed in the first trench via a first insulation film; a plurality of first field plate electrodes having a column shape, being electrically connected to the first electrode, interposing the second electrode, and being disposed in the holes via a second insulation film; a plurality of third electrodes extending from ends of the first insulation films in a first direction t

Abstract: An optical semiconductor device includes a semiconductor substrate having a plurality of photoelectric conversion parts and having a trench formed to separate the plurality of photoelectric conversion parts from each other, an insulating layer formed on at least an inner surface of the trench, a boron layer formed on the insulating layer, and a metal layer formed on the boron layer.

Abstract: A semiconductor device structure can include: (i) a first semiconductor layer having dopants of a first type; (ii) a second semiconductor layer having the dopants of the first type on the first semiconductor layer, where the second semiconductor layer is lightly-doped relative to the first semiconductor layer; (iii) first and second column regions spaced from each other in the second semiconductor layer, where the second column region is arranged between two of the first column regions; and (iv) first and second first sub-column regions laterally arranged in the second column region, where a doping concentration of the first sub-column region decreases in a direction from the first column region to the second sub-column region, and where a doping concentration of the second sub-column region decreases in a direction from the first column region to the first sub-column region.

Abstract: Different isolation liners for different type FinFETs and associated isolation feature fabrication are disclosed herein. An exemplary method includes performing a fin etching process on a substrate to form first trenches defining first fins in a first region and second trenches defining second fins in a second region. An oxide liner is formed over the first fins in the first region and the second fins in the second region. A nitride liner is formed over the oxide liner in the first region and the second region. After removing the nitride liner from the first region, an isolation material is formed over the oxide liner and the nitride liner to fill the first trenches and the second trenches. The isolation material, the oxide liner, and the nitride liner are recessed to form first isolation features (isolation material and oxide liner) and second isolation features (isolation material, nitride liner, and oxide liner).

Abstract: A gate structure of a semiconductor device, includes: a trench gate and a planar gate including a plurality of polysilicon structures (406) separated from each other; the gate structure of the semiconductor device further includes a well region (503) being adjacent to the trench gate and being disposed under the planar gate; a first conduction type doped region (504) being disposed in the well region (503) and including a plurality of regions separated from each other, wherein each region is disposed under adjacent polysilicon structures (406), and respective regions are electrically connected to the planar gate; and a source (504a) being disposed in the well region (503); wherein the trench gate includes: a silicon oxide filler (202) including a side wall silicon oxide and a bottom silicon oxide; a control gate (402) being located over the trench gate, wherein a side wall of the control gate is enclosed by the side wall silicon oxide, and the control gate (402) is electrically-connected to the planar gate; a

Abstract: A semiconductor device and methods for forming the same are provided. The method includes providing a substrate having a first conductive type, forming an epitaxial layer having the first conductive type on the substrate, forming a trench in the epitaxial layer, forming a first insulating layer in the trench and on the top surface of the epitaxial layer, forming a shield electrode and a mask layer on the first insulating layer in order, using the mask layer to remove a portion of the first insulating layer, wherein the top surface of the first insulating layer is higher than the top surface of the shield electrode after removing the portion of the first insulating layer, removing the mask layer, forming a second insulating layer on the first insulating layer and the shield electrode, and forming a gate electrode on the second insulating layer.

Abstract: A semiconductor device includes a first conductivity type semiconductor layer having a first surface and a second surface opposite to the first surface and having an element portion formed in the first surface and an outer peripheral portion surrounding the element portion, a semiconductor element structure formed in the element portion, multiple guard ring trenches formed in the outer peripheral portion and each formed in the first surface of the semiconductor layer, and a second conductivity type outer peripheral portion impurity region formed in the outer peripheral portion, in which the multiple guard ring trenches include a first unit consisting of multiple guard ring trenches and a second unit consisting of multiple guard ring trenches arranged on the outside of the semiconductor layer relative to the multiple guard ring trenches belonging to the first unit, and in which the outer peripheral portion impurity region includes a first portion arranged below the multiple guard ring trenches belonging to the

Abstract: Provided is a method of forming a trench gate MOSFET. A hard mask layer is formed on a substrate. The substrate is partially removed by using the hard mask layer as a mask, so as to form a trench in the substrate. A first insulating layer and a first conductive layer are formed in the lower portion of the trench. A sacrificial layer is formed on the side surface of the upper portion of the trench, and the sacrificial layer is connected to the hard mask layer. An interlayer insulating layer is formed on the first conductive layer by a thermal oxidation process when the sacrificial layer and the hard mask layer are present. A second insulating layer and a second conductive layer are formed in the upper portion of the trench. A trench gate MOSFET is further provided.

Abstract: A semiconductor device includes a semiconductor layer. A first conductivity type region is formed on a base layer portion of the semiconductor layer. A body region of a second conductivity type is formed on the semiconductor layer to be in contact with the first conductivity type region. A trench in which a gate electrode is embedded through a gate insulating film is formed on the semiconductor layer. The trench penetrates through the body region, so that a deepest portion thereof reaches the first conductivity type region. A source region of the first conductivity type is formed on a surface layer portion of the semiconductor layer around the trench. The gate insulating film includes a thick-film portion having a relatively large thickness on a bottom surface of the trench.

Abstract: A semiconductor device includes a transistor in a semiconductor body having a main surface. The transistor includes a source region; a drain region; a body region; a drift zone; a gate electrode at the body region, the body region and the drift zone being disposed along a first direction between the source region and the drain region, and the first direction being parallel to the main surface; a field plate disposed in each of a plurality of field plate trenches, each of the field plate trenches having a longitudinal axis extending along the first direction; and a field dielectric layer between the field plate and the drift zone, a thickness of the field dielectric layer at a bottom of each of the field plate trenches gradually increases along the first direction, the thickness being measured along a depth direction of the plurality of field plate trenches.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side, a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer, a trench source structure including a source trench formed deeper than the gate trench and across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a deep well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, a ratio of a depth of the trench source structure with respect to a depth of the trench gate structure being not less than 1.5 and not more than 4.

Abstract: According to an embodiment a semiconductor device includes a semiconductor layer including first trenches and second trenches, a first gate electrode in the first trench, a second gate electrode in the second trench, a first gate electrode pad, a second gate electrode pad, a first wiring connecting the first gate electrode pad and the first gate electrode, and a second wiring connecting the second gate electrode pad and the second gate electrode. The semiconductor layer includes a first connection trench. Two first trenches adjacent to each other are connected to each other at end portions by the first connection trench. At least one of the second trenches is provided between the two first trenches. The second gate electrode in the at least one second trench is electrically connected to the second wiring between the two first trenches.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first source region, a second source region, a first drain region, and a second drain region. The semiconductor device structure includes a first gate structure over the substrate and between the first source region and the first drain region. The semiconductor device structure includes a second gate structure over the substrate and between the second source region and the second drain region. A first thickness of the first gate structure is greater than a second thickness of the second gate structure. A first gate width of the first gate structure is less than a second gate width of the second gate structure.

Abstract: 2D self-aligned contact structures (both gate contact and source/drain contact) are provided that can improve the process control and push further scaling. The 2D self-aligned contact structures can enable tighter process control which can lead to further device scaling. In accordance with the present application, the gate contact structure is confined in one direction by a sacrificial spacer structure that is present in a dielectric material layer, and in another direction by an edge of a metallization structure that is located above the gate contact structure.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes steps of creating at least one trench in a substrate; forming a dielectric film on the substrate in the trench; depositing a first conductive layer on the dielectric film to partially fill the trench; depositing an insulative film on the first conductive layer; depositing a second conductive layer to bury the insulative film; and recessing the first conductive layer, until the insulative film is entirely removed. Due to the deposition of the insulative film on the first conductive layer, the etch depth of the superfluous first conductive layer can be accurately controlled.