Abstract: The present application discloses a semiconductor device with the multi-layered connecting structure and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a single-layered connecting structure positioned above the substrate, and a multi-layered connecting structure positioned above the substrate and including a plurality of first conductive layers and a plurality of second conductive layers alternatively stacked. A top surface of the multi-layered connecting structure is substantially coplanar with a top surface of the single-layered connecting structure and a width of the multi-layered connecting structure is less than a width of the single-layered connecting structure.

Abstract: A silicon carbide semiconductor device has a gate insulating film, a first gate electrode, a first electrode, a second electrode, and a gate runner. A silicon carbide substrate has a first main surface and a second main surface. The silicon carbide substrate includes a first impurity region, a second impurity region, and a third impurity region. The first main surface is provided with a gate electrode trench and a gate runner trench. The gate electrode trench is defined by a side surface and a bottom surface continuous to the side surface. The gate insulating film is in contact with both the side surface and the bottom surface. The first gate electrode is provided on the gate insulating film. The second gate electrode is provided in the gate runner trench, and is electrically connected to the first gate electrode. The gate runner is provided on the second gate electrode.

Abstract: A semiconductor device having a metal oxide semiconductor that includes a semiconductor substrate, a first semiconductor layer provided on a the semiconductor substrate, a plurality of second semiconductor layers selectively provided on the first semiconductor layer, a plurality of first semiconductor regions selectively provided in the second semiconductor layers at a surface thereof, a plurality of gate insulating films with a plurality of gate electrodes provided thereon, a plurality of first electrodes provided on the second semiconductor layers and the first semiconductor regions, and a second electrode provided on a back surface of the semiconductor substrate. The MOS structure configures an active region and a current detecting region of the semiconductor device. The semiconductor substrate and the first semiconductor layer are in both the active region and the current detecting region.

Abstract: First and second trenches are provided in a semiconductor body. A mesa dividing structure is provided between the first and second trenches and comprises non-semiconductor material. A first semiconductor mesa is provided between the first trench and the non-semiconductor material of the mesa dividing structure. The first semiconductor mesa includes emitter, body and drift regions. The first and second trenches are formed by a masked etching technique with a minimum trench separation distance, and the first semiconductor mesa is provided to have a lateral width that is less than the minimum trench separation distance.

Abstract: A wide gap semiconductor device has: a drift layer 12 using wide gap semiconductor material being a first conductivity type; a plurality of well regions 20 being a second conductivity type and formed in the drift layer 12; a polysilicon layer 150 provided on the well regions 20 and on the drift layer 12 between the well regions 20; an interlayer insulating film 65 provided on the polysilicon layer 150; a gate pad 120 provided on the interlayer insulating film 65; and a source pad 110 electrically connected to the polysilicon layer 150.

Abstract: A method of production of a field-effect transistor from a stack of layers forming a semiconductor-on-insulator type substrate, the stack including a superficial layer of an initial thickness, made of a crystalline semiconductor material and covered with a protective layer, the method including: defining, by photolithography, a gate pattern in the protective layer; etching the gate pattern into the superficial layer to leave a thickness of the layer of semiconductor material in place, the thickness defining a height of a conduction channel of the field-effect transistor; forming a gate in the gate pattern; forming, in the superficial layer and on either side of the gate, source and drain zones, while preserving, in the zones, the initial thickness of the superficial layer.

Abstract: A method of integrated circuit (IC) fabrication includes exposing a plurality of channel regions including a p-type channel region and an n-type channel region; forming a gate dielectric layer over the exposed channel regions; and forming a work function metal (WFM) structure over the gate dielectric layer. The WFM structure includes a p-type WFM portion formed over the p-type channel region and an n-type WFM portion formed over the n-type channel region, and the p-type WFM portion is thinner than the n-type WFM portion. The method further includes forming a fill metal layer over the WFM structure such that the fill metal layer is in direct contact with both the p-type and n-type WFM portions.

Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface, a first region of a first conductivity type formed on the first surface side of the semiconductor layer, a second region of a second conductivity type in contact with the first region, a third region of the first conductivity type that is in contact with the second region and exposed from the first surface side of the semiconductor layer, a gate electrode facing the second region through a gate insulating film, a first electrode that is physically separated from the gate electrode and faces the second region and the third region through an insulating film, a second electrode formed on the semiconductor layer and electrically connected to the first region, the second region, and the first electrode, and a third electrode electrically connected to the third region.

Abstract: A semiconductor device includes a semiconductor body, a first electrode, a control electrode and a control interconnection electrically connected to the control electrode. The first electrode, the control electrode, and the control interconnection are provided on a front surface side of the semiconductor body. The control electrode is shaped as one body in a trench. The control electrode includes a first portion, a second portion, a first end portion and a second end portion that are arranged in a direction along the front surface of the semiconductor body. The first and second portions are positioned between the first and second end portions. The first portion is positioned between the first electrode and the semiconductor body, and the second portion is positioned between the control interconnection and the semiconductor body. The control interconnection crosses the second portion of the control electrode, and is electrically connected thereto.

Abstract: Provided is a semiconductor device, wherein: in a semiconductor substrate, a lifetime control region is provided from at least a part of a transistor portion to a diode portion; the transistor portion includes a main region, a boundary region located between the main region and the diode portion and overlapped with the lifetime control region, and a plurality of gate trench portions; the plurality of gate trench portions include a first gate trench portion provided in the main region and a second gate trench portion provided in the boundary region; and a gate resistance component of the first gate trench portion is different from a gate resistance component of the second gate trench portion.

Abstract: A metal oxide semiconductor field effect transistor and a method for manufacturing the same are provided. The metal oxide semiconductor field effect transistor includes a substrate structure, doped regions, an oxide layer structure, semiconductor layer structures, a dielectric layer structure, and a metal structure. The substrate structure includes a base layer and an epitaxial layer. The epitaxial layer forms a plurality of trenches along a first direction. Any two adjacent trenches form a pitch therebetween, and the pitches formed between the trenches are increased along the first direction. The doped regions are formed at bottoms of the trenches. The oxide layer structure is formed on inner walls of the trenches and a surface of the epitaxial layer. The semiconductor layer structures are respectively formed in the trenches. The dielectric layer structure is formed on the oxide layer structure. The metal structure is formed on the dielectric layer structure.

Abstract: A backplane structure containing a capacitor includes a substrate, a first conductive film disposes on the substrate, a second conductive member having one portion spaced apart from the first conductive film and another portion connected to the first conductive film, a third conductive film spaced apart from the first conductive film and the second conductive member, a fourth conductive member connected to the third conductive film, and a fifth conductive member having one portion connected to the fourth conductive member and another portion spaced apart from the second conductive member. The third conductive film is disposed between the first conductive film and the second conductive member in an insulation manner, and the second conductive member is disposed between the third conductive film, the fourth conductive member, and the fifth conductive member in an insulation manner.

Abstract: A semiconductor device, including a first semiconductor layer of the first conductivity type formed on a semiconductor substrate, a first semiconductor region of the first conductivity type, a first base region of a second conductivity type and a first base region of a second conductivity type that are respectively selectively provided in the first semiconductor layer, a second semiconductor layer of the second conductivity type provided on the first semiconductor layer, a second semiconductor region of the first conductivity type selectively provided in the second semiconductor layer, a trench that penetrates the second semiconductor layer and the second semiconductor region, a gate electrode provided in the trench via a gate insulating film, an interlayer insulating film provided on the gate electrode, a first electrode in contact with the second semiconductor layer and the second semiconductor region, and a second electrode provided on a back surface of the semiconductor substrate.

Abstract: The semiconductor device of the present invention includes a semiconductor substrate, a switching element which is defined on the semiconductor substrate, and a temperature sense element which is provided on the surface of the semiconductor substrate independently from the switching element and characterized by being dependent on a temperature.

Abstract: A semiconductor device includes: a substrate; a drift region disposed on a principal surface of the substrate; a first well region extending from a second principal surface of the drift region in a direction perpendicular to the second principal surface and having a bottom portion; a second well region being in contact with the bottom portion and disposed at a portion inside the substrate located below the bottom portion; and a source region extending in a perpendicular direction from a region of the second principal surface provided with the first well region, and reaching the second well region. In a direction parallel to the second principal surface and oriented from a source electrode to a drain electrode, a distance of the second well region in contact with a gate insulating film is shorter than a distance of the first well region in contact with the gate insulating film.

Abstract: A drift layer made of silicon carbide has a first conductivity type. A body region on the drift layer has a second conductivity type. A source region on the body region has the first conductivity type. A gate insulating film is on each inner wall of at least one trench. A protective layer has at least a portion below the trench, is in contact with the drift layer, and has the second conductivity type. A first low-resistance layer is in contact with the trench and the protective layer, straddles a border between the trench and the protective layer in the depth direction, has the first conductivity type, and has a higher impurity concentration than the drift layer. A second low-resistance layer is in contact with the first low-resistance layer, is away from the trench, has the first conductivity type, and has a higher impurity concentration than the first low-resistance layer.

Abstract: A semiconductor device includes a semiconductor part; first and second electrodes respectively on back and front surfaces of the semiconductor part; and a control electrode between the semiconductor part and the second electrode. The control electrode is provided inside a trench of the semiconductor part. The control electrode is electrically insulated from the semiconductor part by a first insulating film and electrically insulated from the second electrode by a second insulating film. The control electrode includes an insulator at a position apart from the first insulating film and the second insulating film. The semiconductor part includes a first layer of a first conductivity type provided between the first and second electrodes, the second layer of a second conductivity type provided between the first layer and the second electrode and the third layer of the first conductivity type selectively provided between the second layer and the second electrode.

Abstract: A MOSFET device comprising: a structural region, made of a semiconductor material having a first type of conductivity, which extends between a first side and a second side opposite to the first side along an axis; a body region, having a second type of conductivity opposite to the first type, which extends in the structural region starting from the first side; a source region, having the first type of conductivity, which extends in the body region starting from the first side; a gate region, which extends in the structural region starting from the first side, traversing entirely the body region; and a shielding region, having the second type of conductivity, which extends in the structural region between the gate region and the second side. The shielding region is an implanted region self-aligned, in top view, to the gate region.

Abstract: A semiconductor device is provided. The semiconductor device includes a base substrate, which include a first region having a first transistor and a second region having a second transistor, the first transistor having a working current smaller than the second transistor. The semiconductor device further includes a first gate electrode on the first region of the base substrate, a second gate electrode on the second region of the base substrate and having an undercut structure, a first source/drain doped region in the base substrate on both sides of the first gate electrode, and a second source/drain doped region in the base substrate on both sides of the second gate electrode.

Abstract: A silicon carbide semiconductor device includes a first semiconductor layer of a first conductivity type provided on a front surface of a semiconductor substrate of the first conductivity type; a second semiconductor layer of a second conductivity type; a first semiconductor region of the first conductivity type; and a gate electrode having a striped-shape and provided on a gate insulating film. The silicon carbide semiconductor device further includes a first electrode provided on a surface of the second semiconductor layer and the first semiconductor region; a step film provided on the first electrode; a plating film provided on the first electrode and the step film; and a solder on the plating film. The step film is provided on the first electrode on which the solder and the plating film are provided, the step film being provided so as to be embedded in grooves formed on the first electrode.

Abstract: A method includes forming a hard mask over an epitaxy layer of a substrate; forming a patterned mask over the hard mask; etching the hard mask and the epitaxy layer to form a trench in the epitaxy layer, in which a remaining portion of the hard mask covers a topmost surface of the epitaxy layer, and the trench exposes a sidewall of the epitaxy layer; forming a P-well region by directing p-type ion beams into the trench along an oblique direction that is non-parallel to a normal line of the topmost surface of the epitaxy layer, in which the topmost surface of the epitaxy layer is protected from the p-type ion beams by the remaining portion of the hard mask during directing the p-type ion beams into the trench; and after directing the p-type ion beams into the trench, forming a gate structure in the trench.

Abstract: A region of a portion directly beneath an OC pad is a sensing effective region in which unit cells of a current sensing portion are disposed. A p-type low-dose region is provided on a front surface of a semiconductor substrate and surrounds a periphery of the sensing effective region. The p-type low-dose region is fixed at an electric potential of a source pad of a main semiconductor element. The p-type low-dose region is disposed to be separated from a p-type base region of the sensing effective region by an n?-type region between the p-type low-dose region and the sensing effective region. A total dose of impurities in the p-type low-dose region is lower than a total dose of impurities in a p-type region of a front side of a semiconductor substrate in a main effective region in which unit cells of the main semiconductor element are disposed.

Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a metal-including portion being conductive, an insulating portion, a gate electrode, a second electrode, a first interconnect layer, and a second interconnect layer. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region and the metal-including portion are provided on portions of the second semiconductor region. The insulating portion is arranged in a second direction with the third semiconductor region, the second semiconductor region, and a portion of the first semiconductor region. The gate electrode and the second electrode are provided inside the insulating portion. The first interconnect layer is electrically connected to the gate electrode.

Abstract: The present disclosure relates to a structure comprising, in a trench of a substrate, a first conductive region separated from the substrate by a first distance shorter than approximately 10 nm; and a second conductive region extending deeper than the first region.

Abstract: A silicon carbide substrate includes a first impurity region having a first conductivity type, a second impurity region having a second conductivity type, a third impurity region having the first conductivity type, and a fourth impurity region provided between a second main surface and a bottom surface and having the second conductivity type. The first impurity region has a first region being in contact with the second impurity region and having a first impurity concentration, a second region being continuous to the first region, provided between the first region and the second main surface, and having a second impurity concentration lower than the first impurity concentration, and a third region being continuous to the first region and having a third impurity concentration higher than the first impurity concentration. A side surface is in contact with the third region, the second impurity region, and the third impurity region.

Abstract: A silicon carbide semiconductor device includes plural p-type silicon carbide epitaxial layers provided on an n+-type silicon carbide substrate. In some of the p-type silicon carbide epitaxial layers, an n+ source region is provided in at least a region of an upper portion. The n+ source region includes a first portion that contains arsenic and a second portion that contains phosphorous.

Abstract: A semiconductor device includes a gate structure disposed over a channel region, a source/drain epitaxial layer disposed at a source/drain region, a nitrogen containing layer disposed on the source/drain epitaxial layer, a silicide layer disposed on the nitrogen containing layer, and a conductive contact disposed on the silicide layer.

Abstract: A method includes forming a trench over a substrate, wherein the trench is surrounded by gate spacers and an inter-layer dielectric layer, depositing a dielectric layer on a bottom and along sidewalls of the trench, depositing a metal layer over the dielectric layer, depositing a protection layer over the metal layer, wherein the protection layer has an uneven thickness, applying an etch-back process to the protection layer and the metal layer, wherein as a result of applying the etch-back process, a portion of the metal layer has been removed and at least a portion of the protection layer remains at the bottom of the trench and removing the protection layer from the trench.

Abstract: Plural gate trenches are formed on an upper surface side of a semiconductor substrate of a first conductivity type. Gate electrodes are embedded in the plural gate trenches. Plural dummy gate trenches are formed at equivalent intervals between the neighboring gate trenches on the upper surface side of the semiconductor substrate. Dummy gate electrodes are embedded in the plural dummy gate trenches and connected with an emitter electrode. An interval between the gate trench and the dummy gate trench that neighbor each other is shorter than an interval between the neighboring dummy gate trenches.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a transistor. The transistor includes a first source/drain (S/D) region, a second S/D region and a gate structure. The first S/D region is defined in a first well on a double diffusion layer, wherein the first well and the double diffusion layer define a diode at a junction therebetween, wherein an anode of the diode and the first S/D region form an open circuit therebetween. The gate structure is between the first S/D region and the second S/D region.

Abstract: A second source portion having an impurity concentration lower than that of a first source portion, both forming a source region, includes a first sub-portion having a depth from a bottom surface of the first source portion down to a second height higher than a first height, and a second sub-portion having an upper surface in contact with a part of a bottom surface of the first sub-portion, one side surface in a second direction perpendicular to a first direction in contact with an outer side surface of the trench, another side surface in the second direction, both side surfaces in the first direction, and a bottom surface in contact with the base layer, and having a depth from a bottom surface of the first sub-portion up to at least the first height.

Abstract: A semiconductor device includes a region of semiconductor material comprising a semiconductor layer of a first conductivity type and having a first major surface. A body region of a second conductivity type opposite to the first conductivity type is disposed in the second semiconductor layer extending from the first major surface. The body region comprises a first segment having a first doping concentration, and a second segment laterally adjacent to the first segment and adjacent to the first major surface having a second doping concentration less than the first doping concentration. A source region of the first conductivity type is disposed in the first segment but is not disposed in at least a portion of the second segment. An insulated gate electrode is disposed adjacent to the region of semiconductor material adjoining the first segment, the second segment, and the source region. A conductive layer is electrically connected to the first segment, the second segment, and the first source region.

Abstract: This disclosure relates to a power semiconductor device and a method of manufacturing the same, including: a semiconductor layer defining a first major surface and a drift region and a trench extending from the first major surface into the semiconductor layer. The trench includes a gate electrode surrounded by a gate dielectric configured and arranged to electrically isolate the gate electrode from the semiconductor layer; and a source region extending from the first major surface and abutting a top side-wall portion of the trench, and the source region extends to a depth corresponding to a top surface of the gate electrode.

Abstract: This invention discloses a semiconductor power device formed on an upper epitaxial layer of a first conductivity type supported on a semiconductor substrate comprises an active cell area and a termination area disposed near edges of the semiconductor substrate. The semiconductor power device having a super junction structure with the epitaxial layer formed with a plurality of doped columns of a second conductivity type. The termination area further comprises a plurality of surface guard ring regions of the second conductivity type dispose near a top surface of the epitaxial layer close to the doped columns of the second conductivity type. In one of the embodiments, one of the surface guard ring regions extending laterally over several of the doped columns in the termination area.

Abstract: Semiconductor device with multiple independent gates. A gate-controlled semiconductor device includes a first plurality of cells of the semiconductor device configured to be controlled by a primary gate, and a second plurality of cells of the semiconductor device configured to be controlled by an auxiliary gate. The primary gate is electrically isolated from the auxiliary gate, and sources and drains of the semiconductor device are electrically coupled in parallel. The first and second pluralities of cells may be substantially identical in structure.

Abstract: The present technology relates to an imaging element, an imaging device, and a manufacturing apparatus and a method that facilitate electric charge transfer. An imaging element of the present technology includes a vertical transistor that has a potential with a gradient in at least part of a charge transfer channel that transfers electric charge of a photoelectric conversion unit. Also, an imaging device of the present technology includes: an imaging element including a vertical transistor that has a potential with a gradient in at least part of a charge transfer channel that transfers electric charge of a photoelectric conversion unit; and an image processing unit that performs image processing on captured image data obtained by the imaging element.

Abstract: The present disclosure provides a semiconductor memory structure and a method for preparing the semiconductor memory structure. The semiconductor memory structure includes a substrate, a gate structure, a drain stressor and a source stressor. The gate structure is disposed in the substrate. Each of the source stressor and the drain stressor includes a strained part disposed in the substrate.

Abstract: A semiconductor device includes a substrate, first, second, third and fourth bottom contacts in the substrate, and first, second, third and fourth active fins on respective ones of the first, second, third and fourth bottom contacts, the second and third fins overlapping in a first direction. First, second and third gate electrodes extend longitudinally in the first direction, the first and second gate electrodes disposed on side surfaces of respective ones of the first and fourth active fins and the third gate electrode disposed on side surfaces of the second and third active fins. A first top contact is on the first and second active fins and a second top contact is on the third and fourth active fins.

Abstract: A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side, a plurality of gate electrodes that are arranged at intervals on the first main surface of the semiconductor layer, an interlayer insulating film that is formed on the first main surface of the semiconductor layer such as to cover the gate electrodes, an electrode film that is formed on the interlayer insulating film, and a plurality of tungsten plugs that, between a pair of the gate electrodes that are mutually adjacent, are respectively embedded in a plurality of contact openings formed in the interlayer insulating film at intervals in a direction in which the pair of mutually adjacent gate electrodes face each other and each have a bottom portion contacting the semiconductor layer and a top portion contacting the electrode film.

Abstract: Systems and methods of optimizing a gate profile for performance and gate fill are disclosed. A semiconductor device having an optimized gate profile includes a semiconductor substrate and a fin extending above the semiconductor substrate. A pair of source and drain regions are disposed on opposite sides of a channel region. A gate stack is disposed over the channel region, where the gate stack includes a top portion separated from a bottom portion by a tapered portion. The top portion and at least a portion of the tapered portion are disposed above the fin.

Abstract: A method of manufacturing a super junction structure includes etching a material to define a trench, wherein the trench has a tapered profile. The method further includes implanting dopants into sidewalls and a bottom surface of the trench to define a doped region, wherein the doped region surrounds the trench. The method further includes depositing an undoped material into the trench. The method further includes performing a thermal process, wherein the thermal process drives the dopants from the doped region into the undoped material to form a conductive pillar in the trench.

Abstract: A semiconductor device may include active patterns extended in a first direction and spaced apart from each other in the first direction, a device isolation layer defining the active patterns, an insulating structure provided between the active patterns and between the device isolation layer, and a gate structure disposed on the insulating structure and extended in a second direction crossing the first direction. The gate structure may include an upper portion and a lower portion. The lower portion of the gate structure may be enclosed by the insulating structure.

Abstract: An embodiment of a semiconductor device includes a semiconductor mesa in an active device area. The semiconductor mesa includes source regions arranged along a longitudinal direction of the semiconductor mesa and separated from one another along the longitudinal direction. The semiconductor device further includes an electrode trench structure including a dielectric and an electrode. The electrode trench structure adjoins a side of the semiconductor mesa. The semiconductor device further includes an isolation trench structure filled with one or more insulating materials. The isolation trench structure extends through the semiconductor mesa and into or through the electrode trench structure along a first lateral direction.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first source/drain structure and a second source/drain structure in the substrate. The semiconductor device structure includes a gate stack over the substrate and between the first source/drain structure and the second source/drain structure. The gate stack includes a gate dielectric layer and a gate over the gate dielectric layer, a portion of the gate dielectric layer is adjacent to a first sidewall of the gate, the gate stack has a gap between the first sidewall and the portion of the gate dielectric layer, and the gap is a vacuum gap or an air gap.

Abstract: A semiconductor device includes a semiconductor layer that has a first surface and a second surface, a trench that is formed at the first surface of the semiconductor layer and that extends in a first direction, an element portion that has a first-conductivity-type first region, a second-conductivity-type second region, and a third-conductivity-type third region that are formed in order along a depth direction of the trench from the first surface of the semiconductor layer, a gate insulating film formed at an inner surface of the trench, and a gate electrode that is embedded in the trench and that faces the first region, the second region, and the third region through the gate insulating film.

Abstract: A method and a transistor device are disclosed. The method includes: forming first regions of a first doping type and second regions of a second doping type in an inner region and an edge region of a semiconductor body; and forming body regions and source regions of transistor cells in the inner region of the semiconductor body. Forming the first regions and second regions includes: forming semiconductor layers one on top of the other; and in each of the semiconductor layers and before forming a respective next one of the semiconductor layers, forming trenches in the inner region and the edge region and implanting dopant atoms into a first sidewall and a second sidewall of each trench. Implanting the dopant atoms into at least one of the semiconductor layers includes partly covering the trenches in the edge region during an implantation process.

Abstract: A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.

Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating first tiers and second tiers. A first insulator tier is above the stack. First insulator material of the first insulator tier comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Channel-material strings are in the stack and in the first insulator tier. Conducting material is in the first insulator tier directly against sides of individual of the channel-material strings. A second insulator tier is formed above the first insulator tier and the conducting material. Second insulator material of the second insulator tier comprises at least one of the (a) and the (b). Conductive vias are formed and extend through the second insulator tier and that are individually directly electrically coupled to the individual channel-material strings through the conducting material.

Abstract: In an embodiment, a semiconductor device is provided. The semiconductor device includes: a semiconductor body of a first conductivity type having opposing first and second major surfaces; a gate arranged in a trench extending into the semiconductor body from the first major surface; a body region of a second conductivity type; a source region of the first conductivity type arranged on the body region and having first and second dopant species. The source region forms a pn-junction with the body junction, the pn-junction being arranged at a depth dpn from the first major surface, wherein 50 nm<dpn<300 nm. A drain region of the first conductivity type is arranged in the semiconductor body under the trench.

Abstract: SiC Schottky rectifier 100 with surge current ruggedness. As referenced above, the Schottky rectifier 100 may be configured to provide multiple types of surge current protection.