Abstract: A semiconductor device, including a first semiconductor layer of the first conductivity type formed on a semiconductor substrate, a first semiconductor region of the first conductivity type, a first base region and a first base region, both of a second conductivity type, selectively provided in the first semiconductor layer, a second semiconductor layer of the second conductivity type provided on the first semiconductor layer, a second semiconductor region of the first conductivity type selectively provided in the second semiconductor layer, a trench penetrating the second semiconductor layer and the second semiconductor region, a gate electrode provided in the trench, an interlayer insulating film provided on the gate electrode, a second base region in contact with a bottom of the trench, a first electrode in contact with the second semiconductor layer and the second semiconductor region, and a second electrode provided on the back of the semiconductor substrate.

Abstract: A semiconductor device includes: a first semiconductor layer of first conductivity type; a second semiconductor layer of first conductivity type provided on the first semiconductor layer; a first semiconductor region of second conductivity type provided on the second semiconductor layer; a second semiconductor region of first conductivity type provided on the first semiconductor region; a first electrode provided in a first trench, the first trench reaching the second semiconductor layer from above the first semiconductor region, the first electrode facing the first semiconductor region via a first insulating film; a second electrode provided in a second trench, the second trench reaching the second semiconductor layer from above the first semiconductor region, the second electrode facing the first semiconductor region via a second insulating film; a third electrode including a first electrode portion, a second electrode portion provided on the first electrode portion and a third electrode portion provided on

Abstract: A semiconductor memory device may include a first electrode and a second electrode, which are spaced apart from each other in a first direction, and a first semiconductor pattern, which is in contact with both of the first and second electrodes. The first semiconductor pattern may include first to fourth sub-semiconductor patterns, which are sequentially disposed in the first direction. The first and fourth sub-semiconductor patterns may be in contact with the first and second electrodes, respectively. The first and third sub-semiconductor patterns may be of a first conductivity type, and the second and fourth sub-semiconductor patterns may be of a second conductivity type different from the first conductivity type. Each of the first to fourth sub-semiconductor patterns may include a transition metal and a chalcogen element.

Abstract: Transistors include a pyramid-shaped gate trench defined by a triangular shape or a trapezoidal shape in a channel width plane and a trapezoidal shape in a channel length plane. Side wall portions of the pyramid-shaped gate trench form a channel having a triangular shape or a trapezoidal shape in the channel width plane. Advantageously, such transistors increase transconductance without increasing pixel width. Devices, image sensors, and pixels incorporating such transistors are also provided, in addition to methods of manufacturing the same.

Abstract: A DRAM and its manufacturing method are provided. The DRAM includes a buried word line, a first dielectric layer, a bit line, and a bit line contact structure. The buried word line is formed in a word line trench of the substrate, and extends along a first direction. The first dielectric layer is formed in the word line trench, located on the buried word line, and has a top surface lower than the top surface of the substrate. The bit line contact structure is formed on the substrate, and has a bottom surface higher than the top surface of the first dielectric layer. The bit line is formed on the substrate and extends along a second direction perpendicular to the first direction.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side, a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer, a trench source structure including a source trench formed deeper than the gate trench and across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a deep well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, a ratio of a depth of the trench source structure with respect to a depth of the trench gate structure being not less than 1.5 and not more than 4.

Abstract: Provided are a semiconductor element and a semiconductor device capable of achieving on-resistance reduction and miniaturization. The semiconductor element is used in a semiconductor switch for protecting an electric circuit, and includes a semiconductor substrate SB, a MOS transistor Tr provided on the semiconductor substrate SB, and a source electrode SE provided on a front surface 2a side of the semiconductor substrate SB. The MOS transistor Tr includes an n-type source region 8 connected to the source electrode SE, an n-type drift region 21 arranged away from the source region 8, and a p-type well region 31 arranged between the source region 8 and the drift region 21. The source region 8 is interposed between the source electrode SE and the well region 31.

Abstract: The present disclosure relates to a fabricating method of a semiconductor memory device including the following steps. Firstly, a substrate is provided, and a plurality of gate structures is formed in the substrate, with each of the gate structures being parallel with each other and extending along a first direction. Next, a plurality of isolation fins is formed on the substrate, wherein each of the isolation fins is parallel with each other and extends along the first direction, over each of the gate structures respectively. After forming the isolation fins, at least one bit line is formed on the substrate, extending along a second direction being perpendicular to the first direction, wherein the at least one bit line comprises a plurality of pins extending along a direction being perpendicular to the substrate, and each of the pins is alternately arranged with each of the isolation fins along the second direction.

Abstract: A GaN single crystal having a gallium polar surface which is a main surface on one side and a nitrogen polar surface which is a main surface on the opposite side, wherein on the gallium polar surface is found at least one square area, an outer periphery of which is constituted by four sides of 2 mm or more in length, and, when the at least one square area is divided into a plurality of sub-areas each of which is a 100 ?m×100 ?m square, pit-free areas account for 80% or more of the plurality of sub-areas.

Abstract: There is provided a semiconductor device including: a semiconductor layer including a main surface; a plurality of trenches including a plurality of first trench portions and a plurality of second trench portions, respectively; an insulating layer formed in an inner wall of each of the second trench portions; a first electrode buried in each of the second trench portions with the insulating layer interposed between the first electrode and each of the second trench portions; a plurality of insulators buried in the first trench portions so as to cover the first electrode; a contact hole formed at a region between the plurality of first trench portions in the semiconductor layer so as to expose the plurality of insulators; and a second electrode buried in the contact hole.

Abstract: Transistors having nonplanar electron channels in the channel width plane have one or more features that cause the different parts of the nonplanar electron channel to turn on at substantially the same threshold voltage. Advantageously, such transistors have substantially uniform threshold voltage across the nonplanar electron channel. Devices, image sensors, and pixels incorporating such transistors are also provided, in addition to methods of manufacturing the same.

Abstract: The present disclosure provides a method for preparing a semiconductor memory device with air gaps between conductive features. The method includes forming an isolation layer defining a first active region in a substrate; forming a first doped region in the first active region; forming a first word line buried in a first trench adjacent to the first doped region; and forming a high-level bit line contact positioned on the first doped region; forming a first air gap surrounding the high-level bit line contact. The forming of the first word line comprises: forming a lower electrode structure and an upper electrode structure on the lower electrode structure. The forming of the upper electrode structure comprises: forming a source layer substantially covering a sidewall of the first trench; forming a conductive layer on the source layer; and forming a work-function adjustment layer disposed between the source layer and the conductive layer.

Abstract: An apparatus comprises active word lines extending within a semiconductive material, passing word lines extending adjacent to the active word lines within the semiconductive material, isolation regions adjacent to the passing word lines, and a band offset material adjacent to the passing word lines and the isolation regions. The semiconductive material exhibits a first bandgap and the band offset material exhibits a second, different bandgap. Related methods and systems are also described.

Abstract: There is provided a semiconductor device having enhanced operation performance by utilizing a cut region where a gate cut is implemented. There is provided a semiconductor device comprising a first active pattern, a second active pattern, a third active pattern, and a fourth active pattern, all of which extend in parallel in a first direction, and are arranged along a second direction intersecting the first direction; a first gate electrode extended in the second direction on the first to fourth active patterns a first cut region extended in the first direction between the first active pattern and the second active pattern to cut the first gate electrode and a second cut region extended in the first direction between the third active pattern and the fourth active pattern to cut the first gate electrode, wherein one or more first dimensional features related to the first cut region is different from one or more second dimensional features related to the second cut region.

Abstract: The disclosure provides a superjunction IGBT (insulated gate bipolar transistor) device, wherein a carrier storage layer of a first conductivity type is provided between a voltage sustaining layer and a base region, and a MISFET (metal-insulator-semiconductor field effect transistor) of a second conductivity type is also integrated in a cell, with at least one gate of the MISFET is connected to the emitter contact thereof. The MISFET is turned off at a low forward conduction voltage, helping to reduce the conduction voltage drop. The MISFET can provide a path for carriers of a second conductivity type and prevent the carrier storage layer from suffering a high electric field when the forward conduction voltage is slightly higher or it is at the forward blocking state, helping to improve the reliability.

Abstract: A semiconductor device is disclosed that includes a group of trenches positioned in active region inside a first semiconductor region. A first trench is positioned in an outer peripheral region on an outer side of an active region. A second trench is positioned on an outer side of the first trench positioned in the outer peripheral region on the outer side of the active region. A mesa portion is positioned between the first and the second trenches. An insulating layer is positioned inside the first and second trenches. A second field plate is positioned inside the insulating layer in the first trench. A third field plate positioned inside the second insulating layer in the second trench. The mesa portion includes the semiconductor region electrically coupled to the first main electrode on an outermost side. The first trench does not have the gate electrode at upper part of the first trench.

Abstract: A semiconductor device includes a first transistor, a second transistor, a third electrode, and a control layer. The first transistor includes a first region of a semiconductor layer, a first electrode, and a first gate electrode. The first electrode is electrically connected with the first region. The first gate electrode is located in the first region. The second transistor includes a second region of the semiconductor layer, a second gate electrode, and a second electrode. The second region is next to the first region. The second gate electrode is located in the second region. The second electrode is electrically connected with the second region. The third electrode is electrically connected with the first and second transistors. The control layer has a smaller linear expansion coefficient than the third electrode.

Abstract: A method of forming a semiconductor device includes forming a first dummy gate structure and a second dummy gate structure over a fin; forming a first dielectric layer around the first dummy gate structure and around the second dummy gate structure; removing the first dummy gate structure and the second dummy gate structure to form a first recess and a second recess in the first dielectric layer, respectively; forming a gate dielectric layer in the first recess and the second recess; forming a first work function layer over the gate dielectric layer in the first and the second recesses; removing the first work function layer from the first recess; converting a surface layer of the first work function layer in the second recess into an oxide; and forming a second work function layer in the first recess over the gate dielectric layer and in the second recess over the oxide.

Abstract: Provided is a method of forming a trench gate MOSFET. A hard mask layer is formed on a substrate. The substrate is partially removed by using the hard mask layer as a mask, so as to form a trench in the substrate. A first insulating layer and a first conductive layer are formed in the lower portion of the trench. A sacrificial layer is formed on the side surface of the upper portion of the trench, and the sacrificial layer is connected to the hard mask layer. An interlayer insulating layer is formed on the first conductive layer by a thermal oxidation process when the sacrificial layer and the hard mask layer are present. A second insulating layer and a second conductive layer are formed in the upper portion of the trench. A trench gate MOSFET is further provided.

Abstract: A semiconductor device includes an electrical device and has an output capacitance characteristic with at least one output capacitance maximum located at a voltage larger than 5% of a breakdown voltage of the semiconductor device. The output capacitance maximum is larger than 1.2 times an output capacitance at an output capacitance minimum located at a voltage between the voltage at the output capacitance maximum and 5% of a breakdown voltage of the semiconductor device.

Abstract: A semiconductor device includes a semiconductor body having a first surface and second surface opposite to the first surface in a vertical direction, and a plurality of transistor cells at least partly integrated in the semiconductor body. Each transistor cell includes at least two source regions, first and second gate electrodes spaced apart from each other in a first horizontal direction and arranged adjacent to and dielectrically insulated from a continuous body region, a drift region separated from the at least two source regions by the body region, and at least three contact plugs extending from the body region towards a source electrode in the vertical direction. The at least three contact plugs are arranged successively between the first and second gate electrodes. Only the two outermost contact plugs that are arranged closest to the first and second gate electrodes, respectively, directly adjoin at least one of the source regions.

Abstract: A microelectronic device comprises a semiconductive pillar structure comprising a central portion, a first end portion, and a second end portion on a side of the central portion opposite the first end portion, the first end portion oriented at an angle with respect to the central portion and extending substantially parallel to the second end portion, a digit line contact on the central portion of the semiconductive pillar structure, a first storage node contact on the first end portion, and a second storage node contact on the second end portion. Related microelectronic devices, electronic systems, and methods are also described.

Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first to third semiconductor regions, a structure body, and a gate electrode. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided selectively on the second semiconductor region. The structure body includes an insulating part and a conductive part. The insulating part is arranged with the third and second semiconductor regions, and a portion of the first semiconductor region. The conductive part is provided in the insulating part. The conductive part includes a portion facing the first semiconductor region. The gate electrode faces the second semiconductor region. The second electrode is provided on the second and third semiconductor regions, and the structure body. The second electrode is electrically connected to the second and third semiconductor regions, and the conductive part.

Abstract: A method for creating a flat optical structure is disclosed, having steps of providing a substrate, etching at least one nanotrench in the substrate, placing a dielectric material in the at least one nanotrench in the substrate and encapsulating a top of the substrate with a film.

Abstract: The present disclosure provides a method for forming a semiconductor device with an air gap for reducing the parasitic capacitance between two conductive features. The method includes forming a first source/drain region and a second source/drain region in a semiconductor substrate, and forming a first conductive feature over and electrically connected to the first source/drain region. The method also includes forming a first spacer structure on a sidewall of the first conductive feature, and forming a second conductive feature over and electrically connected to the second source/drain region. The second conductive feature is adjacent to the first spacer structure, and the first spacer structure is etched during the forming the second conductive feature. The method further includes forming a second spacer structure over the etched first spacer structure, and performing a heat treatment process to transform a portion of the first spacer structure into an air gap.

Abstract: A semiconductor device has an active region through which current passes and an edge termination structure region. On a front surface of a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type is provided. On a surface of the first semiconductor layer, a parallel pn structure including first columns of the first conductivity type and second columns of a second conductivity type disposed to repeatedly alternate one another is provided. The second columns in the active region include first regions and second regions. A distance from the front surface of the semiconductor substrate to a bottom surface of one of the first regions is greater than a distance from the front surface of the semiconductor substrate to a bottom surface of one of the second regions.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a storage capacitor, an access transistor, and at least one conductive feature for electrically coupling the storage capacitor to the access transistor. The substrate includes at least one isolation feature defining a plurality of active regions, wherein a plurality of impurity regions of the access transistor are in the active region. The storage capacitor is disposed over the substrate, and the conductive feature extends from the storage capacitor and into a portion of the substrate where one of the impurity regions is disposed. As a result, a contact area between the access transistor and the conductive feature is increased, and an operation speed of the compact semiconductor device is increased.

Abstract: According to one embodiment, a semiconductor device includes first, second, and third conductive members, a semiconductor member, and a first insulating member. The semiconductor member includes a first semiconductor region provided on the first conductive member, a second semiconductor region provided on a portion of the first semiconductor region, and a third semiconductor region provided on the second semiconductor region. An impurity concentration in the third semiconductor region is greater than in the first semiconductor region. The second conductive member includes a first conductive portion electrically connected to the second and third semiconductor regions. The third conductive member is provided on an other portion of the first semiconductor region. At least a portion of the first insulating member is between the semiconductor member and the third conductive member.

Abstract: A semiconductor device includes a substrate including a first region and a second region, a first silicon-germanium film which is conformally formed inside a surface of the substrate of the first region and defines a first gate trench, a first gate insulating film which extends on the first silicon-germanium film along a profile of the first gate trench and is in physical contact with the first silicon-germanium film, a first metallic gate electrode on the first gate insulating film, a source/drain region formed inside the substrate on both sides of the first metallic gate electrode, a second gate insulating film in the second region and a second metallic gate electrode on the second gate insulating film.

Abstract: A SGT MOSFET having two stepped oxide (TSO) structure in gate trench is disclosed, wherein the TSO has thinner oxide thickness along upper sidewalls of the gate trench than along lower sidewalls of the gate trench. The BV can be enhanced as result of the electric filed reduction near channel region, on-resistance is thus reduced. The present invention further comprises a super junction region below the oxide charge balance region, making vertical electrical field more uniform, the BV is further enhanced and on-resistance is further reduced.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; an insulating material at least partially above the fin, wherein the insulating material includes a trench above the fin; and a gate metal on the insulating material and extending into the trench.

Abstract: A semiconductor device includes a semiconductor part; first and second electrodes respectively on back and front surfaces of the semiconductor part; third and fourth electrodes inside a trench of the semiconductor part, the fourth electrode being provided between the first electrode and the third electrode; a first insulating portion electrically insulating the third electrode from the semiconductor part; a second insulating portion electrically insulating the third electrode from the second electrode; a third insulating portion electrically insulating the fourth electrode from the semiconductor part; a fourth insulating portion electrically insulating the fourth electrode from the third electrode; and a fifth insulating portion including a first portion and a second portion, the first portion being provided inside the fourth electrode, the second portion extending outward of the fourth electrode.

Abstract: According to one embodiment, a semiconductor device includes a first electrode, first and third semiconductor regions of a first conductivity type, second and fourth semiconductor regions of a second conductivity type, a gate electrode and a second electrode. The third semiconductor region is disposed on one portion of the second semiconductor region. The fourth semiconductor region is disposed on another portion of the second semiconductor region, is positioned below the third semiconductor region. The second electrode includes first and second portions separated from each other and allowing the fourth semiconductor region to be positioned therebetween, and the third portion disposed on the first and second portions and arranged with the third semiconductor region. The first, second, and third portions are in contact with the fourth semiconductor region.

Abstract: A method of manufacturing a trench MOSFET can include: forming a trench extending from an upper surface of a semiconductor base layer to internal portion of the semiconductor base layer; forming a first insulating layer covering sidewall and bottom surfaces of the trench and the upper surface of the semiconductor base layer; forming a shield conductor filling a lower portion of the trench, where the first insulating layer separates the shield conductor from the semiconductor base layer; forming a second insulating layer covering a top surface of the shield conductor, where the first insulating layer separates the second insulating layer from the semiconductor base layer, and the first and second insulating layers conformally form a dielectric layer; and removing the dielectric layer located on the upper surface of the semiconductor base layer and located on the upper sidewall surface of the trench.

Abstract: A method including forming an inter-layer insulation layer on a substrate, forming a plug material penetrating the inter-layer insulation layer and contacting a portion of the substrate, forming a contact plug by etching the plug material, forming a trench exposing a side wall of the contact plug by etching the substrate and the inter-layer insulation layer to be aligned with a side wall of the contact plug, forming a gate insulation layer on a surface of the trench and the exposed side wall of the contact plug, and forming a gate electrode partially filling the trench on the gate insulation layer. The method includes an inter-layer insulation layer formed on a substrate, a contact plug penetrating the inter-layer insulation layer and contacting a portion of the substrate, trenches extending in a line shape and aligned with side walls of the contact plug, and a plug spacer positioned between the trenches and surrounding the contact plug.

Abstract: A method (200) of fabricating a semiconductor device includes etching (205) a group of trenches in a semiconductor surface layer of a substrate. The group of trenches includes an outermost trench that has a first width and remaining trenches of the group of trenches have a second width that is less than the first width. The outermost trench is formed at an edge of the group of trenches. A dielectric liner is formed (210) in the group of trenches and the dielectric liner is etched (215) in an upper portion of the group of trenches to remove a partial thickness of the dielectric liner. A full thickness of the dielectric liner is maintained in a lower portion of the group of trenches. The group of trenches is filled (220) with a polysilicon layer.

Abstract: A field effect transistor has a semiconductor layer with a top surface extending in a horizontal plane, and an active area defined in which are trench gate regions, which extend in depth with respect to the top surface and have an insulating coating layer and a conductive inner layer, and source regions, adjacent to the trench gate regions so as to form a conductive channel extending vertically. The trench gate regions have a plurality of first gate regions, which extend in length in the form of stripes through the active area along a first direction of the horizontal plane, and moreover a plurality of second gate regions, which extend in length in the form of stripes through the same active area along a second direction of the horizontal plane, orthogonal to, and crossing, the first gate regions. In particular, the first gate regions and second gate regions cross in the active area, joining with a non-zero curvature radius.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type, a first semiconductor portion of a second conductivity type provided in the semiconductor layer, first and second conductive members, each having an upper end reaching an upper surface of the semiconductor layer and a lower end connected to the first semiconductor portion, and first and second insulating films covering side surfaces of the first and second conductive members, respectively. A length from the upper end to the lower end of the first conductive member is greater than a total of a length of the first conductive member, a distance between the first conductive member and the second conductive member, and a length of the second conductive member in a direction from the first conductive member toward the second conductive member that is parallel to the upper surface of the semiconductor layer.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The method includes forming a plurality of bit line structures on a semiconductor substrate, wherein there is a plurality of trenches between the bit line structures. The method also includes forming a first oxide layer conformally covering the bit line structures and the trenches, and forming a photoresist material layer in the trenches and on the first oxide layer, wherein the photoresist material layer has an etch selectivity that is higher than that of the first oxide layer. The method further includes removing the photoresist material layer to form a plurality of capacitor contact holes between the bit line structures, and forming a capacitor contact in the capacitor contact holes.

Abstract: A MOSFET is made by: forming a trench extending from an upper surface of a base layer to an internal portion of the base layer; forming a first insulating layer and a shield conductor occupying a lower portion of the trench; forming a gate dielectric layer and a gate conductor occupying an upper portion of the trench, where a top surface of the gate conductor is lower than the upper surface of the base layer; and before forming a body region, forming a blocking region on a region of the top surface of the gate conductor adjacent to sidewalls of the trench to prevent impurities from being implanted into the base layer from the sidewalls of the trench during subsequent ion implantation.

Abstract: Semiconductor cell structure and forming method thereof are provided. The semiconductor cell structure includes: a substrate including a first section and third regions on both sides of the first section in a first direction; and a first gate structure group including one or more first gate structures on the substrate. The first section includes a first region and a second region aligned along the first direction in the first section. The first region and the second region are configured to form transistors have a type opposite to a type of transistors configured to be formed in the third regions. The one or more first gate structures extend along the first direction across the first region, the second region, and the third regions on both sides of the first section.

Abstract: A microelectronic device comprises a conductive structure, a metal nitride material, and a metal silicide material. The conductive structure comprises a first portion having a first width, and a second portion under the first portion and extending into a semiconductive material. The second portion has a tapered profile defining additional widths varying from the first width at an upper boundary of the second portion to a second width less than the first width at a lower boundary of the second portion. The metal nitride material substantially surrounds outer surfaces of the first portion and the second portion of the conductive structure. The metal silicide material substantially covers outer surfaces of the metal nitride material within vertical boundaries of the second portion of the conductive structure. Related methods, memory devices, and electronic systems are also described.

Abstract: A semiconductor device includes a substrate, a semiconductor fin, source region, a gate electrode, a source contact, and a source via. The semiconductor fin has a length extending above the substrate. The source region is on the semiconductor fin. The gate electrode has a length across the semiconductor fin. The source contact is above the source region. The source via lands on the source contact and has a first dimension along a lengthwise direction of the semiconductor fin and has a second dimension along a lengthwise direction of the gate electrode from a top view. A ratio of the second dimension to the first dimension of the source via is greater than about 2.

Abstract: A semiconductor device having an active region and a voltage withstand region comprises a first semiconductor layer of a first conductive type, a second semiconductor region of a second conductive type, disposed selectively on the front side of the first semiconductor layer, a plurality of first trench contact (TC) sections disposed at a peripheral section of the active region in the second semiconductor region, being apart from one another and extending in a first direction, a second trench contact (TC) disposed at the peripheral section of the active region in the second semiconductor region, extending in the first direction and being further from the voltage withstand region than the plurality of first trench contact sections, an electric conductor layer electrically connecting together the plurality of first TC sections, and a conductive connection region disposed between the first TC sections and second TC section, having a lower resistivity than the second semiconductor region, and electrically connecti

Abstract: This invention provides a novel structure formed from GaN material using PEC etching. The structure comprises a member constituted by a single crystal of gallium nitride and the member includes a recess having an aspect ratio of 5 or more.

Abstract: A semicondcutor device, and a method of fabricating the semiconductor device including forming on a substrate a device isolation layer defining a plurality of active regions; and forming a plurality of gate lines intersecting the active regions and buried in the substrate. The forming of the gate lines includes forming on the substrate a trench that intersects the active regions; forming a work-function control layer on a sidewall and a bottom surface of the trench; forming a conductive layer on the work-function control layer; sequentially forming a barrier layer and a source layer on the work-function control layer and the conductive layer, the source layer including a work-function control element; and diffusing the work-function control element from the source layer into an upper portion of the work-function control layer.

Abstract: A method for manufacturing a DRAM includes: forming a hard mask layer on a substrate with an opening therein; forming a dielectric layer on a sidewall of the opening; forming a first barrier layer and a first conductor layer in the opening; performing a first dry etching and a first wet etching processes to respectively partially remove the first barrier layer and the first conductor layer, to expose the dielectric layer on upper sidewall; forming a second barrier layer in the opening; forming a mask layer in the opening to cover the second barrier layer; removing a part of the second barrier layer and the mask layer to expose the dielectric layer on the upper sidewall of the opening; and forming a second conductor layer in the opening.

Abstract: There is provided a semiconductor device including: an anode electrode that is provided on a front surface side of a semiconductor substrate; a drift region of a first conductivity type that is provided in the semiconductor substrate; a first anode region of a first conductivity type that is in Schottky contact with the anode electrode; and a second anode region of a second conductivity type that is different from the first conductivity type, in which the first anode region has a doping concentration lower than or equal to a doping concentration of the second anode region, and is spaced from the drift region by the second anode region.

Abstract: A pixel cell includes a photodiode buried beneath a first side of semiconductor material and coupled to photogenerate image charge in response to incident light. A transfer gate is disposed over the photodiode and includes a vertical transfer gate portion extending a first distance from the first side into the semiconductor material. A floating diffusion region is disposed in the semiconductor material proximate to the transfer gate and is coupled to transfer the image charge from the photodiode toward the first side of the semiconductor material and into the floating diffusion region in response to a transfer control signal. A first pixel transistor having a first gate is disposed over the photodiode proximate to the first side of the semiconductor material. The first gate has a ring structure laterally surrounding the floating diffusion region and the transfer gate at the first side of the semiconductor material.

Abstract: A semiconductor device includes an active area structure, at least one gate and at least one isolation structure. The active area structure is arranged along a first direction. The at least one gate is arranged above the active area structure and along a second direction. The second direction is different from the first direction. The at least one isolation structure is arranged in the active area structure. A length of the at least one isolation structure is shorter than a width of the active area structure in the second direction.