Abstract: One embodiment of a semiconductor device includes a fin at a first side of a semiconductor body, a body region of a second conductivity type in at least a part of the fin, a drain extension region of a first conductivity type, a source region and a drain region of the first conductivity type, a source contact in contact with the source region, the source contact extending along a vertical direction along the source region, and a gate structure adjoining opposing walls of the fin. The body region and the drain extension region are arranged one after another between the source region and the drain region.

Abstract: In some embodiment, a fuse structure in a semiconductor device uses a metal fuse element connected to a stacked via fuse link connected to a thin film resistive element. The fuse structure can be incorporated in an integrated circuit for EOS protection. In other embodiments, an integrated EOS/ESD protection circuit includes a current limiting resistor integrated with an ESD protection circuit. In some embodiments, the current limiting resistor is formed in an N-well forming the collector of the ESD protection circuit.

Abstract: An ESD module includes an ESD circuit coupled between a first source and a second source. A trigger circuit is also included in the ESD module for activating the ESD circuit to provide a low resistance current path between the first and second sources. The trigger circuit includes a reverse diode between the first source and the ESD circuit or between the second source and main ESD circuit. The trigger circuit provides a low trigger voltage to activate the ESD circuit.

Abstract: A method of forming a metal gate diode ESD protection device and the resulting device are provided. Embodiments include forming a metal gate diode including a metal gate on a substrate; forming an n-type cathode on a first side of the metal gate diode; and forming a p-type anode on a second side of the metal gate diode, opposite the first side.

Abstract: Embodiments of an integrated resistor may be incorporated into monolithic transistor circuits and packaged RF amplifier devices. An embodiment of an integrated resistor includes a semiconductor substrate and a resistor formed over the top surface of the semiconductor substrate from resistive material. The resistor includes at least first and second resistive sections. The first resistive section is tapered so that the first resistive section widens toward an input end of the resistor. The second resistive section is coupled in series with the first resistive section. According to a further embodiment, the second resistive section also is tapered so that the second resistive section widens toward an output end of the resistor. According to another further embodiment, a third resistive section with one or more meanders is coupled in series between the first and second resistive sections.

Abstract: There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.

Abstract: A semiconductor integrated circuit is provided. In the semiconductor integrated circuit, each of ESD protection circuitries is disposed between two of TSV bumps arrayed in a matrix, the two being arranged adjacent to each other. First main power lines are disposed to overlap P-channel ESD protection elements. Second main power lines are disposed to overlap N-channel ESD protection elements. The first and second main power lines are arranged orthogonally to each other.

Abstract: A semiconductor memory device includes a pair of bit lines connected to a plurality of memory cells, a first transistor connected between the pair of bit lines, a second transistor between at least one of the pair of bit lines and a first power supply voltage line, and a diffusion layer region shared between the first transistor and the second transistor, and connected to the one of the pair of bit lines. A gate of the first transistor and a gate of the second transistor are connected to each other. A gate of the first transistor is provided such that both a direction of a gate width of the first transistor and a direction of a gate width of second transistor are on one identical extension line.

Abstract: According to one embodiment, a semiconductor storage device includes a nonvolatile semiconductor memory and a controller. The nonvolatile semiconductor memory includes a firmware area capable of storing firmware used to execute either a normal mode or an autorun test mode and a user area capable of storing user data. The controller reads the firmware from the nonvolatile semiconductor memory and determines whether the firmware has been set in either the normal mode or the autorun test mode. The controller repeats erasing, writing, and reading in each block in the user area using a cell applied voltage higher than a voltage used in a normal mode, and enters a block where an error has occurred as a bad block.

Abstract: An integrated semiconductor device is provided. The integrated semiconductor device has a first semiconductor region of a second conductivity type, a second semiconductor region of a first conductivity type forming a pn-junction with the first semiconductor region, a non-monocrystalline semiconductor layer of the first conductivity type arranged on the second semiconductor region, a first well and at least one second well of the first conductivity type arranged on the non-monocrystalline semiconductor layer and an insulating structure insulating the first well from the at least one second well and the non-monocrystalline semiconductor layer. Further, a method for forming a semiconductor device is provided.

Abstract: The present disclosure relates to a method of generating a transistor device having an epitaxial layer disposed over a recessed active region. The epitaxial layer improves transistor device performance. In some embodiments, the method is performed by providing a semiconductor substrate. An epitaxial growth is performed to form an epitaxial layer onto the semiconductor substrate. An electrically insulating layer is then formed onto the epitaxial layer, and a gate structure is formed onto the electrically insulating layer. By forming the epitaxial layer over the semiconductor substrate the surface roughness of the semiconductor substrate is improved, thereby improving transistor device performance.

Abstract: Embodiments of the present invention generally provide a processing system for an input device including a sensor module having sensor circuitry. The sensor module may be coupled to transmitter electrodes, receiver electrodes, and a shield electrode. The sensor module may be configured for transmitting transmitter signals with the transmitter electrodes, receiving resulting signals with the receiver electrodes, and transitioning the shield electrode from a first voltage to a second voltage during a non-sensing time period. The resulting signals may include effects which correspond to the transmitter signals. The input device may further include a determination module configured for determining positional information for an input object based at least in part on the resulting signals.

Abstract: A motor control system includes an inverter and a plurality of current sensors each positioned in-line between the inverter and a phase coil of the motor. Each current sensor measures the current provided to each phase coil of the motor and provides a signal indicative of each phase current to a controller. In some embodiments, the currents sensors are provided as one or more current sense integrated circuits. A protection circuit protects the current sense integrated circuit from ground bounce by coupling a diode and an opposite facing Zener diode in series between the power supply pin and the ground pin of the integrated circuit.

Abstract: Technique capable of achieving reliability improvement of a semiconductor device even if temperature rising of an operation guarantee temperature of the semiconductor device is performed is provided. Gap portions are provided among a plurality of pads, and a glass coat composed of, for example, a silicon oxide film or a silicon nitride film is embedded in the gap portions. The glass coat is provided in order to secure electrical insulation among the pads, and coats outer edge portions of the pads. Trenches are formed so as to be adjacent to regions, which are coated with the glass coat, of the outer edge portions of the pads.

Abstract: Diffusion regions having the same conductivity type are arranged on a side of a second wiring and a side of a third wiring, respectively under a first wiring connected to a signal terminal. Diffusion regions are separated in a whole part or one part of a range in a Y direction. That is, under first wiring, diffusion regions are only formed in parts opposed to diffusion regions formed under the second wiring and third wiring connected to a power supply terminal or a ground terminal, and a diffusion region is not formed in a central part in an X direction. Therefore, terminal capacity of the signal terminal can be reduced without causing ESD resistance to be reduced, in an ESD protection circuit with the signal terminal.

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first well, a first heavily doping region, a field oxide, a first dielectric layer, and a conductive layer. The first well is disposed on the substrate, and the first heavily doping region is disposed in the first well. The field oxide is disposed on the first well and adjacent to the first heavily doping region. The first dielectric layer is disposed on the field oxide and covering the field oxide. The conductive layer is disposed on the first dielectric layer. The first well and the first heavily doping region have a first type doping.

Abstract: A semiconductor device for electrostatic discharge protection includes a substrate, a first well and a second well formed in the substrate. The first and second wells are formed side by side, meeting at an interface, and have a first conductivity type and a second conductivity type, respectively. A first heavily doped region and a second heavily-doped region are formed in the first well. A third heavily doped region and a fourth heavily-doped region are formed in the second well. The first, second, third, and fourth heavily-doped regions have the first, second, second, and first conductivity types, respectively. Positions of the first and second heavily-doped regions are staggered along a direction parallel to the interface.

Abstract: A device having a substrate defined with a device region is presented. The device region includes an ESD protection circuit having a transistor. The transistor includes a gate having first and second sides, a first diffusion region disposed adjacent to the first side of the gate and a second diffusion region displaced away from the second side of the gate. The device includes a first device well encompasses the device region and a second device well disposed within the first device well. The second device well encompasses the first diffusion region and at least a part of the gate. The device also includes a third well which is disposed within the second device well and a drain well which encompasses the second diffusion region and extends below the gate.

Abstract: A design rule checker that performs a maximum pattern density check in a first intermediary metallization layer that underlies a top metallization layer and a pad opening in an integrated circuit. The maximum pattern density check is performed at least under some circumstances if a modulus of the primary metallization material is less than a modulus of a surrounding dielectric material. The maximum pattern density check verifies that the pattern density within the underlying portion is below a maximum pattern density that depends on the thickness of the access pad. A maximum metal width check may also be performed in this portion.

Abstract: An electrostatic discharge protection device includes first and second wells of a first conductivity type, the first and second wells having different impurity doping concentrations, respectively, a gate formed on the first well, a source region of a second conductivity type formed at one side of the gate in the first well, a drift region of the second conductivity type formed at the other side of gate and over both of the first well and the second well, and a drain region of the second conductivity type formed in the drift region of the second well.

Abstract: A semiconductor apparatus and system including a semiconductor apparatus may include: a main pattern block having a plurality of main patterns formed to be coupled to a power source and one or more dummy pattern blocks formed around the main pattern block. Any one of the one or more dummy pattern blocks may include a protection part formed to protect the main pattern block.

Abstract: An integrated circuit includes an UTBOX insulating layer under and plumb with first and second electronic components, and corresponding ground planes and oppositely-doped wells made plumb with them. The wells contact with corresponding ground planes. A pair of oppositely doped bias electrodes, suitable for connecting corresponding bias voltages, contacts respective wells and ground planes. A third electrode contacts the first well. A first trench isolates one bias electrode from the third electrode and extends through the layer and into the first well. A second trench isolates the first bias electrode from one component. This trench has an extent that falls short of reaching an interface between the first ground plane and the first well.

Abstract: An electrostatic discharge protection device is disclosed. The electrostatic discharge protection device comprises a N+ well, a P doping region, a first N doping region, a plurality of N sub-doping regions, a first N+ doping region, a first P+ doping region, a second N+ doping region, and a second doping region. The P doping region is disposed in the N+ well. The first N doping region is disposed in the P doping region. The plurality of N sub-doping regions is disposed in parallel in the P doping region. The first N+ doping region is disposed in the first N doping region. The first P+ doping region is disposed in the first N doping region. The second N+ doping region is disposed in the P doping region.

Abstract: A stacked electrostatic discharge (ESD) protection device includes a substrate; a deep well with a first conductive type formed in the substrate, the deep well defining a plurality of element regions with a second conductive type therein; and a plurality of ESD protection elements, each of which is formed in one of the element regions. A current path is formed by connecting the plurality of ESD protection elements in series.

Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.

Abstract: Provided is a semiconductor device which uses a comb-like N-type MOS transistor as an ESD protection element and is capable of uniformly operating the entire comb-like N-type MOS transistor. By adjusting a length L of a gate electrode of the N-type MOS transistor used as the ESD protection element in accordance with the distance from a contact for fixing a substrate potential, which is provided on a guard ring around an outer periphery, respective portion of N-type MOS transistor represented as a comb teeth uniformly enter snap-back operation, permitting avoidance of local concentration of current and obtainment of a desired ESD tolerance.

Abstract: In a silicon-controlled rectifier, an anode region includes p-type anode well regions which are laterally surrounded by an n-type well region. A length of a p-type anode well region, as measured in a first direction, is greater than a width of the p-type anode well region, as measured in a second direction perpendicular to the first direction. A p-type well region meets the n-type well region at a junction, wherein the junction extends between the p-type well region and n-type well region in the second direction. A cathode region includes a plurality of n-type cathode well regions which are formed in the p-type well region. A length of an n-type cathode well region, as measured in the first direction, is greater than a width of the n-type cathode well region, as measured in the second direction.

Abstract: A semiconductor device capable of ensuring a withstand voltage of a transistor and reducing a forward voltage of a Schottky barrier diode in a package with the transistor and the Schottky barrier diode formed on chip, and a semiconductor package formed by a resin package covering the semiconductor device are provided. The semiconductor device 1 includes a semiconductor layer 22, a transistor area D formed on the semiconductor layer 22 and constituting the transistor 11, and a diode area C formed on the semiconductor layer 22 and constituting the Schottky barrier diode 10. The semiconductor layer 22 in the diode area C is thinner than the semiconductor layer 22 in the transistor area D.

Abstract: A power semiconductor device includes a cell region on a semiconductor substrate, at least a transistor device in the cell region, a peripheral termination region encompassing the cell region, a plurality of epitaxial islands arranged around the cell region, and a grid type epitaxial layer in the peripheral termination region. The grid type epitaxial layer separates the plurality of epitaxial islands from one another.

Abstract: In accordance with an embodiment, a semiconductor component includes a common mode filter monolithically integrated with a protection device. The common mode filter may be composed of first, second, third, and fourth coils, wherein each coil has first and second terminals and the first coil is magnetically coupled to the second coil and the third coil is magnetically coupled to the fourth coil. The protection device has a first terminal coupled to the first terminal of the first coil and a second terminal coupled to the first terminal of the third coil. An energy storage element has a terminal coupled to the second and first terminals of the first and second coils, respectively. Another embodiment includes monolithically integrating a common mode filter with a protection device and monolithically integrating a metal-insulator-metal capacitor with the common mode filter.

Abstract: An electrostatic discharge (ESD) protection structure and an ESD protection circuit are provided. A PMOS transistor is located in a first region of a first N-type well region of a semiconductor substrate. A first doped base region located in a second region of a first N-type well region is N-type doped and connected to an external trigger-voltage adjustment circuit. An NMOS transistor is located in a third region of a first P-type well region. A second doped base region located in the fourth region of the first P-type well region is P-type doped and connected to the external trigger-voltage adjustment circuit. The external trigger-voltage adjustment circuit can be configured to pull up an electric potential of the second doped base region when the power supply terminal generates an instantaneous electric potential difference.

Abstract: A display device includes a first insulation layer on a substrate, gate wires on the first insulation layer, the gate wires extending in a first direction, a second insulation layer on the gate wires, data wires on the second insulation layer, the data wires extending in a second direction crossing the first direction, pixels at intersection regions of gate wires and data wires, respectively, the pixels being connected to respective gate wires and data wires, and data leading diodes having an island form and connected to the data wires, the data leading diodes being configured to induce breakage of the first insulation layer when external static electricity passes through the data wires.

Abstract: A silicon controlled rectifier includes: a substrate; a N well and a P well positioned on a side of the substrate and contact with each other; a first N region and a first P region positioned on an upper surface of the N well and contact with each other; a second N region and a second P region positioned on an upper surface of the P well and contact with each other; a first oxide isolation region isolating the first P region and the second N region; a second oxide isolation region isolating the second N region and the second P region; an anode terminal coupled with the first N region and the first P region; and a cathode terminal coupled with the second N region and the second P region. The first P region has a doping concentration less than 80% of that of the second P region.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having an integrated circuit (IC) device; an interconnect structure disposed on the semiconductor substrate and coupled with the IC device; and a transformer disposed on the semiconductor substrate and integrated in the interconnect structure. The transformer includes a first conductive feature; a second conductive feature inductively coupled with the first conductive feature; a third conductive feature electrically connected to the first conductive feature; and a fourth conductive feature electrically connected to the second conductive feature. The third and fourth conductive features are designed and configured to be capacitively coupled to increase a coupling coefficient of the transformer.

Abstract: Snapback ESD protection device employing one or more non-planar metal-oxide-semiconductor transistors (MOSFETs) are described. The ESD protection devices may further include lightly-doped extended drain regions, the resistances of which may be capacitively controlled through control gates independent of a gate electrode held at a ground potential. Control gates may be floated or biased to modulate ESD protection device performance. In embodiments, a plurality of core circuits are protected with a plurality of non-planar MOSFET-based ESD protection devices with control gate potentials varying across the plurality.

Abstract: Technique capable of achieving reliability improvement of a semiconductor device even if temperature rising of an operation guarantee temperature of the semiconductor device is performed is provided. Gap portions are provided among a plurality of pads, and a glass coat composed of, for example, a silicon oxide film or a silicon nitride film is embedded in the gap portions. The glass coat is provided in order to secure electrical insulation among the pads, and coats outer edge portions of the pads. Trenches are formed so as to be adjacent to regions, which are coated with the glass coat, of the outer edge portions of the pads.

Abstract: [Theme] To provide a chip diode, with which a p-n junction formed on a semiconductor layer can be prevented from being destroyed and fluctuations in characteristics can be suppressed even when a large stress is applied to a pad for electrical connection with the exterior, and a diode package that includes the chip diode. [Solution] A chip diode 15 includes an epitaxial layer 21 with a p-n junction 28, constituting a diode element 29, formed therein, an anode electrode 34 disposed along a top surface 22 of the epitaxial layer 21, electrically connected to a diode impurity region 23, which is the p-side pole of the p-n junction 28, and having a pad 37 for electrical connection with the exterior, and a cathode electrode 41 electrically connected to the epitaxial layer 21, which is the n-side pole of the p-n junction 28, and the pad 37 is provided at a position separated from a position directly above the p-n junction 28.

Abstract: A vertical MOSFET electrostatic discharge device is disclosed, including a substrate comprising a plurality of trenches, a recessed gate disposed in each trench, a drain region disposed between each of the two neighboring recessed gates, an electrostatic discharge implant region disposed under each drain region, and a source region surrounding and disposed under the recessed gates and the electrostatic discharge implant regions.

Abstract: An electrical circuit, planar diode, and method of forming a diode and one or more CMOS devices on the same chip. The method includes electrically isolating a portion of a substrate in a diode region from other substrate regions. The method also includes recessing the substrate in the diode region. The method further includes epitaxially forming in the diode region a first doped layer above the substrate and epitaxially forming in the diode region a second doped layer above the first doped layer.

Abstract: A semiconductor integrated circuit is provided. In the semiconductor integrated circuit, each of ESD protection circuitries is disposed between two of TSV bumps arrayed in a matrix, the two being arranged adjacent to each other. First main power lines are disposed to overlap P-channel ESD protection elements. Second main power lines are disposed to overlap N-channel ESD protection elements. The first and second main power lines are arranged orthogonally to each other.

Abstract: A semiconductor device includes a body and a transistor fabricated into the body. Isolation material at least partially encases the body. Biasing is coupled to the isolation material, wherein the biasing is for changing the electric potential of the isolation material in response to an electrostatic discharge event.

Abstract: A semiconductor device includes a substrate, a gate positioned on the substrate, a drain region and a source region formed at respective two sides of the gate in the substrate, at least a first doped region formed in the drain region, and at least a first well having the first doped region formed therein. The source region and the drain region include a first conductivity type, the first doped region and the first well include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.

Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.

Abstract: A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages.

Abstract: A programmable semiconductor controlled rectifier (SCR) circuit is disclosed. The SCR includes a first terminal (310) and a second terminal (308). A first lightly doped region (304) having a first conductivity type (N?) is formed on a second lightly doped region (314) having a second conductivity type (P?). A first heavily doped region having the second conductivity type (P+) is formed within the first lightly doped region at a face of the substrate and coupled to the first terminal. A second heavily doped region having the first conductivity type (N+) is formed within the second lightly doped region at the face of the substrate and coupled to the second terminal. A third heavily doped region (400) having the second conductivity type (P+) is formed at the face of the substrate between the first and second heavily doped regions and electrically connected to the second lightly doped region.

Abstract: A semiconductor structure includes a substrate, a first well having a first conductive type, a second well having a second conductive type, a body region, a first doped region, a second doped region, a third doped region and a field plate. The first and second wells are formed in the substrate. The body region is formed in the second well. The first and second doped regions are formed in the first well and the body region, respectively. The second and first doped regions have the same polarities, and the dopant concentration of the second doped region is higher than that of the first doped region. The third doped region is formed in the second well and located between the first and second doped regions. The third and first doped regions have reverse polarities. The field plate is formed on the surface region between the first and second doped regions.

Abstract: One or more semiconductor devices with an electrostatic discharge (ESD) device and a functional device in a circular arrangement are provided herein. The semiconductor device comprises a first circular sector, a second circular sector, and at least two disconnect regions disposed between the first circular sector and the second circular sector. The first circular sector comprises at least one ESD device. The second circular sector comprises at least one functional device. A single semiconductor device having a circular arrangement or configuration thus has an ESD device and a functional device.

Abstract: An ESD transistor is provided. The ESD transistor includes a collector region on a substrate, a base contact region on the substrate, an emitter region spaced apart from the base contact region, a sink region disposed vertically below the collector region, and a buried layer disposed horizontally under the sink region.

Abstract: The electronic device includes a first (BP) and a second (BN) terminal and electronic means coupled between said two terminals; the electronic means include at least one block (BLC) comprising an MOS transistor (TR) including a parasitic bipolar transistor, the MOS transistor having the drain (D) thereof coupled to the first terminal (BP), the source (S) thereof coupled to the second terminal (BN) and being additionally configured, in the event of a current pulse (IMP) between the two terminals, to operate in a hybrid mode including MOS operation in a subthreshold mode and operation of the parasitic bipolar transistor. The device can comprise two blocks (BLC1, BLC2) connected symmetrically between the two terminals (BP, BN) with a triac (TRC) the trigger of which is connected to the common terminal (BC) of the two blocks.

Abstract: A cell phone has a plurality of interconnected electronic components for performing the electrical functions of the phone. A DC/DC converter provides an operating voltage which is applied to power supply terminals of the plurality of interconnected electronic components. The DC/DC converter uses a monolithic semiconductor device containing a power metal oxide semiconductor field effect transistor (MOSFET) and Schottky diode. The semiconductor device has the lateral diffused MOSFET formed on a surface of the semiconductor device. The MOSFET is formed with a plurality conduction fingers. The Schottky diode is also formed on the surface of the semiconductor device and integrated between the plurality of conduction fingers of the MOSFET. The drain of the MOSFET is connected to the anode of the diode on the surface of the monolithic semiconductor device.