Abstract: Present invention proposes a dramatic improvement of CMOS IC technology by providing high speed bipolar current amplifiers compatible with CMOS technological process while retaining the footprint compatible to one of standard CMOS devices. This invention promises further increase of speed of ICs as well as a reduction of power dissipation.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first epitaxial layer, a first sinker, a first buried layer, a second epitaxial layer, a second sinker and a second buried layer. The first and second epitaxial layers are disposed sequentially on the substrate. The first sinker and the first buried layer define a first area from the first and the second epitaxial layers. The second sinker and the second buried layer define a second area from the second epitaxial layer in the first area. An active device is disposed in the second area. The first buried layer is disposed between the first area and the substrate, and is connected to the first sinker. The second buried layer is disposed between the second area and the first epitaxial layer, and is connected to the second sinker.

Abstract: A high-frequency noise isolation structure and a method for forming the same are provided. The noise isolation structure isolates a first device region and a second device region over a semiconductor substrate. The noise isolation structure preferably includes a sinker region substantially encircling a first device region, a buried layer underlying the first device region and joining the sinker region, a deep guard ring substantially encircling the sinker region, and a deep trench oxide region substantially encircling the sinker region. The isolation structure further includes a wide guard ring between the first and the second device regions. The sinker region and the buried region preferably have a high impurity concentration. Integrated circuits to be noise decoupled are preferably formed in the respective first and second device regions.

Abstract: The present invention can prevent occurrence of an off-leak current in the NMISFETs formed over the Si (110) substrate and having a silicided source/drain region. The semiconductor device includes N channel MISFETs (Metal Insulator Semiconductor Field Effect Transistors) which are formed over a semiconductor substrate having a main surface with a (110) plane orientation and have a source region and a drain region at least one of which has thereover nickel silicide or a nickel alloy silicide. Of these NMISFETs, those having a channel width less than 400 nm are laid out so that their channel length direction is parallel to a <100> crystal orientation.

Abstract: A method of manufacturing a semiconductor device including a complementary metal oxide semiconductor (CMOS) and a bipolar junction transistor (BJT), the method comprising the steps of: forming a gate oxide layer on a substrate having a p-type and an n-type well; removing the gate oxide layer on the p-type well; forming bases on the p-type well; forming a first photosensitive layer pattern that exposes the bases on the substrate; implanting p-type impurity ions into the bases through the first photosensitive layer pattern; removing the first photosensitive layer pattern; forming a second photosensitive layer pattern that exposes the p-type and the n-type wells; and implanting n-type impurity ions into the p-type and the n-type wells through the second photosensitive layer pattern to form an emitter and a collector, respectively, to form the BJT. Therefore, CMOS manufacturing processes are used to form a high frequency BJT having improved frequency and noise characteristics.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may comprise forming an opening in a masking layer, implanting an amorphizing species into a silicon region disposed within the opening, wherein the silicon region comprises a portion of an emitter of a bipolar transistor; and forming a silicide layer on the silicon region.

Abstract: An integrated BiCMOS semiconductor circuit has active moat areas in silicon. The active moat areas include electrically active components of the semiconductor circuit, which comprise active window structures for base and/or emitter windows. The integrated BiCMOS semiconductor circuit has zones where silicon is left to form dummy moat areas which do not include electrically active components, and has isolation trenches to separate the active moat areas from each other and from the dummy moat areas. The dummy moat areas comprise dummy window structures having geometrical dimensions and shapes similar to those of the active window structures for the base and/or emitter windows.

Abstract: This document discusses, among other things, apparatus having at least one CMOS transistor overlying a substrate; and at least one finned bipolar transistor overlying the substrate and methods for making the apparatus.

Abstract: A semiconductor integrated circuit has complementary field-effect transistors, one formed in a semiconductor substrate, the other formed in a well in the substrate, and has four power-supply potentials: two supplied to the sources of the field-effect transistors, one supplied to the substrate, and one supplied to the well. An unwanted pair of parasitic bipolar transistors are formed in association with the field-effect transistors. An intentionally formed bipolar transistor operates in series with one of the unwanted parasitic transistors and as a current mirror for the other unwanted parasitic transistor, limiting the flow of unwanted current through the parasitic bipolar transistors.

Abstract: A bipolar transistor which has a base formed of a combination of shallow and deep acceptors species. Specifically, elements such as Indium, Tellurium, and Gallium are deep acceptors in silicon, and are appropriate for such an application, in combination with boron as the shallow acceptor. The use of a deep acceptor for doping the base of the transistor has the benefit of providing a doping species, which increases in ionization as the temperature rises. At elevated temperatures, the fraction of, for example, indium which is ionized increases and it results in an increased Gummel number, driving down the current gain. In other words, the enhancement of the Gummel number between room temperature and an elevated temperature compensates for the increase in the ratio of collector and base currents due to band gap narrowing effects. Thus, a zero temperature coefficient bipolar transistor is provided.

Abstract: The SOI lateral semiconductor device includes a semiconductor region of a first conductivity type, a buried oxide film layer in the semiconductor region, a thin active layer on the buried oxide film layer, an anode region in the thin active layer, and a drain layer contacting the buried oxide film layer for confining the minority carriers injected from the anode region to the thin active layer within the thin active layer and for forming a structure that sustains a high breakdown voltage. The SOI lateral semiconductor device can provide a high breakdown voltage and low switching losses using the thin buried oxide film, which can be formed by an implanted oxygen (SIMOX) method.

Abstract: The relationship between a distance Ls between a base layer and an n type buffer layer formed on the surface of a drift layer and the thickness t of a semiconductor substrate in contact with the drift layer is set to Ls?t?2×Ls. A loss upon turn-off of a high breakdown voltage semiconductor device can be reduced without deteriorating breakdown voltage characteristics.

Abstract: A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch stop layer with tensile stress is formed over the NMOS transistor, and a second contact etch stop layer with compressive stress is formed over the PMOS transistor and the bipolar transistor, allowing for an enhancement of each device. Another embodiment has, in addition to the stressed contact etch stop layers, strained channel regions in the PMOS transistor and the NMOS transistor, and a strained base in the BJT.

Abstract: An n-type buried diffusion layer is formed on the surface layer of the prescribed area of a p-type silicon substrate, and a p-type first high-concentration isolation diffusion layer is formed in the silicon substrate so as to surround the buried diffusion layer. An n-type epitaxial layer is formed on the silicon substrate, the buried diffusion layer, and the first high-concentration isolation diffusion layer. A p-type second high-concentration isolation diffusion layer is formed in the epitaxial layer on the first high-concentration isolation diffusion layer. A p-type low-concentration isolation diffusion layer for isolating the epitaxial layer into a plurality of island regions is formed in the epitaxial layer on the second high-concentration isolation diffusion layer.

Abstract: A BiCMOS integrated circuit (IC) includes a floating gate-type non-volatile memory (NVM) device that uses the polycrystalline silicon gate of a CMOS FET and the P-base and N-emitter diffusions of a bipolar transistor to provide an isolated P-type body and N-type source/drain diffusions. The P-body diffusion of the NVM device is isolated from a P-substrate by an N-well, thus facilitating the use of reduced positive and negative voltage levels to produce the onset of Fowler-Nordheim tunneling without the need for a triple-well structure. The polysilicon gate structure is formed on a suitable gate oxide over the P-body. The source/drain diffusions, which like the N-emitter diffusions of the bipolar transistor have no LDD, produce a reduced field drop across the gate oxide to allow Fowler-Nordheim tunneling from the source side.

Abstract: Disclosed is a triple well CMOS device structure that addresses the issue of latchup by adding an n+ buried layer not only beneath the p-well to isolate the p-well from the p-substrate but also beneath the n-well. The structure eliminates the spacing issues between the n-well and n+ buried layer by extending the n+ buried layer below the entire device. The structure also addresses the issue of threshold voltage scattering by providing a p+ buried layer below the entire device under the n+ buried layer or below the p-well side of the device only either under or above the n+ buried layer) Latchup robustness can further be improved by incorporating into the device an isolation structure that eliminates lateral pnp, npn, or pnpn devices and/or a sub-collector region between the n+ buried layer and the n-well.

Abstract: A semiconductor device includes an inverter having an NMOSFET and a PMOSFET having sources, drains and gate electrodes respectively, the drains being connected to each other and the gate electrodes being connected to each other, and a pnp bipolar transistor including a collector (C), a base (B) and an emitter (E), the base (B) receiving an output of the inverter.

Abstract: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.

Abstract: A semiconductor device includes a semiconductor layer formed on an insulation layer and having an MOS (Metal Oxide Semiconductor) transistor area and a bi-polar transistor area; an MOS transistor formed in the MOS transistor area; and a bi-polar transistor formed in the bi-polar transistor area. The MOS transistor includes a source area of a second conductive type; a drain area of the second conductive type; and a channel area of a first conductive type. The MOS transistor further includes a gate electrode formed on the channel area with a first oxide layer inbetween. The bi-polar transistor includes a collector area of the second conductive type; an emitter area of the second conductive type; and a base area of the first conductive type. The bi-polar transistor further includes a dummy pattern formed on the base area with a second oxide layer inbetween.

Abstract: A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch stop layer with tensile stress is formed over the NMOS transistor, and a second contact etch stop layer with compressive stress is formed over the PMOS transistor and the bipolar transistor, allowing for an enhancement of each device. Another embodiment has, in addition to the stressed contact etch stop layers, strained channel regions in the PMOS transistor and the NMOS transistor, and a strained base in the BJT.

Abstract: High performance bipolar transistors with raised extrinsic self-aligned base are integrated into a BiCMOS structure containing CMOS devices. By forming pad layers and raising the height of an intrinsic base layer relative to the source and drain of preexisting CMOS devices and by forming an extrinsic base through selective epitaxy, the effect of topographical variations is minimized during a lithographic patterning of the extrinsic base. Also, by not employing any chemical mechanical planarization process during the fabrication of the bipolar structures, complexity of process integration is reduced. Internal spacers or external spacers may be formed to isolate the base from the emitter. The pad layers, the intrinsic base layer, and the extrinsic base layer form a mesa structure with coincident outer sidewall surfaces.

Abstract: A planar combined structure of a bipolar junction transistor (BJT) and n-type/p-type metal semiconductor field-effect transistors (MESFETs) and a method for forming the structure. The n-type GaN MESFET is formed at the same time when an inversion region (an emitter region) of the GaN BJT is formed by an ion implantation or impurity diffusion method by using a particular mask design, while a p-type GaN region is at the same time is formed as the p-type GaN MESFET. Namely, the n-type channel of the n-type MESFET is formed by the ion implantation or impurity diffusion method when the BJT is formed with the same ion implantation or impurity diffusion method performed, while a region of the p-type GaN without being subject to the ion implantation or impurity diffusion method is formed as the p-type MESFET. As such, the BJT is formed currently with the n-type/p-type MESFETs on the same GaN crystal growth layer as a planar structure.

Abstract: According to the invention there is provided a semiconductor device including: at least one cell including a base region of a first conductivity type having disposed therein at least one emitter region of a second conductivity type; a first well region of a second conductivity type; a second well region of a first conductivity type; a drift region of a second conductivity type; a collector region of a first conductivity type; a collector contact; in which each cell is disposed within the first well region and the first well region is disposed within the second well region; the device further including: a first gate in communication with a base region so that a MOSFET channel can be formed between an emitter region and the first well region; and at least one embedded region embedded in the first well region; in which the device is configured such that during operation of the device a depletion region at a junction between the base region and the first well region can extend to a junction between the first well

Abstract: Integrated circuits (ICs) utilize bipolar transistors in electro-static discharge (ESD) protection circuits to shunt discharge currents during ESD events to protect the components in the ICs. Bipolar transistors are subject to non-uniform current crowding across the emitter-base junction during ESD events, which results in less protection for the IC components and degradation of the bipolar transistor. This invention comprises multiple contact islands (126) on the emitter (116) of a bipolar transistor, which act to spread current uniformly across the emitter-base junction. Also included in this invention is segmentation of the emitter diffused region to further improve current uniformity and biasing of the transistor. This invention can be combined with drift region ballasting or back-end ballasting to optimize an ESD protection circuit.

Abstract: To provide a reverse conducting semiconductor device in which an insulated gate bipolar transistor and a free wheeling diode excellent in recovery characteristic are monolithically formed on a substrate, the free wheeling diode including; a second conductive type base layer to constitute the insulated gate bipolar transistor; a first conductive type base layer for constituting the insulated gate bipolar transistor, an anode electrode which is an emitter electrode covering a first conductive type emitter layer and the second conductive type base layer, a cathode electrode which is a collector electrode covering the first conductive type base layer and a second conductive type collector layer formed on the part of the first conductive type base layer, wherein a short lifetime region is formed on a part of the first conductive type base layer.

Abstract: A diode with low substrate current leakage and suitable for BiCMOS process technology. A buried layer is formed on a semiconductor substrate. A connection region and well contact the buried layer. Isolation regions are adjacent to two sides of the buried layer, each deeper than the buried layer. The isolation regions and the buried layer isolate the connection zone and the well from the substrate. The first doped region in the well is a first electrode. The well and the connection region are electrically connected, acting as a second electrode.

Abstract: A semiconductor device includes a first semiconductor layer that is formed on a first insulating layer; a second insulating layer that is formed on the first semiconductor layer; a second semiconductor layer that is formed on the second insulating layer; a first gate electrode that is formed on the second semiconductor layer; first conductive-source and drain layers that are formed in the second semiconductor layer and are arranged at sides of the gate electrode; and a first wiring layer that connects the first gate electrode to the first semiconductor layer.

Abstract: An exemplary method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a P-well and an N-well for high voltage (HV) devices and a first well in a low voltage/medium voltage (LV/MV) region for a logic device, in a semiconductor substrate; simultaneously forming a second well in the LV/MV region for a logic device and a drift region for one of the HV devices using the same mask; and respectively forming gate oxide layers on the semiconductor substrate in the HV/MV/LV regions. According to the present invention, the number of photolithography processes can be reduced by replacing or combining an additional mask for forming an extended drain region of a high voltage depletion-enhancement CMOS (DECMOS) with a mask for forming a typical well of a logic device, so productivity of the total process of the device can be enhanced.

Abstract: A bipolar transistor is provided, which is low in collector-to-emitter saturation voltage, small in size and to be manufactured by a reduced number of processes, and a semiconductor device formed with such a bipolar transistor and a MOS transistor on a same substrate. A high concentration region for reducing the collector-to-emitter saturation voltage VCE(sat) is formed in a manner surrounding a base region of an NPN transistor. This high concentration region is not necessarily formed in such a depth as reaching a buried layer, and can be reduced in the spread in a lateral direction. Because a high concentration region can be formed in a same process as upon forming source and drain regions for an NMOS transistor to be formed together with an NPN transistor on a same silicon substrate, it is possible to omit a diffusion process exclusive for forming a high concentration region and hence to manufacture a semiconductor device through a reduced number of processes.

Abstract: Semiconductor device structures that integrate field effect transistors and bipolar junction transistors on a single substrate, such as a semiconductor-on-insulator substrate, and methods for fabricating such hybrid semiconductor device structures. The field effect and bipolar junction transistors are fabricated using adjacent electrically-isolated semiconductor bodies. During fabrication of the device structures, certain fabrication stages strategically rely on block masks for process isolation. Other fabrication stages are shared during the fabrication process for seamless integration that reduces process complexity.

Abstract: A semiconductor device includes first, second, and third wells. The first well is connected to a pad to which an external pin is connected and includes a first-type diffusion region that receives a well bias voltage. The second well is adjacent to the first well, and includes an insulating region and a second-type diffusion region outside the insulating region. The third well is adjacent to the second well and includes a first-type diffusion region that receives a first voltage. The insulating region inside the second well along with the first-type well diffusion region of the first well constitute a bipolar junction transistor that cuts off current flowing from the first well to the third well.

Abstract: A current-limiting circuit for limiting rising of a current above a predetermined level. The circuit including forward- and reverse-conducting devices, each device including a MOS and a bipolar transistor, wherein ON-resistance of one of the devices is used instead of a current-sensing resistance for another of the devices; and a gate driver connected to the gates of the forward- and reverse-conducting devices for controlling the devices such that a channel of each of the devices simultaneously conducts a current.

Abstract: A semiconductor device is disclosed. In one embodiment the semiconductor device includes a semiconductor body of which is integrated a temperature sensor for measuring the temperature prevailing in the semiconductor body. The temperature sensor has a MOS transistor and a bipolar transistor. The MOS transistor is integrated into the semiconductor body nd configured such that the substhreshold current intensity of the MOS transistor is proportional to the temperature to be measured. The subthreshold current of the MOS transistor is amplified by the bipolar transistor.

Abstract: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.

Abstract: Bipolar junction transistors (BJTs) are provided including silicon carbide (SiC) substrates. An epitaxial SiC base region is provided on the SiC substrate. The epitaxial SiC base region has a first conductivity type. An epitaxial SiC emitter region is also provided on the SiC substrate. The epitaxial SiC emitter region has a second conductivity type, different from the first conductivity type. The epitaxial SiC emitter region has first and second portions. The first portion is provided on the SiC substrate and the second portion is provided on the first portion. The second portion has a higher carrier concentration than the first portion. Related methods of fabricating BJTs are also provided herein.

Abstract: A structure of an electrostatic discharge (ESD) device integrated with a pad is provided. The ESD device is integrated with the pad and formed under the pad. By using the area under the pad, the ESD device does not occupy additional space of an integrated circuit. Furthermore, since the pad is a large, plate, and ideal conductor, the connected pad and the ESD device are capable of distributing current in the ESD device averagely.

Abstract: An improved lateral bipolar junction transistor and a method of forming such a lateral bipolar transistor without added mask in CMOS flow on a p-substrate are disclosed. The CMOS flow includes patterning and n-well implants; pattern and implant pocket implants for core nMOS and MOS; pattern and implants pocket implants I/O nMOS and pMOS; sidewall deposit and etch and then source/drain pattern and implant for nMOS and pMOS. The bipolar transistor is formed by forming emitter and collector contacts by implants used in source/drain regions; forming an emitter by implants done in core pMOS during core pMOS LDD extender; and forming part of an base by pocket implant steps.

Abstract: The present invention includes a bipolar ESD device for protecting an integrated circuit from ESD damage. The bipolar ESD device includes a collector connected to a terminal of the integrated circuit, a floating base, and a grounded emitter. When an ESD pulse hits the terminal of the integrated circuit, the PN junction between the emitter and the base becomes forward biased. The forward biasing of the emitter-base PN junction in turn causes carriers to be injected into the collector-base junction, triggering the bipolar ESD device to turn on to discharge the ESD pulse. The trigger voltage of the bipolar ESD device is a fraction of a breakdown voltage of the collector-base PN junction and can be modified by adjusting a base length of the bipolar ESD device, a junction depth of the collector, or a dopant concentration in the base.

Abstract: An output stage structure includes first and second PMOS transistors and first and second NMOS transistors, wherein the MOS transistors are manufactured with a twin well process. The first PMOS transistor has a source coupled to a supply voltage (VDD), and a gate coupled to the first voltage. The second PMOS transistor has a source coupled to a drain of the first PMOS transistor, a gate coupled to the second voltage, and a drain coupled to an output pad. The first NMOS transistor has a drain coupled to the output pad, and a gate coupled to the third voltage. The second NMOS transistor has a drain coupled to source of the first NMOS transistor, a gate coupled to the fourth voltage, and a source coupled to ground.

Abstract: A driving circuit and a data-line driver is provided which are capable of improving the tolerance to noise between adjacent terminals by using a conventional CMOS process while keeping the chip size small, because a high-density N-diffusion layer (116) is provided in an isolation region (115) to minimize a collector current of a parasitic NPN transistor (102).

Abstract: A horizontal semiconductor device having multiple unit semiconductor elements, each of said unit semiconductor element formed by an IGBT including: a semiconductor substrate of a first conductivity type; a semiconductor region of a second conductivity type formed on the semiconductor substrate; a collector layer of the first conductivity type formed within the semiconductor region; a ring-shaped base layer of the first conductivity type formed within the semiconductor region such that the base layer is off said collector layer but surrounds said collector layer; and a ring-shaped first emitter layer of the second conductivity type formed in said base layer, wherein movement of carriers between the first emitter layer and the collector layer is controlled in a channel region formed in the base layer, and the unit semiconductor elements are disposed adjacent to each other.

Abstract: A ballasting region is placed between the base region and the collector contact of a bipolar junction transistor to relocate a hot spot away from the collector contact of the transistor. Relocating the hot spot away from the collector contact prevents the collector contact from melting during an electrostatic discharge (ESD) pulse.

Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.

Abstract: A method of manufacturing a bipolar-complementary metal oxide semiconductor (BiCMOS) is provided. A gate in a CMOS area and a conductive layer pattern defining an opening, which opens an active region in a bipolar transistor area, are simultaneously formed by patterning a gate conductive layer. Thereafter, bipolar transistor manufacturing processes are performed while CMOS manufacturing processes are performed. Accordingly, the number of masks is decreased, and degradation of device characteristics is prevented.

Abstract: A method of forming a bipolar transistor device, and more particularly a vertical poly-emitter PNP transistor, as part of a BiCMOS type manufacturing process is disclosed. The formation of the PNP transistor during a CMOS/DMOS fabrication process requires merely one additional mask to facilitate formation of a very small emitter in a portion of an N-type surface layer of a double diffused well (DWELL). Unlike conventional PNP transistors, a separate mask is not required to establish the base of the transistor as the transistor base is formed from a portion of the double diffused well and the DWELL includes a P-type body layer formed via implantation through the same opening in the same mask utilized to establish the N-type surface layer of the double diffused well. The base is also thin thus improving the transistor's frequency and gain.

Abstract: A semiconductor device is disclosed that reduces the reverse leakage current caused by reverse bias voltage application and reduces the on-voltage of the IGBT. A two-way switching device using the semiconductor devices is provided, and a method of manufacturing the semiconductor device is disclosed. The reverse blocking IGBT reduces the reverse leakage current and the on-voltage by bringing portions of an n?-type drift region 1 that extend between p-type base regions and an emitter electrode into Schottky contact to form Schottky junctions.

Abstract: A MOS field effect transistor includes an auxiliary diffusion formed in the drain region where the auxiliary diffusion has a conductivity type opposite to the drain region and is electrically shorted to the drain region. The auxiliary diffusion region forms a parasitic bipolar transistor having the effect of reducing substrate conduction caused by a forward biased drain to body junction.

Abstract: A semiconductor memory device includes first and second MOS transistors. The first MOS transistor is formed on a region enclosed by a first element isolating region and includes a first gate insulating film and a first gate electrode. The second MOS transistor is formed on a region enclosed by a second element isolating region and includes a second gate insulating film and a second gate electrode. The upper part of the first and second element isolating regions project from a semiconductor substrate and their corners are curved. The width from the position where the first element isolating region contacts the first gate insulating film to the top surface end of the first element isolating region is equal to the width from the position where the second element isolating region contacts the second gate insulating film to the top surface end of the second element isolating region.

Abstract: The present invention provides a “subcollector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped subcollector. Instead, the inventive vertical SOI BJT uses a back gate-induced, majority carrier accumulation layer as the subcollector when it operates. The SOI substrate is biased such that the accumulation layer is formed at the bottom of the first semiconductor layer. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS. A back-gated CMOS device is also provided.

Abstract: A semiconductor structure with device trench and a semiconductor device in the device trench, that enables realization of high integration, lowered on-resistance, reduction in switching losses and a high operation speed in a semiconductor device provided with a lateral IGBT, and that prevents malfunctions such as latchup when IGBTs or an IGBT and CMOS devices are integrated together. The structure includes an SOI substrate having a supporting substrate, an oxide film and a p?-semiconductor layer. An island-like element-forming region is isolated by a trench isolation region from surroundings. The trench isolation region includes an isolation trench with an insulation film on its inner wall. The device trench is formed in the element-forming region. A gate electrode is formed with a gate insulator film in the device trench. A collector region and an emitter region outside are provided respectively on the bottom and the outside of the device trench.