Abstract: An insulated gate field effect transistor is disclosed. The transistor includes a semi-insulating silicon carbide substrate, an epitaxial layer of silicon carbide layer adjacent the semi-insulating substrate for providing a drift region having a first conductivity type, and source and drain regions in the epitaxial layer having the same conductivity type as the drift region. A channel region is in the epitaxial layer, has portions between the source and the drain regions, and has the opposite conductivity type from the source and drain regions. The transistor includes contacts to the epitaxial layer for the source, drain and channel regions, an insulating layer over the channel region of the epitaxial layer, and a gate contact adjacent the insulating layer and the channel region.

Abstract: Phased array components utilizing two or more different types of semiconductor in one monolithic device are provided. High quality epitaxil layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Abstract: An asymmetrical N-channel IGFET and an asymmetrical P-channel IGFET are disclosed. One or both IGFETs include a lightly doped drain region, heavily doped source and drain regions, and an ultra-heavily doped source region. Preferably, the heavily doped source region and lightly doped drain region provide channel junctions.

Abstract: A collector region is formed on a semiconductor substrate. An emitter electrode, an external base electrode and a gate electrode are formed on the semiconductor substrate. The position of the interface between the gate electrode and the semiconductor substrate is rendered higher than the position of the interface between the external base electrode and the semiconductor substrate. Thus provided is a semiconductor device so improved that dispersion of the withstand voltage of a gate oxide film and dispersion of characteristics such as a threshold voltage and a drain-to-source current are reduced.

Abstract: It is an object to obtain a semiconductor device capable of minimizing an increase in a gate capacity without adversely influencing an operation characteristic and a method of manufacturing the semiconductor device. A first trench (7) and a second trench (11) are formed to reach an upper layer portion of an N− layer (3) through a P base layer (5) and an N layer (4), respectively. In this case, a predetermined number of second trenches (11) are formed between the first trenches (7) and (7). The first trench (7) is provided adjacently to an N+ emitter region (6) and has a gate electrode (9) formed therein. The second trench (11) has a polysilicon region (15) formed therein. The second trench (11) is different from the first trench (7) in that the N+ emitter region (6) is not formed in a vicinal region and the gate electrode (9) is not formed therein.

Abstract: A method of providing a Transient Voltage Suppression (TVS) device is described utilizing a Metal Oxide Semiconductor (MOS) structure and an Insulated Gate Bipolar Transistor (IGBT) structure. The MOS based TVS devices offer reduced leakage current with reduced clamp voltages between 0.5 and 5 volts. Trench MOS based TVS device (72) provides an enhanced gain operation, while device (88) provides a top side drain contact. The high gain MOS based TVS devices provide increased control over clamp voltage variation.

Abstract: Provided is a BiCOMOS semiconductor integrated circuit device which comprises a semiconductor substrate having an insulating layer internally and partially embedded therein and a semiconductor layer deposited on the insulating layer, an insulated gate type transistor formed in the semiconductor layer, a highly-doped collector layer of a bipolar transistor embedded in an insulating-layer-free portion of the semiconductor substrate, and a low-doped collector layer disposed on the highly-doped collector layer of the bipolar transistor, wherein the height level of the lower portion of the low-doped collector layer is below the height level of the lower portion of the insulating layer so as to attain high breakdown voltage and high speed operation of the bipolar transistor.

Abstract: An N type buried layer is buried in a P type silicon substrate. An N type epitaxial layer is formed on this buried layer. A P type intrinsic base region and an extrinsic base region are formed on the surface of the epitaxial layer. An N type emitter region is formed in the intrinsic base region. An emitter electrode is formed to contact the emitter region. A collector plug region is formed in an area separated from the extrinsic base region through a filed insulating film. A cobalt silicide film is formed on the extrinsic base region to surround the emitter electrode. An extrinsic base contact hole is formed at only one side of the emitter electrode. In the semiconductor device, the base resistance Rb and the collector-base capacity Ccb are reduced to make the maximum oscillation frequency fmax sufficiently large.

Abstract: A semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, and a fourth semiconductor region. The first semiconductor region is a collector region of a first conductivity type. The second semiconductor region is provided on the first semiconductor region and serves as a collector region whose impurity concentration is lower than that of the first semiconductor region. The third semiconductor region is provided in the second semiconductor region and serves as a base region of a second conductivity type. The fourth semiconductor region is provided in the third semiconductor region and serves as an emitter region of the first conductivity type. The second semiconductor region is thinner than a depletion layer formed in the collector region when a potential difference between the base region and the emitter region is substantially equal to a potential difference between the collector region and the emitter region.

Abstract: An integrated circuit device includes a semiconductor substrate, an NMOS, a PMOS contiguous with the NMOS, and a composite pnp bipolar junction transistor contiguous with the NMOS. The composite pnp bipolar junction transistor includes a lateral npn bipolar junction transistor having a first current gain, and a lateral pnp bipolar junction transistor having a second current gain, wherein the current gain of the composite pnp bipolar junction transistor equals the first current gain multiplied by the second current gain.

Abstract: A method for fabricating a high speed complementary bipolar/CMOS device is disclosed which enables the forming of a silicon epitaxial layer in a PNP transistor having carbon incorporated therein to suppress boron up-diffusion from lower heavily boron-doped buried layers into upper PNP structures. According to an embodiment of the invention, an epitaxial layer is formed on a P type silicon substrate in which a plurality of P+ buried layer regions, a plurality of N+ buried layer regions, and a P+ field layer region occupying most of the substrate surface are diffused. The substrate is loaded in a reactor with a carrier gas and pre-baked at a temperature of approximately 850° C. for a time. The temperature is then increased to approximately 1050° C. and subjected to a high temperature bake cycle. A thin carbon-doped epitaxial cap layer is deposited on the substrate, which then is subjected to a high temperature gas purge cycle at approximately 1080° C.

Abstract: A bipolar transistor has metal silicide as a base lead-out electrode instead of conventional polysilicon, and the metal silicide film extends to an edge of an etching stopper layer, to reduce an emitter resistance and restrain an occurrence of an emitter plug effect. Such bipolar transistor can be utilized in a CMOS semiconductor device.

Abstract: A semiconductor device and a method of producing the same are disclosed. After boron or similar p-type impurity has been introduced into a polysilicon layer constituting a pMOS gate, annealing can be effected at an optimal temperature low enough to prevent the impurity from entering a silicon substrate via a gate oxide film, e.g., 800° C. or below in the case of boron. This prevents the characteristic of a transistor, e.g., threshold voltage from being varied. Further, in an nMOS gate electrode and source-drain region, the n-type impurity can be provided with a concentration reducing the resistance of a silicide layer. In addition, in the emitter diffusion layer of a bipolar transistor, the concentration of the n-type impurity does not fall and allows a current amplification factor to be increased while allowing an emitter resistance to be reduced.

Abstract: A semiconductor device and a method of producing the same are disclosed. After boron or similar p-type impurity has been introduced into a polysilicon layer constituting a pMOS gate, annealing can be effected at an optimal temperature low enough to prevent the impurity from entering a silicon substrate via a gate oxide film, e.g., 800° C. or below in the case of boron. This prevents the characteristic of a transistor, e.g., threshold voltage from being varied. Further, in an nMOS gate electrode and source-drain region, the n-type impurity can be provided with a concentration reducing the resistance of a silicide layer. In addition, in the emitter diffusion layer of a bipolar transistor, the concentration of the n-type impurity does not fall and allows a current amplification factor to be increased while allowing an emitter resistance to be reduced.

Abstract: The present invention provides a semiconductor integrated circuit device comprising a digital circuit and an analog circuit on a common substrate wherein a substrate effect constant of the analog circuit is at least less than a substrate effect constant of the digital circuit and wherein the analog circuit further comprises a P type polysilicon gate electrode for a nMOSFET and a N type polysilicon gate electrode for a pMOSFET.

Abstract: A circuit incorporated IGBT is provided with a semiconductor substrate having an IGBT area and a circuit area which are adjacent to each other. In a semiconductor layer of one conductivity type in which a circuit element is formed in the circuit area, there is provided another semiconductor layer of another conductivity type which adjoins the circuit element and has an impurity concentration higher than that of the semiconductor layer of the one conductivity type. An electrode contacts the other semiconductor layer and is connected to an electrode of the IGBT. Carriers are ejected from the other semiconductor layer to the electrode of the IGBT, thereby making it possible to prevent an erroneous operation of the circuit.

Abstract: A process for forming isolated active device regions on a silicon substrate comprises the steps of forming at least one trench in a silicon substrate to define at least two active device regions on the substrate to be isolated from each other, depositing an electrically insulative material on the substrate to fill the trench with the material, planarizing the surface of the substrate, performing a masking and etching operation to expose at least one active device region on the substrate, selectively growing a first epitaxial layer of silicon on the exposed active device region, masking the substrate to leave exposed at least one other active device region on the substrate, selectively growing a second epitaxial layer of silicon on the other exposed active device region, the first epitaxial layer and second epitaxial layer being doped with dopant atoms to the same or different dopant concentration to provide, at least two isolated active device regions on the silicon substrate.

Abstract: In a semiconductor device having a bipolar transistor and a MOS transistor on a same semiconductor substrate, a gate electrode of MOS transistor is formed of a first gate electrode layer on a gate oxide film and a second gate electrode layer formed on the first gate electrode layer. Nitrogen is introduced into the first gate electrode layer, and is aggregated around the interface with the gate oxide film. Arsenic is implanted into a second gate electrode layer, and diffused into the second gate electrode layer. An emitter electrode of a bipolar transistor is formed of the same layer with the second gate electrode layer, but nitrogen is not introduced.

Abstract: On one side of a shallow trench isolation region formed on the surface of a p type well, an n type source region is provided while on the other side thereof, an n type drain region is provided so as to sandwich the shallow trench isolation region. In the drain region, a bent portion to allow a breakdown current to flow is provided and connected to a gate of a MOSFET comprising a circuit to be protected. Furthermore, a well contact connected to the source region is formed on the well surface and this well contact is grounded. When a positive high voltage which is higher than a predetermine voltage is applied to the drain region, since electric fields concentrate at the bent portion, a breakdown current flows from this bent portion toward the well contact. Thereafter, a current flows between the source and the drain.

Abstract: A structure of a BiCMOS transistor hindering over-etching of source/drain regions of a MOS transistor and a manufacturing method thereof are provided. A polysilicon film that is to be a gate electrode lower layer of a MOS transistor is formed, and thereon, another polysilicon film that is to be a gate electrode upper layer of the MOS transistor as well as to be a base electrode of a bipolar transistor is formed. Thereafter, etching is conducted to form the polysilicon film to be the base electrode of the bipolar transistor and the gate electrode at the same time. Here, an oxide film shown in FIG. 4 serves as a protective film, thereby hindering over-etching of n type and p type wells to be active regions of respective MOS transistors.

Abstract: A semiconductor device is disclosed involving a semiconductor substrate which contains a buried layer of a predetermined conductivity type as well as trenches deep enough to penetrate through the buried layer for element isolation purposes. Each of the trenches is formed in a boundary area between two regions with a potential difference developing therebetween, and an open-potential area is formed along the trench in the boundary area. This structure prevents leaks from occurring in areas interposed typically between an NPN region and an NMOS region in a BiCMOS semiconductor device, or any other area between two regions subject to two different potential levels.

Abstract: A pnp bipolar junction transistor is formed with improved emitter efficiency by reducing the depth of the p well implant to increase carrier concentration in the emitter and making the emitter junction deeper to increase minority lifetime in the emitter. The high gain BJT is formed without added mask steps to the process flow. A blanket high energy boron implant is used to suppress the isolation leakage in SRAM in the preferred embodiment.

Abstract: Bipolar transistor performance is improved in CMOS process with deep wells by increasing the relative doping density between the emitter and base. To do this, the base dopant concentration is decreased in an npn device by using only the starting p substrate or epitaxial material, and NOT the p-well implant, to form the base*.

Abstract: A bipolar transistor is produced by processes employed in the manufacture of CMOS nonvolatile memory devices, and is part of an integrated circuit. The integrated circuit includes a semiconductor substrate having a first type of conductivity, a PMOS transistor formed in said substrate, an NMOS transistor formed in said substrate, and the bipolar transistor.

Abstract: Bipolar transistors of different designs, particularly designs optimized for different high frequency applications are formed on the same substrate by separate base layer formation processes for epitaxial growth including different material concentration profiles of germanium, boron and/or carbon. Epitaxial growth of individual growth layers by low temperature processes is facilitated by avoiding etching of the silicon substrate including respective collector regions through use of an etch stop that can be etched selectively to silicon. Annealing processes can be performed between growth of respective base layers and/or performed collectively after all transistors are substantially completed.

Abstract: In a bipolar transistor block, a base layer (20a) of SiGe single crystals and an emitter layer (26) of almost 100% of Si single crystals are stacked in this order over a collector diffused layer (9). Over both edges of the base layer (20a), a base undercoat insulating film (5a) and base extended electrodes (22) made of polysilicon are provided. The base layer (20a) has a peripheral portion with a thickness equal to that of the base undercoat insulating film (5a) and a center portion thicker than the peripheral portion. The base undercoat insulating film (5a) and gate insulating films (5b and 5c) for a CMOS block are made of the same oxide film. A stress resulting from a difference in thermal expansion coefficient between the SiGe layer as the base layer and the base undercoat insulating film 5a can be reduced, and a highly reliable BiCMOS device is realized.

Abstract: The present invention relates generally to protection of integrated circuits from electrostatic discharges and more specifically to the use of devices formed in isolated well regions for electrostatic discharge protection. One aspect of the present invention is an ESD protection circuit that includes a first FET and a second FET. The drain of the first FET is coupled to an ESD susceptible node and the source of the first FET is coupled to a first voltage terminal. The gate and a well of the first FET are coupled together and to the drain of the second FET. The source of the second FET is coupled to the first voltage terminal. The gate of the second FET is coupled to a second voltage terminal. The second voltage terminal is connected to a voltage source that is at the first voltage when the circuit is not powered, and at a voltage above the threshold voltage of the second FET when the circuit is powered. The well in which the first FET is formed is electrically isolated from other wells in the substrate.

Abstract: A method for making an isolated NMOS transistor (10) in a BiCMOS process includes forming an N− conductivity type DUF layer (19) in a P conductivity type semiconductor substrate (12), followed by forming alternate contiguous N+ and P conductivity type buried regions (30,26) in the substrate (12). A layer of substantially intrinsic semiconductor material (32) is then formed on the substrate (12) in which alternate and contiguous N and P conductivity type wells (35,36) are formed, respectively above and extending to the N+ and P conductivity type buried regions (30,26). Finally, NMOS source and drain regions (48) are formed in at least one of the P conductivity type wells (35). The method is preferably performed concurrently with the construction of a bipolar transistor structure (11) elsewhere on the substrate (12).

Abstract: Provided is a BiCOMOS semiconductor integrated circuit device which comprises a semiconductor substrate having an insulating layer internally and partially embedded therein and a semiconductor layer deposited on the insulating layer, an insulated gate type transistor formed in the semiconductor layer, a highly-doped collector layer of a bipolar transistor embedded in an insulating-layer-free portion of the semiconductor substrate, and a low-doped collector layer disposed on the highly-doped collector layer of the bipolar transistor, wherein the height level of the lower portion of the low-doped collector layer is below the height level of the lower portion of the insulating layer so as to attain high breakdown voltage and high speed operation of the bipolar transistor.

Abstract: A semiconductor device having a bipolar transistor which is capable of high integration, and a semiconductor device in which the bipolar transistor has good characteristic properties. A process for producing said semiconductor device.

Abstract: The present invention relates to a method of manufacturing a capacitor in a BICMOS integrated circuit manufacturing technology, including the steps of depositing, on a thick oxide region, a polysilicon layer corresponding to a MOS transistor gate electrode; successively depositing a base polysilicon layer and a silicon oxide layer; forming an opening in these last two layers; performing a thermal anneal in an oxidizing atmosphere; depositing a silicon nitride layer and a spacer polysilicon layer; depositing an emitter polysilicon layer; and making a contact with the base polysilicon layer and a contact with the emitter polysilicon layer.

Abstract: A new and improved power MOS transistor having a protective diode with an increased breakdown voltage difference and less sheet resistivity is disclosed. In an up-drain type MOSFET, an n-type well layer has its top surface in which an elongated p-type base region is provided adjacent to a deep n+-type region (drain region). The p-type base region is formed so that it partly overlaps the deep n+ region. A p+-type region (p-type base region) is connected to a source electrode. A surge bypassing diode D1 is thus formed between the source and drain of the MOSFET.

Abstract: There is provided a semiconductor device which causes less element characteristic fluctuation and hardly causes parasitic actions even when a wire comprising a barrier metal made of a titanium material is provided. The semiconductor device comprises a MOS transistor provided on the surface side of a semiconductor substrate, a first silicon oxide film, a silicon nitride film-and a second silicon oxide film-provided on the semiconductor substrate while covering the MOS transistor and a wire having a barrier metal made of a titanium material and provided on the insulating film, and is characterized in that the silicon nitride film covers the MOS transistor and has an opening on an element isolating region for isolating the MOS transistors. The silicon nitride film may be what is formed in one and same process with that of a dielectric film of a capacitor element.

Abstract: A bipolar vertical PNP transistor compatible with CMOS processing and useful in a complementary BiMOS structure is characterized in that it is devoid of an epitaxial layer and employs a high-energy implanted phosphorus layer to provide N-type substrate isolation.

Abstract: A gate electrode layer is formed opposite to a p type backgate region posed between an n type source region and an n type epitaxial region, with a gate insulating layer interposed therebetween. A sidewall insulating layer is formed to cover a sidewall of the gate electrode layer. A p type backgate region has a relatively shallow p type diffusion region and a relatively deep p type diffusion region. The relatively deep p type diffusion region has a portion overlapping the relatively shallow p type diffusion region, and has its end portion at the substrate surface located directly beneath the sidewall insulating layer. Accordingly, a semiconductor device and a manufacturing method thereof that allow easy control of the threshold voltage of a DMOS transistor and facilitate realization of a rapidly operating bipolar transistor are attained.

Abstract: A circuit incorporated IGBT is provided with a semiconductor substrate having an IGBT area and a circuit area which are adjacent to each other. In a semiconductor layer of one conductivity type in which a circuit element is formed in the circuit area, there is provided another semiconductor layer of another conductivity type which adjoins the circuit element and has an impurity concentration higher than that of the semiconductor layer of the one conductivity type. An electrode contacts the other semiconductor layer and is connected to an electrode of the IGBT. Carriers are ejected from the other semiconductor layer to the electrode of the IGBT, thereby making it possible to prevent an erroneous operation of the circuit.

Abstract: The disclosed high voltage device includes a semiconductor substrate, and a first semiconductor layer formed between an underlying first insulating layer and an overlying second insulating layer buried within the semiconductor substrate. The high voltage device includes first and second drift regions formed over the second insulating layer in the semiconductor substrate and spaced apart from each other, an emitter impurity region formed in the first drift region, and a collector impurity region formed in the second drift region. The high voltage device further includes a second semiconductor layer adjacent to and insulated from the collector impurity region, and connected to the first semiconductor layer, and a third semiconductor layer adjacent to and insulated from the emitter impurity region, and connected to the first semiconductor layer.

Abstract: A semiconductor includes a buried conducting layer, such as a buried collector, comprises a trench, the walls of which are covered with a layer of a material in which dopant ions diffuse faster than in monocrystalline silicon. A contact area is doped in close proximity to the trench wall. The dopants will diffuse through the layer and form a low resistance connection to the buried layer. The layer may comprise polysilicon or porous silicon, or a silicide. If the material used in the layer is not in itself conducting, the size of the component may be significantly reduced.

Abstract: An ESD protection circuit that will prevent internal circuits of an integrated circuit is formed on a semiconductor substrate to prevent damage during extreme voltage levels from an ESD voltage source and is connected to an input/output pad. A plurality of drains of multiple MOS FET's is formed within the surface of the semiconductor substrate and are each connected to the input/output pad. A plurality of sources of the multiple MOS FET's is formed within the surface of the semiconductor substrate and are placed at a distance from the plurality of drains and are connected to a ground reference potential. Pairs of the plurality of sources are adjacent to each other. A plurality of isolation regions placed between each source of the pairs of sources and are allowed to float. The multiple MOS FET's have a plurality of parasitic bipolar junction transistors.

Abstract: A BiCMOS integrated circuit is formed with CMOS transistors on an SOI substrate in a silicon layer having a standard thickness of 0.1 &mgr;m to 0.2 &mgr;m and with Bipolar SiGe transistors formed in an epitaxial layer nominally 0.5 &mgr;m thick. The CMOS transistors are formed first with standard processing, then covered with an insulating film. The insulating film is stripped in the bipolar areas and an epitaxial SiGe layer is deposited on the Si substrate. The bipolar transistors are formed using the SiGe epi layer for the base and having an encapsulated structure for device isolation using shallow isolation trenches and the buried oxide.

Abstract: A semiconductor device and a method of manufacturing the same are provided with a silicon region of a first conductivity type, a silicon layer including at least one cavity existing inside the silicon region as a buried layer, and a source/drain region of a second conductivity type different from the first conductivity type selectively formed directly on an upper surface of the silicon region with a bottom surface of the source/drain region located adjacent to an upper surface of the silicon layer such that a depletion layer between the silicon region and the bottom surface of the source/drain region exists inside the silicon layer. With such a structure, a semiconductor device achieves a faster operation and lower power consumption while ensuring stable operation as a MOSFET.

Abstract: A semiconductor device comprising an isolating layer (diffusion layer) having a deep depth which can be produced with improved productivity and a method of the same. The semiconductor device comprises a semiconductor substrate of a first conductivity type; a first diffusion layer of a second conductivity type formed in the semiconductor substrate; a first semiconductor layer formed on the semiconductor substrate; a second diffusion layer of the second conductivity type formed in the first semiconductor layer and connected to the first diffusion layer; and a second semiconductor layer formed on the first semiconductor layer; the second semiconductor layer being electrically isolated from the semiconductor substrate by the first diffusion layer and the second diffusion layer.

Abstract: A semiconductor device which has: a bipolar transistor having a collector region of a second conductivity type formed from the surface of a semiconductor substrate of a first conductivity type, a base region of a first conductivity type formed from the surface of the collector region, and an emitter region of a second conductivity type formed from the surface of the base region; a collector extraction region that is separated by an insulating layer and is formed in the collector region except the base region; a concave portion in the collector extraction region that is formed up to a depth where the collector region has a peak concentration in impurity distribution; and a collector extraction electrode that is connected with the collector region to extract ohmic-connecting to the bottom of the concave portion.

Abstract: The device includes a N+ buried layer in a substrate. A P-well is formed in an epitaxial layer on the buried layer. N-wells surround the P-well are also formed in the epitaxial layer. One of the N-well regions acts as a drain in the structure. A plurality of field oxide regions is formed on the N-well or P-well to define the active area of the device. A gate oxide is formed on the surface of the P-well and the N-well served as the drain. A gate is formed on the gate oxide. Drain contact is formed in the N-well for drain. The source region of the device is formed in the P-well adjacent to the drain. An isolation layer is deposited on the gate. The method includes forming a N+ buried layer in a P substrate. A P epitaxial layer is then formed on the surface of the P substrate. The N-well and P-well are respectively formed in the epitaxial layer by ion implantation and thermally diffusion. A plurality of field oxide (FOX) regions are created to define the active area.

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs which have different threshold voltages and yet have the same channel characteristics. The MOSFETs include gate structures with a polysilicon material. The polysilicon material is implanted with lower concentrations of germanium where lower threshold voltage MOSFETs are required. Over a range of 0-60% concentration of germanium, the threshold voltage can be varied by roughly 240 mV.

Abstract: A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then forming N+ and P+ diffusions in the P and N wells respectively. A unitary pillar of the epitaxial silicon is grown on the substrate having a base at the substrate overlying both the N and P wells and preferably extending at least from said N+ diffusion to said P+ diffusion in said substrate. The pillar terminates at a distal end. An N well is formed on the side of the pillar overlying the N well in the substrate and a P well is formed on the side of the distal end of the pillar overlying the P well on the substrate and abuts the N well in the pillar. A P+ diffusion is formed in the N well in the pillar adjacent the distal end and a N+ diffusion is formed in the P well in the pillar adjacent the distal end.

Abstract: The invention concerns a BI-CMOS process, in which Field-Effect Transistors (FETs) and Bipolar Junction Transistors (BJTs) are manufactured on a common substrate. In several processing steps, FET structures are formed simultaneously with BJT structures. For example, in one step, polysilicon gate electrodes for the FETs and polysilicon emitters for the BJTs are formed simultaneously. In another aspect of the invention, a polysilicon layer is used to reduce channeling which would otherwise occur during an implant step.

Abstract: A process for fabricating a bipolar transistor on a silicon-on-insulator substrate which includes etching a bipolar transistor area into the substrate, wherein the bipolar transistor area has substantially vertical sidewalls and a bottom, and forming a buried collector in bottom of the bipolar transistor area. Polysilicon sidewalls are formed adjacent to the vertical sidewalls in the bipolar transistor area, wherein the polysilicon sidewalls are connected to the buried collector. The polysilicon sidewalls are oxidized to form a layer of oxidized polysilicon. Oxide sidewalls are formed on the oxidized polysilicon sidewalls, and epitaxial silicon is formed to fill the bipolar transistor area. A base and an emitter are formed for the bipolar transistor, within the epitaxial barrier.

Abstract: In a BiCMOS structure, a bipolar transistor is formed inside a the ring of a ring-shaped structure that is made of the same material as the gate electrode, and an insulation film that provides insulation between an emitter electrode and a p-type intrinsic base region is used only inside the ring-shaped structure, so that the insulation film that makes up the side wall insulation film of the CMOS transistor and the insulation film that provides insulation between the bipolar transistor emitter electrode and p-type intrinsic base region are different films.

Abstract: Complementary LDMOS and MOS structures and vertical PNP transistors capable of withstanding a relatively high voltage may be realized in a mixed-technology integrated circuit of the so-called “smart power” type, by forming a phosphorus doped n-region of a similar diffusion profile, respectively in: The drain zone of the n-channel LDMOS transistors, in the body zone of the p-channel LDMOS transistors forming first CMOS structures; in the drain zone of n-channel MOS transistors belonging to second CMOS structures and in a base region near the emitter region of isolated collector, vertical PNP transistors, thus simultaneously achieving the result of increasing the voltage withstanding ability of all these monolithically integrated structures.